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https://github.com/FEX-Emu/linux.git
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Merge branch 'cxgb4-next'
Hariprasad Shenai says:
====================
Misc. fixes for cxgb4
This patch series provides miscelleneous fixes for Chelsio T4/T5 adapters
cxgb4 driver related to SGE and MTU.
Also fixes regression in LSO calcuation path.
("cxgb4: Calculate len properly for LSO path")
The patches series is created against David Miller's 'net-next' tree.
And includes patches on cxgb4 driver.
We would like to request this patch series to get merged via David Miller's
'net-next' tree.
We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
bc0a9a4b0d
@ -556,8 +556,13 @@ struct sge {
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u32 pktshift; /* padding between CPL & packet data */
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u32 fl_align; /* response queue message alignment */
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u32 fl_starve_thres; /* Free List starvation threshold */
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unsigned int starve_thres;
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u8 idma_state[2];
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/* State variables for detecting an SGE Ingress DMA hang */
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unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */
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unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */
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unsigned int idma_state[2]; /* SGE IDMA Hang detect state */
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unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */
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unsigned int egr_start;
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unsigned int ingr_start;
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void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
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@ -1032,4 +1037,5 @@ void t4_db_dropped(struct adapter *adapter);
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int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
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int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
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u32 addr, u32 val);
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void t4_sge_decode_idma_state(struct adapter *adapter, int state);
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#endif /* __CXGB4_H__ */
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@ -93,6 +93,16 @@
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*/
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#define TX_QCHECK_PERIOD (HZ / 2)
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/* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate
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* (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA
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* State Machines in the same state for this amount of time (in HZ) then we'll
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* issue a warning about a potential hang. We'll repeat the warning as the
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* SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till
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* the situation clears. If the situation clears, we'll note that as well.
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*/
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#define SGE_IDMA_WARN_THRESH (1 * HZ)
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#define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD)
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/*
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* Max number of Tx descriptors to be reclaimed by the Tx timer.
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*/
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@ -1041,7 +1051,6 @@ out_free: dev_kfree_skb(skb);
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end = (u64 *)wr + flits;
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len = immediate ? skb->len : 0;
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len += sizeof(*cpl);
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ssi = skb_shinfo(skb);
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if (ssi->gso_size) {
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struct cpl_tx_pkt_lso *lso = (void *)wr;
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@ -1069,6 +1078,7 @@ out_free: dev_kfree_skb(skb);
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q->tso++;
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q->tx_cso += ssi->gso_segs;
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} else {
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len += sizeof(*cpl);
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wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) |
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FW_WR_IMMDLEN(len));
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cpl = (void *)(wr + 1);
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@ -2008,7 +2018,7 @@ irq_handler_t t4_intr_handler(struct adapter *adap)
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static void sge_rx_timer_cb(unsigned long data)
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{
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unsigned long m;
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unsigned int i, cnt[2];
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unsigned int i, idma_same_state_cnt[2];
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struct adapter *adap = (struct adapter *)data;
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struct sge *s = &adap->sge;
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@ -2031,21 +2041,64 @@ static void sge_rx_timer_cb(unsigned long data)
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}
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t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
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cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
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cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
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idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
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idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
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for (i = 0; i < 2; i++)
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if (cnt[i] >= s->starve_thres) {
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if (s->idma_state[i] || cnt[i] == 0xffffffff)
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continue;
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s->idma_state[i] = 1;
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t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
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m = t4_read_reg(adap, SGE_DEBUG_DATA_LOW) >> (i * 16);
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dev_warn(adap->pdev_dev,
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"SGE idma%u starvation detected for "
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"queue %lu\n", i, m & 0xffff);
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} else if (s->idma_state[i])
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s->idma_state[i] = 0;
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for (i = 0; i < 2; i++) {
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u32 debug0, debug11;
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/* If the Ingress DMA Same State Counter ("timer") is less
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* than 1s, then we can reset our synthesized Stall Timer and
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* continue. If we have previously emitted warnings about a
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* potential stalled Ingress Queue, issue a note indicating
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* that the Ingress Queue has resumed forward progress.
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*/
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if (idma_same_state_cnt[i] < s->idma_1s_thresh) {
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if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH)
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CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n",
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i, s->idma_qid[i],
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s->idma_stalled[i]/HZ);
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s->idma_stalled[i] = 0;
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continue;
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}
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/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
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* domain. The first time we get here it'll be because we
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* passed the 1s Threshold; each additional time it'll be
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* because the RX Timer Callback is being fired on its regular
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* schedule.
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*
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* If the stall is below our Potential Hung Ingress Queue
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* Warning Threshold, continue.
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*/
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if (s->idma_stalled[i] == 0)
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s->idma_stalled[i] = HZ;
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else
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s->idma_stalled[i] += RX_QCHECK_PERIOD;
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if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH)
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continue;
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/* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */
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if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0)
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continue;
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/* Read and save the SGE IDMA State and Queue ID information.
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* We do this every time in case it changes across time ...
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*/
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t4_write_reg(adap, SGE_DEBUG_INDEX, 0);
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debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
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s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
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t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
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debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
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s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
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CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
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i, s->idma_qid[i], s->idma_state[i],
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s->idma_stalled[i]/HZ, debug0, debug11);
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t4_sge_decode_idma_state(adap, s->idma_state[i]);
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}
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mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
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}
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@ -2596,11 +2649,19 @@ static int t4_sge_init_soft(struct adapter *adap)
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fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
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fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
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/* We only bother using the Large Page logic if the Large Page Buffer
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* is larger than our Page Size Buffer.
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*/
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if (fl_large_pg <= fl_small_pg)
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fl_large_pg = 0;
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#undef READ_FL_BUF
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/* The Page Size Buffer must be exactly equal to our Page Size and the
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* Large Page Size Buffer should be 0 (per above) or a power of 2.
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*/
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if (fl_small_pg != PAGE_SIZE ||
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(fl_large_pg != 0 && (fl_large_pg < fl_small_pg ||
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(fl_large_pg & (fl_large_pg-1)) != 0))) {
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(fl_large_pg & (fl_large_pg-1)) != 0) {
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dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n",
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fl_small_pg, fl_large_pg);
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return -EINVAL;
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@ -2715,8 +2776,8 @@ static int t4_sge_init_hard(struct adapter *adap)
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int t4_sge_init(struct adapter *adap)
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{
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struct sge *s = &adap->sge;
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u32 sge_control;
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int ret;
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u32 sge_control, sge_conm_ctrl;
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int ret, egress_threshold;
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/*
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* Ingress Padding Boundary and Egress Status Page Size are set up by
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@ -2741,15 +2802,24 @@ int t4_sge_init(struct adapter *adap)
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* SGE's Egress Congestion Threshold. If it isn't, then we can get
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* stuck waiting for new packets while the SGE is waiting for us to
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* give it more Free List entries. (Note that the SGE's Egress
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* Congestion Threshold is in units of 2 Free List pointers.)
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* Congestion Threshold is in units of 2 Free List pointers.) For T4,
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* there was only a single field to control this. For T5 there's the
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* original field which now only applies to Unpacked Mode Free List
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* buffers and a new field which only applies to Packed Mode Free List
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* buffers.
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*/
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s->fl_starve_thres
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= EGRTHRESHOLD_GET(t4_read_reg(adap, SGE_CONM_CTRL))*2 + 1;
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sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL);
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if (is_t4(adap->params.chip))
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egress_threshold = EGRTHRESHOLD_GET(sge_conm_ctrl);
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else
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egress_threshold = EGRTHRESHOLDPACKING_GET(sge_conm_ctrl);
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s->fl_starve_thres = 2*egress_threshold + 1;
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setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
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setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
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s->starve_thres = core_ticks_per_usec(adap) * 1000000; /* 1 s */
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s->idma_state[0] = s->idma_state[1] = 0;
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s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */
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s->idma_stalled[0] = 0;
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s->idma_stalled[1] = 0;
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spin_lock_init(&s->intrq_lock);
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return 0;
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@ -2596,6 +2596,112 @@ int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
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return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
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}
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/**
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* t4_sge_decode_idma_state - decode the idma state
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* @adap: the adapter
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* @state: the state idma is stuck in
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*/
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void t4_sge_decode_idma_state(struct adapter *adapter, int state)
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{
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static const char * const t4_decode[] = {
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"IDMA_IDLE",
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"IDMA_PUSH_MORE_CPL_FIFO",
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"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
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"Not used",
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"IDMA_PHYSADDR_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
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"IDMA_PHYSADDR_SEND_PAYLOAD",
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"IDMA_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATA_FL_PREP",
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"IDMA_FL_REQ_DATA_FL",
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"IDMA_FL_DROP",
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"IDMA_FL_H_REQ_HEADER_FL",
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"IDMA_FL_H_SEND_PCIEHDR",
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"IDMA_FL_H_PUSH_CPL_FIFO",
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"IDMA_FL_H_SEND_CPL",
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"IDMA_FL_H_SEND_IP_HDR_FIRST",
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"IDMA_FL_H_SEND_IP_HDR",
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"IDMA_FL_H_REQ_NEXT_HEADER_FL",
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"IDMA_FL_H_SEND_NEXT_PCIEHDR",
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"IDMA_FL_H_SEND_IP_HDR_PADDING",
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"IDMA_FL_D_SEND_PCIEHDR",
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"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
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"IDMA_FL_D_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_PCIEHDR",
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"IDMA_FL_PUSH_CPL_FIFO",
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"IDMA_FL_SEND_CPL",
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"IDMA_FL_SEND_PAYLOAD_FIRST",
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"IDMA_FL_SEND_PAYLOAD",
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"IDMA_FL_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_NEXT_PCIEHDR",
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"IDMA_FL_SEND_PADDING",
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"IDMA_FL_SEND_COMPLETION_TO_IMSG",
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"IDMA_FL_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATAFL_DONE",
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"IDMA_FL_REQ_HEADERFL_DONE",
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};
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static const char * const t5_decode[] = {
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"IDMA_IDLE",
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"IDMA_ALMOST_IDLE",
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"IDMA_PUSH_MORE_CPL_FIFO",
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"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
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"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
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"IDMA_PHYSADDR_SEND_PAYLOAD",
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"IDMA_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATA_FL",
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"IDMA_FL_DROP",
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"IDMA_FL_DROP_SEND_INC",
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"IDMA_FL_H_REQ_HEADER_FL",
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"IDMA_FL_H_SEND_PCIEHDR",
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"IDMA_FL_H_PUSH_CPL_FIFO",
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"IDMA_FL_H_SEND_CPL",
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"IDMA_FL_H_SEND_IP_HDR_FIRST",
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"IDMA_FL_H_SEND_IP_HDR",
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"IDMA_FL_H_REQ_NEXT_HEADER_FL",
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"IDMA_FL_H_SEND_NEXT_PCIEHDR",
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"IDMA_FL_H_SEND_IP_HDR_PADDING",
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"IDMA_FL_D_SEND_PCIEHDR",
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"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
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"IDMA_FL_D_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_PCIEHDR",
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"IDMA_FL_PUSH_CPL_FIFO",
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"IDMA_FL_SEND_CPL",
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"IDMA_FL_SEND_PAYLOAD_FIRST",
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"IDMA_FL_SEND_PAYLOAD",
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"IDMA_FL_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_NEXT_PCIEHDR",
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"IDMA_FL_SEND_PADDING",
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"IDMA_FL_SEND_COMPLETION_TO_IMSG",
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};
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static const u32 sge_regs[] = {
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SGE_DEBUG_DATA_LOW_INDEX_2,
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SGE_DEBUG_DATA_LOW_INDEX_3,
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SGE_DEBUG_DATA_HIGH_INDEX_10,
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};
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const char **sge_idma_decode;
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int sge_idma_decode_nstates;
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int i;
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if (is_t4(adapter->params.chip)) {
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sge_idma_decode = (const char **)t4_decode;
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sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
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} else {
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sge_idma_decode = (const char **)t5_decode;
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sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
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}
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if (state < sge_idma_decode_nstates)
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CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
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else
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CH_WARN(adapter, "idma state %d unknown\n", state);
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for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
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CH_WARN(adapter, "SGE register %#x value %#x\n",
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sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
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}
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/**
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* t4_fw_hello - establish communication with FW
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* @adap: the adapter
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@ -230,6 +230,12 @@
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#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
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#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
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#define EGRTHRESHOLDPACKING_MASK 0x3fU
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#define EGRTHRESHOLDPACKING_SHIFT 14
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#define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT)
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#define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
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EGRTHRESHOLDPACKING_MASK)
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#define SGE_DBFIFO_STATUS 0x10a4
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#define HP_INT_THRESH_SHIFT 28
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#define HP_INT_THRESH_MASK 0xfU
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@ -278,6 +284,9 @@
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#define SGE_DEBUG_INDEX 0x10cc
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#define SGE_DEBUG_DATA_HIGH 0x10d0
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#define SGE_DEBUG_DATA_LOW 0x10d4
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#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
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#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
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#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
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#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
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#define S_HP_INT_THRESH 28
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