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Merge branch 'dev/removing-s5p6442' into for-next

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This commit is contained in:
Kukjin Kim 2011-05-16 16:29:50 +09:00
commit bd6356bdaf
155 changed files with 1546 additions and 3273 deletions
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2
Documentation/arm/Samsung/Overview.txt
View File

@ -14,7 +14,6 @@ Introduction
- S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
- S3C64XX: S3C6400 and S3C6410
- S5P6440
- S5P6442
- S5PC100
- S5PC110 / S5PV210
@ -36,7 +35,6 @@ Configuration
unifying all the SoCs into one kernel.
s5p6440_defconfig - S5P6440 specific default configuration
s5p6442_defconfig - S5P6442 specific default configuration
s5pc100_defconfig - S5PC100 specific default configuration
s5pc110_defconfig - S5PC110 specific default configuration
s5pv210_defconfig - S5PV210 specific default configuration

4
Documentation/flexible-arrays.txt
View File

@ -66,10 +66,10 @@ trick is to ensure that any needed memory allocations are done before
entering atomic context, using:
int flex_array_prealloc(struct flex_array *array, unsigned int start,
unsigned int end, gfp_t flags);
unsigned int nr_elements, gfp_t flags);
This function will ensure that memory for the elements indexed in the range
defined by start and end has been allocated. Thereafter, a
defined by start and nr_elements has been allocated. Thereafter, a
flex_array_put() call on an element in that range is guaranteed not to
block.

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 39
EXTRAVERSION = -rc6
EXTRAVERSION = -rc7
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

16
arch/arm/Kconfig
View File

@ -736,16 +736,6 @@ config ARCH_S5P64X0
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
config ARCH_S5P6442
bool "Samsung S5P6442"
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5P6442 CPU based systems
config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
@ -995,8 +985,6 @@ endif
source "arch/arm/mach-s5p64x0/Kconfig"
source "arch/arm/mach-s5p6442/Kconfig"
source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
@ -1424,7 +1412,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
@ -2010,7 +1998,7 @@ menu "Power management options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
depends on !ARCH_S5P64X0 && !ARCH_S5P6442
depends on !ARCH_S5P64X0
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y

1
arch/arm/Makefile
View File

@ -178,7 +178,6 @@ machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c24
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4

2
arch/arm/common/Kconfig
View File

@ -7,7 +7,7 @@ config ARM_VIC
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
default 3 if ARCH_S5P6442 || ARCH_S5PC100
default 3 if ARCH_S5PC100
default 2
depends on ARM_VIC
help

48
arch/arm/configs/at91x40_defconfig Normal file
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@ -0,0 +1,48 @@
CONFIG_EXPERIMENTAL=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EMBEDDED=y
# CONFIG_HOTPLUG is not set
# CONFIG_ELF_CORE is not set
# CONFIG_FUTEX is not set
# CONFIG_TIMERFD is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91X40=y
CONFIG_MACH_AT91EB01=y
CONFIG_AT91_EARLY_USART0=y
CONFIG_CPU_ARM7TDMI=y
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x01000000
CONFIG_DRAM_SIZE=0x00400000
CONFIG_FLASH_MEM_BASE=0x01400000
CONFIG_PROCESSOR_ID=0x14000040
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_BINFMT_FLAT=y
# CONFIG_SUSPEND is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_ROMFS_FS=y
# CONFIG_ENABLE_MUST_CHECK is not set

65
arch/arm/configs/s5p6442_defconfig
View File

@ -1,65 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_S5P6442=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6442=y
CONFIG_CPU_32v6K=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
CONFIG_FPE_NWFPE=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y

8
arch/arm/kernel/ptrace.c
View File

@ -767,12 +767,20 @@ long arch_ptrace(struct task_struct *child, long request,
#ifdef CONFIG_HAVE_HW_BREAKPOINT
case PTRACE_GETHBPREGS:
if (ptrace_get_breakpoints(child) < 0)
return -ESRCH;
ret = ptrace_gethbpregs(child, addr,
(unsigned long __user *)data);
ptrace_put_breakpoints(child);
break;
case PTRACE_SETHBPREGS:
if (ptrace_get_breakpoints(child) < 0)
return -ESRCH;
ret = ptrace_sethbpregs(child, addr,
(unsigned long __user *)data);
ptrace_put_breakpoints(child);
break;
#endif

1
arch/arm/mach-at91/Kconfig
View File

@ -83,6 +83,7 @@ config ARCH_AT91CAP9
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL
select HAVE_NET_MACB
config ARCH_AT572D940HF
bool "AT572D940HF"

7
arch/arm/mach-at91/board-eb01.c
View File

@ -30,6 +30,11 @@
#include <mach/board.h>
#include "generic.h"
static void __init at91eb01_init_irq(void)
{
at91x40_init_interrupts(NULL);
}
static void __init at91eb01_map_io(void)
{
at91x40_initialize(40000000);
@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void)
MACHINE_START(AT91EB01, "Atmel AT91 EB01")
/* Maintainer: Greg Ungerer <gerg@snapgear.com> */
.timer = &at91x40_timer,
.init_irq = at91x40_init_interrupts,
.init_irq = at91eb01_init_irq,
.map_io = at91eb01_map_io,
MACHINE_END

28
arch/arm/mach-at91/include/mach/cpu.h
View File

@ -27,6 +27,7 @@
#define ARCH_ID_AT91SAM9G45 0x819b05a0
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_AT91CAP9 0x039A03A0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void)
#define ARCH_EXID_AT91SAM9G46 0x00000003
#define ARCH_EXID_AT91SAM9G45 0x00000004
#define ARCH_EXID_AT91SAM9G15 0x00000000
#define ARCH_EXID_AT91SAM9G35 0x00000001
#define ARCH_EXID_AT91SAM9X35 0x00000002
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
static inline unsigned long at91_exid_identify(void)
{
return at91_sys_read(AT91_DBGU_EXID);
@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void)
#define cpu_is_at91sam9m11() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9X5
#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
#else
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
#define cpu_is_at91sam9g35() (0)
#define cpu_is_at91sam9x35() (0)
#define cpu_is_at91sam9g25() (0)
#define cpu_is_at91sam9x25() (0)
#endif
#ifdef CONFIG_ARCH_AT91CAP9
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)

25
arch/arm/mach-s5p6442/Kconfig
View File

@ -1,25 +0,0 @@
# arch/arm/mach-s5p6442/Kconfig
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
# Configuration options for the S5P6442
if ARCH_S5P6442
config CPU_S5P6442
bool
select S3C_PL330_DMA
help
Enable S5P6442 CPU support
config MACH_SMDK6442
bool "SMDK6442"
select CPU_S5P6442
select S3C_DEV_WDT
help
Machine support for Samsung SMDK6442
endif

24
arch/arm/mach-s5p6442/Makefile
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@ -1,24 +0,0 @@
# arch/arm/mach-s5p6442/Makefile
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5P6442 system
obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o

2
arch/arm/mach-s5p6442/Makefile.boot
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@ -1,2 +0,0 @@
zreladdr-y := 0x20008000
params_phys-y := 0x20000100

420
arch/arm/mach-s5p6442/clock.c
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@ -1,420 +0,0 @@
/* linux/arch/arm/mach-s5p6442/clock.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6442.h>
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};
/* Possible clock sources for ARM Mux */
static struct clk *clk_src_arm_list[] = {
[1] = &clk_mout_apll.clk,
[2] = &clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_arm = {
.sources = clk_src_arm_list,
.nr_sources = ARRAY_SIZE(clk_src_arm_list),
};
static struct clksrc_clk clk_mout_arm = {
.clk = {
.name = "mout_arm",
.id = -1,
},
.sources = &clk_src_arm,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
};
static struct clk clk_dout_a2m = {
.name = "dout_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
};
/* Possible clock sources for D0 Mux */
static struct clk *clk_src_d0_list[] = {
[1] = &clk_mout_mpll.clk,
[2] = &clk_dout_a2m,
};
static struct clksrc_sources clk_src_d0 = {
.sources = clk_src_d0_list,
.nr_sources = ARRAY_SIZE(clk_src_d0_list),
};
static struct clksrc_clk clk_mout_d0 = {
.clk = {
.name = "mout_d0",
.id = -1,
},
.sources = &clk_src_d0,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
};
static struct clk clk_dout_apll = {
.name = "dout_apll",
.id = -1,
.parent = &clk_mout_arm.clk,
};
/* Possible clock sources for D0SYNC Mux */
static struct clk *clk_src_d0sync_list[] = {
[1] = &clk_mout_d0.clk,
[2] = &clk_dout_apll,
};
static struct clksrc_sources clk_src_d0sync = {
.sources = clk_src_d0sync_list,
.nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
};
static struct clksrc_clk clk_mout_d0sync = {
.clk = {
.name = "mout_d0sync",
.id = -1,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
};
/* Possible clock sources for D1 Mux */
static struct clk *clk_src_d1_list[] = {
[1] = &clk_mout_mpll.clk,
[2] = &clk_dout_a2m,
};
static struct clksrc_sources clk_src_d1 = {
.sources = clk_src_d1_list,
.nr_sources = ARRAY_SIZE(clk_src_d1_list),
};
static struct clksrc_clk clk_mout_d1 = {
.clk = {
.name = "mout_d1",
.id = -1,
},
.sources = &clk_src_d1,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
};
/* Possible clock sources for D1SYNC Mux */
static struct clk *clk_src_d1sync_list[] = {
[1] = &clk_mout_d1.clk,
[2] = &clk_dout_apll,
};
static struct clksrc_sources clk_src_d1sync = {
.sources = clk_src_d1sync_list,
.nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
};
static struct clksrc_clk clk_mout_d1sync = {
.clk = {
.name = "mout_d1sync",
.id = -1,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
};
static struct clk clk_hclkd0 = {
.name = "hclkd0",
.id = -1,
.parent = &clk_mout_d0sync.clk,
};
static struct clk clk_hclkd1 = {
.name = "hclkd1",
.id = -1,
.parent = &clk_mout_d1sync.clk,
};
static struct clk clk_pclkd0 = {
.name = "pclkd0",
.id = -1,
.parent = &clk_hclkd0,
};
static struct clk clk_pclkd1 = {
.name = "pclkd1",
.id = -1,
.parent = &clk_hclkd1,
};
int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
}
int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "dout_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
}, {
.clk = {
.name = "dout_apll",
.id = -1,
.parent = &clk_mout_arm.clk,
},
.sources = &clk_src_arm,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
}, {
.clk = {
.name = "hclkd1",
.id = -1,
.parent = &clk_mout_d1sync.clk,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "hclkd0",
.id = -1,
.parent = &clk_mout_d0sync.clk,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "pclkd0",
.id = -1,
.parent = &clk_hclkd0,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
}, {
.clk = {
.name = "pclkd1",
.id = -1,
.parent = &clk_hclkd1,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
}
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_mpll,
&clk_mout_epll,
&clk_mout_arm,
&clk_mout_d0,
&clk_mout_d0sync,
&clk_mout_d1,
&clk_mout_d1sync,
};
void __init_or_cpufreq s5p6442_setup_clocks(void)
{
struct clk *pclkd0_clk;
struct clk *pclkd1_clk;
unsigned long xtal;
unsigned long arm;
unsigned long hclkd0 = 0;
unsigned long hclkd1 = 0;
unsigned long pclkd0 = 0;
unsigned long pclkd1 = 0;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
xtal = clk_get_rate(&clk_xtal);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
apll, mpll, epll);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
arm = clk_get_rate(&clk_dout_apll);
hclkd0 = clk_get_rate(&clk_hclkd0);
hclkd1 = clk_get_rate(&clk_hclkd1);
pclkd0_clk = clk_get(NULL, "pclkd0");
BUG_ON(IS_ERR(pclkd0_clk));
pclkd0 = clk_get_rate(pclkd0_clk);
clk_put(pclkd0_clk);
pclkd1_clk = clk_get(NULL, "pclkd1");
BUG_ON(IS_ERR(pclkd1_clk));
pclkd1 = clk_get_rate(pclkd1_clk);
clk_put(pclkd1_clk);
printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
hclkd0, hclkd1, pclkd0, pclkd1);
/* For backward compatibility */
clk_f.rate = arm;
clk_h.rate = hclkd1;
clk_p.rate = pclkd1;
clk_pclkd0.rate = pclkd0;
clk_pclkd1.rate = pclkd1;
}
static struct clk init_clocks_off[] = {
{
.name = "pdma",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
},
};
static struct clk init_clocks[] = {
{
.name = "systimer",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<23),
},
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
&clk_mout_epll.clk,
&clk_mout_d0.clk,
&clk_mout_d0sync.clk,
&clk_mout_d1.clk,
&clk_mout_d1sync.clk,
&clk_hclkd0,
&clk_pclkd0,
&clk_hclkd1,
&clk_pclkd1,
};
void __init s5p6442_register_clocks(void)
{
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_pwmclk_init();
}

143
arch/arm/mach-s5p6442/cpu.c
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@ -1,143 +0,0 @@
/* linux/arch/arm/mach-s5p6442/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s5p6442.h>
/* Initial IO mappings */
static struct map_desc s5p6442_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5P6442_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5P6442_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5P6442_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5P6442_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}
};
static void s5p6442_idle(void)
{
if (!need_resched())
cpu_do_idle();
local_irq_enable();
}
/*
* s5p6442_map_io
*
* register the standard cpu IO areas
*/
void __init s5p6442_map_io(void)
{
iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc));
}
void __init s5p6442_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5p6442_register_clocks();
s5p6442_setup_clocks();
}
void __init s5p6442_init_irq(void)
{
/* S5P6442 supports 3 VIC */
u32 vic[3];
/* VIC0, VIC1, and VIC2: some interrupt reserved */
vic[0] = 0x7fefffff;
vic[1] = 0X7f389c81;
vic[2] = 0X1bbbcfff;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
struct sysdev_class s5p6442_sysclass = {
.name = "s5p6442-core",
};
static struct sys_device s5p6442_sysdev = {
.cls = &s5p6442_sysclass,
};
static int __init s5p6442_core_init(void)
{
return sysdev_class_register(&s5p6442_sysclass);
}
core_initcall(s5p6442_core_init);
int __init s5p6442_init(void)
{
printk(KERN_INFO "S5P6442: Initializing architecture\n");
/* set idle function */
pm_idle = s5p6442_idle;
return sysdev_register(&s5p6442_sysdev);
}

217
arch/arm/mach-s5p6442/dev-audio.c
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/* linux/arch/arm/mach-s5p6442/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
unsigned int base;
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
base = S5P6442_GPC1(0);
break;
case 0:
base = S5P6442_GPC0(0);
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static const char *rclksrc_v35[] = {
[0] = "busclk",
[1] = "i2sclk",
};
static struct s3c_audio_pdata i2sv35_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
.src_clk = rclksrc_v35,
},
},
};
static struct resource s5p6442_iis0_resource[] = {
[0] = {
.start = S5P6442_PA_I2S0,
.end = S5P6442_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DMACH_I2S0S_TX,
.end = DMACH_I2S0S_TX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
.resource = s5p6442_iis0_resource,
.dev = {
.platform_data = &i2sv35_pdata,
},
};
static const char *rclksrc_v3[] = {
[0] = "iis",
[1] = "sclk_audio",
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
.type = {
.i2s = {
.src_clk = rclksrc_v3,
},
},
};
static struct resource s5p6442_iis1_resource[] = {
[0] = {
.start = S5P6442_PA_I2S1,
.end = S5P6442_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S1_TX,
.end = DMACH_I2S1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S1_RX,
.end = DMACH_I2S1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
.resource = s5p6442_iis1_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S5P6442_GPC0(0);
break;
case 1:
base = S5P6442_GPC1(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6442_pcm_cfg_gpio,
};
static struct resource s5p6442_pcm0_resource[] = {
[0] = {
.start = S5P6442_PA_PCM0,
.end = S5P6442_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
.resource = s5p6442_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5p6442_pcm1_resource[] = {
[0] = {
.start = S5P6442_PA_PCM1,
.end = S5P6442_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM1_TX,
.end = DMACH_PCM1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM1_RX,
.end = DMACH_PCM1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
.resource = s5p6442_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};

121
arch/arm/mach-s5p6442/dev-spi.c
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/* linux/arch/arm/mach-s5p6442/dev-spi.c
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/spi-clocks.h>
#include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h>
static char *spi_src_clks[] = {
[S5P6442_SPI_SRCCLK_PCLK] = "pclk",
[S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
};
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
static struct resource s5p6442_spi0_resource[] = {
[0] = {
.start = S5P6442_PA_SPI,
.end = S5P6442_PA_SPI + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI0_TX,
.end = DMACH_SPI0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI0_RX,
.end = DMACH_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI0,
.end = IRQ_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
.cfg_gpio = s5p6442_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15,
};
static u64 spi_dmamask = DMA_BIT_MASK(32);
struct platform_device s5p6442_device_spi = {
.name = "s3c64xx-spi",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_spi0_resource),
.resource = s5p6442_spi0_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_spi0_pdata,
},
};
void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
{
struct s3c64xx_spi_info *pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0
|| src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
return;
}
switch (cntrlr) {
case 0:
pd = &s5p6442_spi0_pdata;
break;
default:
printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
__func__, cntrlr);
return;
}
pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
}

105
arch/arm/mach-s5p6442/dma.c
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6442_pdma_resource[] = {
[0] = {
.start = S5P6442_PA_PDMA,
.end = S5P6442_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA,
.end = IRQ_PDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_MAX,
[7] = DMACH_MAX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_PCM0_RX,
[21] = DMACH_PCM0_TX,
[22] = DMACH_PCM1_RX,
[23] = DMACH_PCM1_TX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MSM_REQ0,
[28] = DMACH_MSM_REQ1,
[29] = DMACH_MSM_REQ2,
[30] = DMACH_MSM_REQ3,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6442_device_pdma = {
.name = "s3c-pl330",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
.resource = s5p6442_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_pdma_pdata,
},
};
static struct platform_device *s5p6442_dmacs[] __initdata = {
&s5p6442_device_pdma,
};
static int __init s5p6442_dma_init(void)
{
platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
return 0;
}
arch_initcall(s5p6442_dma_init);

35
arch/arm/mach-s5p6442/include/mach/debug-macro.S
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/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
.macro addruart, rp, rv
ldr \rp, = S3C_PA_UART
ldr \rv, = S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>

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arch/arm/mach-s5p6442/include/mach/dma.h
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */

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arch/arm/mach-s5p6442/include/mach/entry-macro.S
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/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Low-level IRQ helper macros for the Samsung S5P6442
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, # S5P_IRQ_OFFSET + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
@ otherwise try vic2
addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm

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arch/arm/mach-s5p6442/include/mach/gpio.h
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/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5P6442_GPIO_A0_NR (8)
#define S5P6442_GPIO_A1_NR (2)
#define S5P6442_GPIO_B_NR (4)
#define S5P6442_GPIO_C0_NR (5)
#define S5P6442_GPIO_C1_NR (5)
#define S5P6442_GPIO_D0_NR (2)
#define S5P6442_GPIO_D1_NR (6)
#define S5P6442_GPIO_E0_NR (8)
#define S5P6442_GPIO_E1_NR (5)
#define S5P6442_GPIO_F0_NR (8)
#define S5P6442_GPIO_F1_NR (8)
#define S5P6442_GPIO_F2_NR (8)
#define S5P6442_GPIO_F3_NR (6)
#define S5P6442_GPIO_G0_NR (7)
#define S5P6442_GPIO_G1_NR (7)
#define S5P6442_GPIO_G2_NR (7)
#define S5P6442_GPIO_H0_NR (8)
#define S5P6442_GPIO_H1_NR (8)
#define S5P6442_GPIO_H2_NR (8)
#define S5P6442_GPIO_H3_NR (8)
#define S5P6442_GPIO_J0_NR (8)
#define S5P6442_GPIO_J1_NR (6)
#define S5P6442_GPIO_J2_NR (8)
#define S5P6442_GPIO_J3_NR (8)
#define S5P6442_GPIO_J4_NR (5)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5P6442_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
S5P6442_GPIO_A0_START = 0,
S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
};
/* S5P6442 GPIO number definitions. */
#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr))
#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr))
#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr))
#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr))
#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr))
#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr))
#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr))
#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr))
#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr))
#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr))
#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr))
#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr))
#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr))
#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr))
#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr))
#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr))
#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr))
#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr))
#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr))
#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr))
#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr))
#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr))
#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr))
#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr))
#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr))
/* the end of the S5P6442 specific gpios */
#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
#define S3C_GPIO_END S5P6442_GPIO_END
/* define the number of gpios we need to the one after the GPJ4() range */
#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

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arch/arm/mach-s5p6442/include/mach/hardware.h
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/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/mach-s5p6442/include/mach/io.h
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/* arch/arm/mach-s5p6442/include/mach/io.h
*
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for S5P6442
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif

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arch/arm/mach-s5p6442/include/mach/irqs.h
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/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
/* VIC0 */
#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
#define IRQ_BATF S5P_IRQ_VIC0(17)
#define IRQ_MDMA S5P_IRQ_VIC0(18)
#define IRQ_PDMA S5P_IRQ_VIC0(19)
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
#define IRQ_WDT S5P_IRQ_VIC0(27)
#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
/* VIC1 */
#define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_ONENAND S5P_IRQ_VIC1(7)
#define IRQ_UART0 S5P_IRQ_VIC1(10)
#define IRQ_UART1 S5P_IRQ_VIC1(11)
#define IRQ_UART2 S5P_IRQ_VIC1(12)
#define IRQ_SPI0 S5P_IRQ_VIC1(15)
#define IRQ_IIC S5P_IRQ_VIC1(19)
#define IRQ_IIC1 S5P_IRQ_VIC1(20)
#define IRQ_IIC2 S5P_IRQ_VIC1(21)
#define IRQ_OTG S5P_IRQ_VIC1(24)
#define IRQ_MSM S5P_IRQ_VIC1(25)
#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
#define IRQ_COMMRX S5P_IRQ_VIC1(29)
#define IRQ_COMMTX S5P_IRQ_VIC1(30)
/* VIC2 */
#define IRQ_LCD0 S5P_IRQ_VIC2(0)
#define IRQ_LCD1 S5P_IRQ_VIC2(1)
#define IRQ_LCD2 S5P_IRQ_VIC2(2)
#define IRQ_LCD3 S5P_IRQ_VIC2(3)
#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
#define IRQ_JPEG S5P_IRQ_VIC2(8)
#define IRQ_3D S5P_IRQ_VIC2(10)
#define IRQ_Mixer S5P_IRQ_VIC2(11)
#define IRQ_MFC S5P_IRQ_VIC2(14)
#define IRQ_TVENC S5P_IRQ_VIC2(15)
#define IRQ_I2S0 S5P_IRQ_VIC2(16)
#define IRQ_I2S1 S5P_IRQ_VIC2(17)
#define IRQ_RP S5P_IRQ_VIC2(19)
#define IRQ_PCM0 S5P_IRQ_VIC2(20)
#define IRQ_PCM1 S5P_IRQ_VIC2(21)
#define IRQ_ADC S5P_IRQ_VIC2(23)
#define IRQ_PENDN S5P_IRQ_VIC2(24)
#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
#define IRQ_VIC_END S5P_IRQ_VIC2(31)
#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT(31) + 1)
#endif /* __ASM_ARCH_IRQS_H */

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arch/arm/mach-s5p6442/include/mach/map.h
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/* linux/arch/arm/mach-s5p6442/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P6442_PA_SDRAM 0x20000000
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
#define S5P6442_PA_CHIPID 0xE0000000
#define S5P6442_PA_SYSCON 0xE0100000
#define S5P6442_PA_GPIO 0xE0200000
#define S5P6442_PA_VIC0 0xE4000000
#define S5P6442_PA_VIC1 0xE4100000
#define S5P6442_PA_VIC2 0xE4200000
#define S5P6442_PA_SROMC 0xE7000000
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER 0xEA000000
#define S5P6442_PA_SYSTIMER 0xEA100000
#define S5P6442_PA_WATCHDOG 0xEA200000
#define S5P6442_PA_UART 0xEC000000
#define S5P6442_PA_IIC0 0xEC100000
#define S5P6442_PA_SPI 0xEC300000
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* Compatibiltiy Defines */
#define S3C_PA_IIC S5P6442_PA_IIC0
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P_PA_TIMER S5P6442_PA_TIMER
/* UART */
#define S3C_PA_UART S5P6442_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

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arch/arm/mach-s5p6442/include/mach/memory.h
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/* linux/arch/arm/mach-s5p6442/include/mach/memory.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PLAT_PHYS_OFFSET UL(0x20000000)
#define CONSISTENT_DMA_SIZE SZ_8M
#endif /* __ASM_ARCH_MEMORY_H */

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arch/arm/mach-s5p6442/include/mach/pwm-clock.h
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/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5P6442 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */

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arch/arm/mach-s5p6442/include/mach/regs-clock.h
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/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
#define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x108)
#define S5P_EPLL_CON S5P_CLKREG(0x110)
#define S5P_VPLL_CON S5P_CLKREG(0x120)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
/* CLK_OUT */
#define S5P_CLK_OUT_SHIFT (12)
#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT)
#define S5P_CLK_OUT S5P_CLKREG(0x500)
#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000)
#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004)
#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100)
#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104)
#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
/* Register Bit definition */
#define S5P_EPLL_EN (1<<31)
#define S5P_EPLL_MASK 0xffffffff
#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
/* CLKDIV0 */
#define S5P_CLKDIV0_APLL_SHIFT (0)
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
#define S5P_CLKDIV0_A2M_SHIFT (4)
#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
#define S5P_CLKDIV0_D0CLK_SHIFT (16)
#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
#define S5P_CLKDIV0_P0CLK_SHIFT (20)
#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
#define S5P_CLKDIV0_D1CLK_SHIFT (24)
#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
#define S5P_CLKDIV0_P1CLK_SHIFT (28)
#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
/* Clock MUX status Registers */
#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0)
#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4)
#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8)
#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12)
#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16)
#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20)
#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24)
#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24)
#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28)
#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

19
arch/arm/mach-s5p6442/include/mach/regs-irq.h
View File

@ -1,19 +0,0 @@
/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <asm/hardware/vic.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_REGS_IRQ_H */

17
arch/arm/mach-s5p6442/include/mach/spi-clocks.h
View File

@ -1,17 +0,0 @@
/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __S5P6442_PLAT_SPI_CLKS_H
#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
#define S5P6442_SPI_SRCCLK_PCLK 0
#define S5P6442_SPI_SRCCLK_SCLK 1
#endif /* __S5P6442_PLAT_SPI_CLKS_H */

23
arch/arm/mach-s5p6442/include/mach/system.h
View File

@ -1,23 +0,0 @@
/* linux/arch/arm/mach-s5p6442/include/mach/system.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - system support header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
#include <plat/system-reset.h>
static void arch_idle(void)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_SYSTEM_H */

26
arch/arm/mach-s5p6442/include/mach/tick.h
View File

@ -1,26 +0,0 @@
/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/tick.h
*
* S5P6442 - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_TICK_H */

24
arch/arm/mach-s5p6442/include/mach/timex.h
View File

@ -1,24 +0,0 @@
/* arch/arm/mach-s5p6442/include/mach/timex.h
*
* Copyright (c) 2003-2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S5P6442 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
* a variable is useless. It seems as long as we make our timers an
* exact multiple of HZ, any value that makes a 1->1 correspondence
* for the time conversion functions to/from jiffies is acceptable.
*/
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */

24
arch/arm/mach-s5p6442/include/mach/uncompress.h
View File

@ -1,24 +0,0 @@
/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */

17
arch/arm/mach-s5p6442/include/mach/vmalloc.h
View File

@ -1,17 +0,0 @@
/* arch/arm/mach-s5p6442/include/mach/vmalloc.h
*
* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S5P6442 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

44
arch/arm/mach-s5p6442/init.c
View File

@ -1,44 +0,0 @@
/* linux/arch/arm/mach-s5p6442/s5p6442-init.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s5p6442.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = {
[0] = {
.name = "pclk",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->clocks = s5p6442_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks);
}
}
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}

102
arch/arm/mach-s5p6442/mach-smdk6442.c
View File

@ -1,102 +0,0 @@
/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/i2c.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <plat/s5p6442.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
};
static struct platform_device *smdk6442_devices[] __initdata = {
&s3c_device_i2c0,
&samsung_asoc_dma,
&s5p6442_device_iis0,
&s3c_device_wdt,
};
static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("wm8580", 0x1b), },
};
static void __init smdk6442_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs));
}
static void __init smdk6442_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, smdk6442_i2c_devs0,
ARRAY_SIZE(smdk6442_i2c_devs0));
platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
}
MACHINE_START(SMDK6442, "SMDK6442")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = s5p6442_init_irq,
.map_io = smdk6442_map_io,
.init_machine = smdk6442_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END

28
arch/arm/mach-s5p6442/setup-i2c0.c
View File

@ -1,28 +0,0 @@
/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

2
arch/arm/plat-s5p/Kconfig
View File

@ -7,7 +7,7 @@
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
default y
select ARM_VIC if !ARCH_EXYNOS4
select ARM_GIC if ARCH_EXYNOS4

10
arch/arm/plat-s5p/cpu.c
View File

@ -21,7 +21,6 @@
#include <plat/cpu.h>
#include <plat/s5p6440.h>
#include <plat/s5p6442.h>
#include <plat/s5p6450.h>
#include <plat/s5pc100.h>
#include <plat/s5pv210.h>
@ -30,7 +29,6 @@
/* table of supported CPUs */
static const char name_s5p6440[] = "S5P6440";
static const char name_s5p6442[] = "S5P6442";
static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
@ -45,14 +43,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = s5p6440_init_uarts,
.init = s5p64x0_init,
.name = name_s5p6440,
}, {
.idcode = 0x36442000,
.idmask = 0xfffff000,
.map_io = s5p6442_map_io,
.init_clocks = s5p6442_init_clocks,
.init_uarts = s5p6442_init_uarts,
.init = s5p6442_init,
.name = name_s5p6442,
}, {
.idcode = 0x36450000,
.idmask = 0xfffff000,

33
arch/arm/plat-s5p/include/plat/s5p6442.h
View File

@ -1,33 +0,0 @@
/* arch/arm/plat-s5p/include/plat/s5p6442.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Header file for s5p6442 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S5P6442 related SoCs */
extern void s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s5p6442_register_clocks(void);
extern void s5p6442_setup_clocks(void);
#ifdef CONFIG_CPU_S5P6442
extern int s5p6442_init(void);
extern void s5p6442_init_irq(void);
extern void s5p6442_map_io(void);
extern void s5p6442_init_clocks(int xtal);
#define s5p6442_init_uarts s5p6442_common_init_uarts
#else
#define s5p6442_init_clocks NULL
#define s5p6442_init_uarts NULL
#define s5p6442_map_io NULL
#define s5p6442_init NULL
#endif

1
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -80,7 +80,6 @@ extern struct sysdev_class s3c2443_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
extern struct sysdev_class s5p64x0_sysclass;
extern struct sysdev_class s5p6442_sysclass;
extern struct sysdev_class s5pv210_sysclass;
extern struct sysdev_class exynos4_sysclass;

2
arch/arm/plat-samsung/include/plat/debug-macro.S
View File

@ -11,7 +11,7 @@
#include <plat/regs-serial.h>
/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */
/* The S5PV210/S5PC110 implementations are as belows. */
.macro fifo_level_s5pv210 rd, rx
ldr \rd, [ \rx, # S3C2410_UFSTAT ]

6
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -110,12 +110,6 @@ extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_ahci;
extern struct platform_device s5p6442_device_pcm0;
extern struct platform_device s5p6442_device_pcm1;
extern struct platform_device s5p6442_device_iis0;
extern struct platform_device s5p6442_device_iis1;
extern struct platform_device s5p6442_device_spi;
extern struct platform_device s5p6440_device_pcm;
extern struct platform_device s5p6440_device_iis;

2
arch/arm/plat-samsung/include/plat/regs-serial.h
View File

@ -194,7 +194,7 @@
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38
/* Following are specific to S5PV210 and S5P6442 */
/* Following are specific to S5PV210 */
#define S5PV210_UCON_CLKMASK (1<<10)
#define S5PV210_UCON_PCLK (0<<10)
#define S5PV210_UCON_UCLK (1<<10)

1
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
View File

@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
#endif /* __S3C64XX_PLAT_SPI_H */

12
arch/powerpc/kernel/ptrace.c
View File

@ -933,12 +933,16 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
if (data && !(data & DABR_TRANSLATION))
return -EIO;
#ifdef CONFIG_HAVE_HW_BREAKPOINT
if (ptrace_get_breakpoints(task) < 0)
return -ESRCH;
bp = thread->ptrace_bps[0];
if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
if (bp) {
unregister_hw_breakpoint(bp);
thread->ptrace_bps[0] = NULL;
}
ptrace_put_breakpoints(task);
return 0;
}
if (bp) {
@ -948,9 +952,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
(DABR_DATA_WRITE | DABR_DATA_READ),
&attr.bp_type);
ret = modify_user_hw_breakpoint(bp, &attr);
if (ret)
if (ret) {
ptrace_put_breakpoints(task);
return ret;
}
thread->ptrace_bps[0] = bp;
ptrace_put_breakpoints(task);
thread->dabr = data;
return 0;
}
@ -965,9 +972,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
ptrace_triggered, task);
if (IS_ERR(bp)) {
thread->ptrace_bps[0] = NULL;
ptrace_put_breakpoints(task);
return PTR_ERR(bp);
}
ptrace_put_breakpoints(task);
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
/* Move contents to the DABR register */

4
arch/sh/kernel/ptrace_32.c
View File

@ -117,7 +117,11 @@ void user_enable_single_step(struct task_struct *child)
set_tsk_thread_flag(child, TIF_SINGLESTEP);
if (ptrace_get_breakpoints(child) < 0)
return;
set_single_step(child, pc);
ptrace_put_breakpoints(child);
}
void user_disable_single_step(struct task_struct *child)

87
arch/x86/kernel/cpu/perf_event_intel.c
View File

@ -184,26 +184,23 @@ static __initconst const u64 snb_hw_cache_event_ids
},
},
[ C(LL ) ] = {
/*
* TBD: Need Off-core Response Performance Monitoring support
*/
[ C(OP_READ) ] = {
/* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01bb,
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
[ C(OP_WRITE) ] = {
/* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01bb,
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
[ C(OP_PREFETCH) ] = {
/* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01bb,
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
},
[ C(DTLB) ] = {
@ -285,26 +282,26 @@ static __initconst const u64 westmere_hw_cache_event_ids
},
[ C(LL ) ] = {
[ C(OP_READ) ] = {
/* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01bb,
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
/*
* Use RFO, not WRITEBACK, because a write miss would typically occur
* on RFO.
*/
[ C(OP_WRITE) ] = {
/* OFFCORE_RESPONSE_1.ANY_RFO.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01bb,
/* OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS */
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
[ C(OP_PREFETCH) ] = {
/* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
[ C(RESULT_ACCESS) ] = 0x01b7,
/* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01bb,
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
[ C(RESULT_MISS) ] = 0x01b7,
},
},
[ C(DTLB) ] = {
@ -352,16 +349,36 @@ static __initconst const u64 westmere_hw_cache_event_ids
};
/*
* OFFCORE_RESPONSE MSR bits (subset), See IA32 SDM Vol 3 30.6.1.3
* Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
* See IA32 SDM Vol 3B 30.6.1.3
*/
#define DMND_DATA_RD (1 << 0)
#define DMND_RFO (1 << 1)
#define DMND_WB (1 << 3)
#define PF_DATA_RD (1 << 4)
#define PF_DATA_RFO (1 << 5)
#define RESP_UNCORE_HIT (1 << 8)
#define RESP_MISS (0xf600) /* non uncore hit */
#define NHM_DMND_DATA_RD (1 << 0)
#define NHM_DMND_RFO (1 << 1)
#define NHM_DMND_IFETCH (1 << 2)
#define NHM_DMND_WB (1 << 3)
#define NHM_PF_DATA_RD (1 << 4)
#define NHM_PF_DATA_RFO (1 << 5)
#define NHM_PF_IFETCH (1 << 6)
#define NHM_OFFCORE_OTHER (1 << 7)
#define NHM_UNCORE_HIT (1 << 8)
#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
#define NHM_OTHER_CORE_HITM (1 << 10)
/* reserved */
#define NHM_REMOTE_CACHE_FWD (1 << 12)
#define NHM_REMOTE_DRAM (1 << 13)
#define NHM_LOCAL_DRAM (1 << 14)
#define NHM_NON_DRAM (1 << 15)
#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
#define NHM_DMND_READ (NHM_DMND_DATA_RD)
#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
static __initconst const u64 nehalem_hw_cache_extra_regs
[PERF_COUNT_HW_CACHE_MAX]
@ -370,16 +387,16 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
{
[ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = DMND_DATA_RD|RESP_UNCORE_HIT,
[ C(RESULT_MISS) ] = DMND_DATA_RD|RESP_MISS,
[ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
[ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
},
[ C(OP_WRITE) ] = {
[ C(RESULT_ACCESS) ] = DMND_RFO|DMND_WB|RESP_UNCORE_HIT,
[ C(RESULT_MISS) ] = DMND_RFO|DMND_WB|RESP_MISS,
[ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
[ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
},
[ C(OP_PREFETCH) ] = {
[ C(RESULT_ACCESS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_UNCORE_HIT,
[ C(RESULT_MISS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_MISS,
[ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
[ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
},
}
};

36
arch/x86/kernel/ptrace.c
View File

@ -608,6 +608,9 @@ static int ptrace_write_dr7(struct task_struct *tsk, unsigned long data)
unsigned len, type;
struct perf_event *bp;
if (ptrace_get_breakpoints(tsk) < 0)
return -ESRCH;
data &= ~DR_CONTROL_RESERVED;
old_dr7 = ptrace_get_dr7(thread->ptrace_bps);
restore:
@ -655,6 +658,9 @@ restore:
}
goto restore;
}
ptrace_put_breakpoints(tsk);
return ((orig_ret < 0) ? orig_ret : rc);
}
@ -668,10 +674,17 @@ static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
if (n < HBP_NUM) {
struct perf_event *bp;
if (ptrace_get_breakpoints(tsk) < 0)
return -ESRCH;
bp = thread->ptrace_bps[n];
if (!bp)
return 0;
val = bp->hw.info.address;
val = 0;
else
val = bp->hw.info.address;
ptrace_put_breakpoints(tsk);
} else if (n == 6) {
val = thread->debugreg6;
} else if (n == 7) {
@ -686,6 +699,10 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
struct perf_event *bp;
struct thread_struct *t = &tsk->thread;
struct perf_event_attr attr;
int err = 0;
if (ptrace_get_breakpoints(tsk) < 0)
return -ESRCH;
if (!t->ptrace_bps[nr]) {
ptrace_breakpoint_init(&attr);
@ -709,24 +726,23 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
* writing for the user. And anyway this is the previous
* behaviour.
*/
if (IS_ERR(bp))
return PTR_ERR(bp);
if (IS_ERR(bp)) {
err = PTR_ERR(bp);
goto put;
}
t->ptrace_bps[nr] = bp;
} else {
int err;
bp = t->ptrace_bps[nr];
attr = bp->attr;
attr.bp_addr = addr;
err = modify_user_hw_breakpoint(bp, &attr);
if (err)
return err;
}
return 0;
put:
ptrace_put_breakpoints(tsk);
return err;
}
/*

4
drivers/block/rbd.c
View File

@ -777,9 +777,9 @@ static int rbd_do_request(struct request *rq,
ops,
false,
GFP_NOIO, pages, bio);
if (IS_ERR(req)) {
if (!req) {
up_read(&header->snap_rwsem);
ret = PTR_ERR(req);
ret = -ENOMEM;
goto done_pages;
}

43
drivers/firewire/ohci.c
View File

@ -2199,7 +2199,6 @@ static int ohci_set_config_rom(struct fw_card *card,
{
struct fw_ohci *ohci;
unsigned long flags;
int ret = -EBUSY;
__be32 *next_config_rom;
dma_addr_t uninitialized_var(next_config_rom_bus);
@ -2240,22 +2239,37 @@ static int ohci_set_config_rom(struct fw_card *card,
spin_lock_irqsave(&ohci->lock, flags);
/*
* If there is not an already pending config_rom update,
* push our new allocation into the ohci->next_config_rom
* and then mark the local variable as null so that we
* won't deallocate the new buffer.
*
* OTOH, if there is a pending config_rom update, just
* use that buffer with the new config_rom data, and
* let this routine free the unused DMA allocation.
*/
if (ohci->next_config_rom == NULL) {
ohci->next_config_rom = next_config_rom;
ohci->next_config_rom_bus = next_config_rom_bus;
copy_config_rom(ohci->next_config_rom, config_rom, length);
ohci->next_header = config_rom[0];
ohci->next_config_rom[0] = 0;
reg_write(ohci, OHCI1394_ConfigROMmap,
ohci->next_config_rom_bus);
ret = 0;
next_config_rom = NULL;
}
copy_config_rom(ohci->next_config_rom, config_rom, length);
ohci->next_header = config_rom[0];
ohci->next_config_rom[0] = 0;
reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
spin_unlock_irqrestore(&ohci->lock, flags);
/* If we didn't use the DMA allocation, delete it. */
if (next_config_rom != NULL)
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
next_config_rom, next_config_rom_bus);
/*
* Now initiate a bus reset to have the changes take
* effect. We clean up the old config rom memory and DMA
@ -2263,13 +2277,10 @@ static int ohci_set_config_rom(struct fw_card *card,
* controller could need to access it before the bus reset
* takes effect.
*/
if (ret == 0)
fw_schedule_bus_reset(&ohci->card, true, true);
else
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
next_config_rom, next_config_rom_bus);
return ret;
fw_schedule_bus_reset(&ohci->card, true, true);
return 0;
}
static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)

6
drivers/gpu/drm/drm_mm.c
View File

@ -431,7 +431,7 @@ EXPORT_SYMBOL(drm_mm_search_free_in_range);
void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new)
{
list_replace(&old->node_list, &new->node_list);
list_replace(&old->node_list, &new->hole_stack);
list_replace(&old->hole_stack, &new->hole_stack);
new->hole_follows = old->hole_follows;
new->mm = old->mm;
new->start = old->start;
@ -699,8 +699,8 @@ int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm)
entry->size);
total_used += entry->size;
if (entry->hole_follows) {
hole_start = drm_mm_hole_node_start(&mm->head_node);
hole_end = drm_mm_hole_node_end(&mm->head_node);
hole_start = drm_mm_hole_node_start(entry);
hole_end = drm_mm_hole_node_end(entry);
hole_size = hole_end - hole_start;
seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: free\n",
hole_start, hole_end, hole_size);

10
drivers/gpu/drm/i915/intel_display.c
View File

@ -5154,8 +5154,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(DSPCNTR(plane), dspcntr);
POSTING_READ(DSPCNTR(plane));
if (!HAS_PCH_SPLIT(dev))
intel_enable_plane(dev_priv, plane, pipe);
ret = intel_pipe_set_base(crtc, x, y, old_fb);
@ -5605,9 +5603,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
intel_clock_t clock;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = FP0(pipe);
fp = I915_READ(FP0(pipe));
else
fp = FP1(pipe);
fp = I915_READ(FP1(pipe));
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev)) {
@ -6579,8 +6577,10 @@ intel_user_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-ENOENT);
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
if (!intel_fb)
if (!intel_fb) {
drm_gem_object_unreference_unlocked(&obj->base);
return ERR_PTR(-ENOMEM);
}
ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
if (ret) {

17
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1470,7 +1470,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
if (!HAS_PCH_CPT(dev) &&
I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
struct drm_crtc *crtc = intel_dp->base.base.crtc;
/* Hardware workaround: leaving our transcoder select
* set to transcoder B while it's off will prevent the
* corresponding HDMI output on transcoder A.
@ -1485,7 +1486,19 @@ intel_dp_link_down(struct intel_dp *intel_dp)
/* Changes to enable or select take place the vblank
* after being written.
*/
intel_wait_for_vblank(dev, intel_crtc->pipe);
if (crtc == NULL) {
/* We can arrive here never having been attached
* to a CRTC, for instance, due to inheriting
* random state from the BIOS.
*
* If the pipe is not running, play safe and
* wait for the clocks to stabilise before
* continuing.
*/
POSTING_READ(intel_dp->output_reg);
msleep(50);
} else
intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
}
I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);

3
drivers/gpu/drm/i915/intel_lvds.c
View File

@ -539,6 +539,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
struct drm_device *dev = dev_priv->dev;
struct drm_connector *connector = dev_priv->int_lvds_connector;
if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
return NOTIFY_OK;
/*
* check and update the status of LVDS connector after receiving
* the LID nofication event.

2
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -152,8 +152,6 @@ nouveau_mem_vram_fini(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
nouveau_bo_ref(NULL, &dev_priv->vga_ram);
ttm_bo_device_release(&dev_priv->ttm.bdev);
nouveau_ttm_global_release(dev_priv);

5
drivers/gpu/drm/nouveau/nouveau_state.c
View File

@ -768,6 +768,11 @@ static void nouveau_card_takedown(struct drm_device *dev)
engine->mc.takedown(dev);
engine->display.late_takedown(dev);
if (dev_priv->vga_ram) {
nouveau_bo_unpin(dev_priv->vga_ram);
nouveau_bo_ref(NULL, &dev_priv->vga_ram);
}
mutex_lock(&dev->struct_mutex);
ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);

4
drivers/gpu/drm/radeon/radeon_atombios.c
View File

@ -431,7 +431,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
}
}
/* Acer laptop (Acer TravelMate 5730G) has an HDMI port
/* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
* on the laptop and a DVI port on the docking station and
* both share the same encoder, hpd pin, and ddc line.
* So while the bios table is technically correct,
@ -440,7 +440,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
* with different crtcs which isn't possible on the hardware
* side and leaves no crtcs for LVDS or VGA.
*/
if ((dev->pdev->device == 0x95c4) &&
if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
(dev->pdev->subsystem_vendor == 0x1025) &&
(dev->pdev->subsystem_device == 0x013c)) {
if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&

29
drivers/gpu/drm/radeon/radeon_atpx_handler.c
View File

@ -15,6 +15,9 @@
#define ATPX_VERSION 0
#define ATPX_GPU_PWR 2
#define ATPX_MUX_SELECT 3
#define ATPX_I2C_MUX_SELECT 4
#define ATPX_SWITCH_START 5
#define ATPX_SWITCH_END 6
#define ATPX_INTEGRATED 0
#define ATPX_DISCRETE 1
@ -149,13 +152,35 @@ static int radeon_atpx_switch_mux(acpi_handle handle, int mux_id)
return radeon_atpx_execute(handle, ATPX_MUX_SELECT, mux_id);
}
static int radeon_atpx_switch_i2c_mux(acpi_handle handle, int mux_id)
{
return radeon_atpx_execute(handle, ATPX_I2C_MUX_SELECT, mux_id);
}
static int radeon_atpx_switch_start(acpi_handle handle, int gpu_id)
{
return radeon_atpx_execute(handle, ATPX_SWITCH_START, gpu_id);
}
static int radeon_atpx_switch_end(acpi_handle handle, int gpu_id)
{
return radeon_atpx_execute(handle, ATPX_SWITCH_END, gpu_id);
}
static int radeon_atpx_switchto(enum vga_switcheroo_client_id id)
{
int gpu_id;
if (id == VGA_SWITCHEROO_IGD)
radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 0);
gpu_id = ATPX_INTEGRATED;
else
radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 1);
gpu_id = ATPX_DISCRETE;
radeon_atpx_switch_start(radeon_atpx_priv.atpx_handle, gpu_id);
radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, gpu_id);
radeon_atpx_switch_i2c_mux(radeon_atpx_priv.atpx_handle, gpu_id);
radeon_atpx_switch_end(radeon_atpx_priv.atpx_handle, gpu_id);
return 0;
}

6
drivers/gpu/drm/radeon/radeon_cursor.c
View File

@ -167,9 +167,6 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
return -EINVAL;
}
radeon_crtc->cursor_width = width;
radeon_crtc->cursor_height = height;
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
if (!obj) {
DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
@ -180,6 +177,9 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
if (ret)
goto fail;
radeon_crtc->cursor_width = width;
radeon_crtc->cursor_height = height;
radeon_lock_cursor(crtc, true);
/* XXX only 27 bit offset for legacy cursor */
radeon_set_cursor(crtc, obj, gpu_addr);

2
drivers/media/dvb/dvb-usb/Kconfig
View File

@ -356,6 +356,8 @@ config DVB_USB_LME2510
select DVB_TDA826X if !DVB_FE_CUSTOMISE
select DVB_STV0288 if !DVB_FE_CUSTOMISE
select DVB_IX2505V if !DVB_FE_CUSTOMISE
select DVB_STV0299 if !DVB_FE_CUSTOMISE
select DVB_PLL if !DVB_FE_CUSTOMISE
help
Say Y here to support the LME DM04/QQBOX DVB-S USB2.0 .

1
drivers/media/dvb/ngene/ngene-core.c
View File

@ -1520,6 +1520,7 @@ static int init_channel(struct ngene_channel *chan)
if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
set_transfer(chan, 1);
chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
set_transfer(&chan->dev->channel[2], 1);
dvb_register_device(adapter, &chan->ci_dev,
&ngene_dvbdev_ci, (void *) chan,

2
drivers/media/radio/saa7706h.c
View File

@ -376,7 +376,7 @@ static int __devinit saa7706h_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%02x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct saa7706h_state), GFP_KERNEL);
state = kzalloc(sizeof(struct saa7706h_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
sd = &state->sd;

2
drivers/media/radio/tef6862.c
View File

@ -176,7 +176,7 @@ static int __devinit tef6862_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%02x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct tef6862_state), GFP_KERNEL);
state = kzalloc(sizeof(struct tef6862_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
state->freq = TEF6862_LO_FREQ;

31
drivers/media/rc/imon.c
View File

@ -46,7 +46,7 @@
#define MOD_AUTHOR "Jarod Wilson <jarod@wilsonet.com>"
#define MOD_DESC "Driver for SoundGraph iMON MultiMedia IR/Display"
#define MOD_NAME "imon"
#define MOD_VERSION "0.9.2"
#define MOD_VERSION "0.9.3"
#define DISPLAY_MINOR_BASE 144
#define DEVICE_NAME "lcd%d"
@ -460,8 +460,9 @@ static int display_close(struct inode *inode, struct file *file)
}
/**
* Sends a packet to the device -- this function must be called
* with ictx->lock held.
* Sends a packet to the device -- this function must be called with
* ictx->lock held, or its unlock/lock sequence while waiting for tx
* to complete can/will lead to a deadlock.
*/
static int send_packet(struct imon_context *ictx)
{
@ -991,12 +992,21 @@ static void imon_touch_display_timeout(unsigned long data)
* the iMON remotes, and those used by the Windows MCE remotes (which is
* really just RC-6), but only one or the other at a time, as the signals
* are decoded onboard the receiver.
*
* This function gets called two different ways, one way is from
* rc_register_device, for initial protocol selection/setup, and the other is
* via a userspace-initiated protocol change request, either by direct sysfs
* prodding or by something like ir-keytable. In the rc_register_device case,
* the imon context lock is already held, but when initiated from userspace,
* it is not, so we must acquire it prior to calling send_packet, which
* requires that the lock is held.
*/
static int imon_ir_change_protocol(struct rc_dev *rc, u64 rc_type)
{
int retval;
struct imon_context *ictx = rc->priv;
struct device *dev = ictx->dev;
bool unlock = false;
unsigned char ir_proto_packet[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86 };
@ -1029,6 +1039,11 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 rc_type)
memcpy(ictx->usb_tx_buf, &ir_proto_packet, sizeof(ir_proto_packet));
if (!mutex_is_locked(&ictx->lock)) {
unlock = true;
mutex_lock(&ictx->lock);
}
retval = send_packet(ictx);
if (retval)
goto out;
@ -1037,6 +1052,9 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 rc_type)
ictx->pad_mouse = false;
out:
if (unlock)
mutex_unlock(&ictx->lock);
return retval;
}
@ -2134,6 +2152,7 @@ static struct imon_context *imon_init_intf0(struct usb_interface *intf)
goto rdev_setup_failed;
}
mutex_unlock(&ictx->lock);
return ictx;
rdev_setup_failed:
@ -2205,6 +2224,7 @@ static struct imon_context *imon_init_intf1(struct usb_interface *intf,
goto urb_submit_failed;
}
mutex_unlock(&ictx->lock);
return ictx;
urb_submit_failed:
@ -2299,6 +2319,8 @@ static int __devinit imon_probe(struct usb_interface *interface,
usb_set_intfdata(interface, ictx);
if (ifnum == 0) {
mutex_lock(&ictx->lock);
if (product == 0xffdc && ictx->rf_device) {
sysfs_err = sysfs_create_group(&interface->dev.kobj,
&imon_rf_attr_group);
@ -2309,13 +2331,14 @@ static int __devinit imon_probe(struct usb_interface *interface,
if (ictx->display_supported)
imon_init_display(ictx, interface);
mutex_unlock(&ictx->lock);
}
dev_info(dev, "iMON device (%04x:%04x, intf%d) on "
"usb<%d:%d> initialized\n", vendor, product, ifnum,
usbdev->bus->busnum, usbdev->devnum);
mutex_unlock(&ictx->lock);
mutex_unlock(&driver_lock);
return 0;

1
drivers/media/rc/ite-cir.c
View File

@ -36,6 +36,7 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/input.h>
#include <linux/bitops.h>

2
drivers/media/rc/mceusb.c
View File

@ -220,6 +220,8 @@ static struct usb_device_id mceusb_dev_table[] = {
{ USB_DEVICE(VENDOR_PHILIPS, 0x206c) },
/* Philips/Spinel plus IR transceiver for ASUS */
{ USB_DEVICE(VENDOR_PHILIPS, 0x2088) },
/* Philips IR transceiver (Dell branded) */
{ USB_DEVICE(VENDOR_PHILIPS, 0x2093) },
/* Realtek MCE IR Receiver and card reader */
{ USB_DEVICE(VENDOR_REALTEK, 0x0161),
.driver_info = MULTIFUNCTION },

4
drivers/media/rc/rc-main.c
View File

@ -707,7 +707,8 @@ static void ir_close(struct input_dev *idev)
{
struct rc_dev *rdev = input_get_drvdata(idev);
rdev->close(rdev);
if (rdev)
rdev->close(rdev);
}
/* class for /sys/class/rc */
@ -733,6 +734,7 @@ static struct {
{ RC_TYPE_SONY, "sony" },
{ RC_TYPE_RC5_SZ, "rc-5-sz" },
{ RC_TYPE_LIRC, "lirc" },
{ RC_TYPE_OTHER, "other" },
};
#define PROTO_NONE "none"

2
drivers/media/video/m52790.c
View File

@ -174,7 +174,7 @@ static int m52790_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct m52790_state), GFP_KERNEL);
state = kzalloc(sizeof(struct m52790_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;

2
drivers/media/video/tda9840.c
View File

@ -171,7 +171,7 @@ static int tda9840_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
sd = kmalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
if (sd == NULL)
return -ENOMEM;
v4l2_i2c_subdev_init(sd, client, &tda9840_ops);

2
drivers/media/video/tea6415c.c
View File

@ -152,7 +152,7 @@ static int tea6415c_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
sd = kmalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
if (sd == NULL)
return -ENOMEM;
v4l2_i2c_subdev_init(sd, client, &tea6415c_ops);

2
drivers/media/video/tea6420.c
View File

@ -125,7 +125,7 @@ static int tea6420_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
sd = kmalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
if (sd == NULL)
return -ENOMEM;
v4l2_i2c_subdev_init(sd, client, &tea6420_ops);

2
drivers/media/video/upd64031a.c
View File

@ -230,7 +230,7 @@ static int upd64031a_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct upd64031a_state), GFP_KERNEL);
state = kzalloc(sizeof(struct upd64031a_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
sd = &state->sd;

2
drivers/media/video/upd64083.c
View File

@ -202,7 +202,7 @@ static int upd64083_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct upd64083_state), GFP_KERNEL);
state = kzalloc(sizeof(struct upd64083_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
sd = &state->sd;

9
drivers/mfd/omap-usb-host.c
View File

@ -25,7 +25,6 @@
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <plat/usb.h>
#define USBHS_DRIVER_NAME "usbhs-omap"
@ -700,8 +699,7 @@ static int usbhs_enable(struct device *dev)
dev_dbg(dev, "starting TI HSUSB Controller\n");
if (!pdata) {
dev_dbg(dev, "missing platform_data\n");
ret = -ENODEV;
goto end_enable;
return -ENODEV;
}
spin_lock_irqsave(&omap->lock, flags);
@ -915,7 +913,8 @@ static int usbhs_enable(struct device *dev)
end_count:
omap->count++;
goto end_enable;
spin_unlock_irqrestore(&omap->lock, flags);
return 0;
err_tll:
if (pdata->ehci_data->phy_reset) {
@ -931,8 +930,6 @@ err_tll:
clk_disable(omap->usbhost_fs_fck);
clk_disable(omap->usbhost_hs_fck);
clk_disable(omap->usbhost_ick);
end_enable:
spin_unlock_irqrestore(&omap->lock, flags);
return ret;
}

57
drivers/platform/x86/eeepc-laptop.c
View File

@ -585,8 +585,9 @@ static bool eeepc_wlan_rfkill_blocked(struct eeepc_laptop *eeepc)
return true;
}
static void eeepc_rfkill_hotplug(struct eeepc_laptop *eeepc)
static void eeepc_rfkill_hotplug(struct eeepc_laptop *eeepc, acpi_handle handle)
{
struct pci_dev *port;
struct pci_dev *dev;
struct pci_bus *bus;
bool blocked = eeepc_wlan_rfkill_blocked(eeepc);
@ -599,9 +600,16 @@ static void eeepc_rfkill_hotplug(struct eeepc_laptop *eeepc)
mutex_lock(&eeepc->hotplug_lock);
if (eeepc->hotplug_slot) {
bus = pci_find_bus(0, 1);
port = acpi_get_pci_dev(handle);
if (!port) {
pr_warning("Unable to find port\n");
goto out_unlock;
}
bus = port->subordinate;
if (!bus) {
pr_warning("Unable to find PCI bus 1?\n");
pr_warning("Unable to find PCI bus?\n");
goto out_unlock;
}
@ -609,6 +617,7 @@ static void eeepc_rfkill_hotplug(struct eeepc_laptop *eeepc)
pr_err("Unable to read PCI config space?\n");
goto out_unlock;
}
absent = (l == 0xffffffff);
if (blocked != absent) {
@ -647,6 +656,17 @@ out_unlock:
mutex_unlock(&eeepc->hotplug_lock);
}
static void eeepc_rfkill_hotplug_update(struct eeepc_laptop *eeepc, char *node)
{
acpi_status status = AE_OK;
acpi_handle handle;
status = acpi_get_handle(NULL, node, &handle);
if (ACPI_SUCCESS(status))
eeepc_rfkill_hotplug(eeepc, handle);
}
static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data)
{
struct eeepc_laptop *eeepc = data;
@ -654,7 +674,7 @@ static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data)
if (event != ACPI_NOTIFY_BUS_CHECK)
return;
eeepc_rfkill_hotplug(eeepc);
eeepc_rfkill_hotplug(eeepc, handle);
}
static int eeepc_register_rfkill_notifier(struct eeepc_laptop *eeepc,
@ -672,6 +692,11 @@ static int eeepc_register_rfkill_notifier(struct eeepc_laptop *eeepc,
eeepc);
if (ACPI_FAILURE(status))
pr_warning("Failed to register notify on %s\n", node);
/*
* Refresh pci hotplug in case the rfkill state was
* changed during setup.
*/
eeepc_rfkill_hotplug(eeepc, handle);
} else
return -ENODEV;
@ -693,6 +718,12 @@ static void eeepc_unregister_rfkill_notifier(struct eeepc_laptop *eeepc,
if (ACPI_FAILURE(status))
pr_err("Error removing rfkill notify handler %s\n",
node);
/*
* Refresh pci hotplug in case the rfkill
* state was changed after
* eeepc_unregister_rfkill_notifier()
*/
eeepc_rfkill_hotplug(eeepc, handle);
}
}
@ -816,11 +847,7 @@ static void eeepc_rfkill_exit(struct eeepc_laptop *eeepc)
rfkill_destroy(eeepc->wlan_rfkill);
eeepc->wlan_rfkill = NULL;
}
/*
* Refresh pci hotplug in case the rfkill state was changed after
* eeepc_unregister_rfkill_notifier()
*/
eeepc_rfkill_hotplug(eeepc);
if (eeepc->hotplug_slot)
pci_hp_deregister(eeepc->hotplug_slot);
@ -889,11 +916,6 @@ static int eeepc_rfkill_init(struct eeepc_laptop *eeepc)
eeepc_register_rfkill_notifier(eeepc, "\\_SB.PCI0.P0P5");
eeepc_register_rfkill_notifier(eeepc, "\\_SB.PCI0.P0P6");
eeepc_register_rfkill_notifier(eeepc, "\\_SB.PCI0.P0P7");
/*
* Refresh pci hotplug in case the rfkill state was changed during
* setup.
*/
eeepc_rfkill_hotplug(eeepc);
exit:
if (result && result != -ENODEV)
@ -928,8 +950,11 @@ static int eeepc_hotk_restore(struct device *device)
struct eeepc_laptop *eeepc = dev_get_drvdata(device);
/* Refresh both wlan rfkill state and pci hotplug */
if (eeepc->wlan_rfkill)
eeepc_rfkill_hotplug(eeepc);
if (eeepc->wlan_rfkill) {
eeepc_rfkill_hotplug_update(eeepc, "\\_SB.PCI0.P0P5");
eeepc_rfkill_hotplug_update(eeepc, "\\_SB.PCI0.P0P6");
eeepc_rfkill_hotplug_update(eeepc, "\\_SB.PCI0.P0P7");
}
if (eeepc->bluetooth_rfkill)
rfkill_set_sw_state(eeepc->bluetooth_rfkill,

130
drivers/platform/x86/sony-laptop.c
View File

@ -934,6 +934,14 @@ static ssize_t sony_nc_sysfs_store(struct device *dev,
/*
* Backlight device
*/
struct sony_backlight_props {
struct backlight_device *dev;
int handle;
u8 offset;
u8 maxlvl;
};
struct sony_backlight_props sony_bl_props;
static int sony_backlight_update_status(struct backlight_device *bd)
{
return acpi_callsetfunc(sony_nc_acpi_handle, "SBRT",
@ -954,21 +962,26 @@ static int sony_nc_get_brightness_ng(struct backlight_device *bd)
{
int result;
int *handle = (int *)bl_get_data(bd);
struct sony_backlight_props *sdev =
(struct sony_backlight_props *)bl_get_data(bd);
sony_call_snc_handle(*handle, 0x0200, &result);
sony_call_snc_handle(sdev->handle, 0x0200, &result);
return result & 0xff;
return (result & 0xff) - sdev->offset;
}
static int sony_nc_update_status_ng(struct backlight_device *bd)
{
int value, result;
int *handle = (int *)bl_get_data(bd);
struct sony_backlight_props *sdev =
(struct sony_backlight_props *)bl_get_data(bd);
value = bd->props.brightness;
sony_call_snc_handle(*handle, 0x0100 | (value << 16), &result);
value = bd->props.brightness + sdev->offset;
if (sony_call_snc_handle(sdev->handle, 0x0100 | (value << 16), &result))
return -EIO;
return sony_nc_get_brightness_ng(bd);
return value;
}
static const struct backlight_ops sony_backlight_ops = {
@ -981,8 +994,6 @@ static const struct backlight_ops sony_backlight_ng_ops = {
.update_status = sony_nc_update_status_ng,
.get_brightness = sony_nc_get_brightness_ng,
};
static int backlight_ng_handle;
static struct backlight_device *sony_backlight_device;
/*
* New SNC-only Vaios event mapping to driver known keys
@ -1549,6 +1560,75 @@ static void sony_nc_kbd_backlight_resume(void)
&ignore);
}
static void sony_nc_backlight_ng_read_limits(int handle,
struct sony_backlight_props *props)
{
int offset;
acpi_status status;
u8 brlvl, i;
u8 min = 0xff, max = 0x00;
struct acpi_object_list params;
union acpi_object in_obj;
union acpi_object *lvl_enum;
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
props->handle = handle;
props->offset = 0;
props->maxlvl = 0xff;
offset = sony_find_snc_handle(handle);
if (offset < 0)
return;
/* try to read the boundaries from ACPI tables, if we fail the above
* defaults should be reasonable
*/
params.count = 1;
params.pointer = &in_obj;
in_obj.type = ACPI_TYPE_INTEGER;
in_obj.integer.value = offset;
status = acpi_evaluate_object(sony_nc_acpi_handle, "SN06", &params,
&buffer);
if (ACPI_FAILURE(status))
return;
lvl_enum = (union acpi_object *) buffer.pointer;
if (!lvl_enum) {
pr_err("No SN06 return object.");
return;
}
if (lvl_enum->type != ACPI_TYPE_BUFFER) {
pr_err("Invalid SN06 return object 0x%.2x\n",
lvl_enum->type);
goto out_invalid;
}
/* the buffer lists brightness levels available, brightness levels are
* from 0 to 8 in the array, other values are used by ALS control.
*/
for (i = 0; i < 9 && i < lvl_enum->buffer.length; i++) {
brlvl = *(lvl_enum->buffer.pointer + i);
dprintk("Brightness level: %d\n", brlvl);
if (!brlvl)
break;
if (brlvl > max)
max = brlvl;
if (brlvl < min)
min = brlvl;
}
props->offset = min;
props->maxlvl = max;
dprintk("Brightness levels: min=%d max=%d\n", props->offset,
props->maxlvl);
out_invalid:
kfree(buffer.pointer);
return;
}
static void sony_nc_backlight_setup(void)
{
acpi_handle unused;
@ -1557,14 +1637,14 @@ static void sony_nc_backlight_setup(void)
struct backlight_properties props;
if (sony_find_snc_handle(0x12f) != -1) {
backlight_ng_handle = 0x12f;
ops = &sony_backlight_ng_ops;
max_brightness = 0xff;
sony_nc_backlight_ng_read_limits(0x12f, &sony_bl_props);
max_brightness = sony_bl_props.maxlvl - sony_bl_props.offset;
} else if (sony_find_snc_handle(0x137) != -1) {
backlight_ng_handle = 0x137;
ops = &sony_backlight_ng_ops;
max_brightness = 0xff;
sony_nc_backlight_ng_read_limits(0x137, &sony_bl_props);
max_brightness = sony_bl_props.maxlvl - sony_bl_props.offset;
} else if (ACPI_SUCCESS(acpi_get_handle(sony_nc_acpi_handle, "GBRT",
&unused))) {
@ -1577,22 +1657,22 @@ static void sony_nc_backlight_setup(void)
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_PLATFORM;
props.max_brightness = max_brightness;
sony_backlight_device = backlight_device_register("sony", NULL,
&backlight_ng_handle,
ops, &props);
sony_bl_props.dev = backlight_device_register("sony", NULL,
&sony_bl_props,
ops, &props);
if (IS_ERR(sony_backlight_device)) {
pr_warning(DRV_PFX "unable to register backlight device\n");
sony_backlight_device = NULL;
if (IS_ERR(sony_bl_props.dev)) {
pr_warn(DRV_PFX "unable to register backlight device\n");
sony_bl_props.dev = NULL;
} else
sony_backlight_device->props.brightness =
ops->get_brightness(sony_backlight_device);
sony_bl_props.dev->props.brightness =
ops->get_brightness(sony_bl_props.dev);
}
static void sony_nc_backlight_cleanup(void)
{
if (sony_backlight_device)
backlight_device_unregister(sony_backlight_device);
if (sony_bl_props.dev)
backlight_device_unregister(sony_bl_props.dev);
}
static int sony_nc_add(struct acpi_device *device)
@ -2590,7 +2670,7 @@ static long sonypi_misc_ioctl(struct file *fp, unsigned int cmd,
mutex_lock(&spic_dev.lock);
switch (cmd) {
case SONYPI_IOCGBRT:
if (sony_backlight_device == NULL) {
if (sony_bl_props.dev == NULL) {
ret = -EIO;
break;
}
@ -2603,7 +2683,7 @@ static long sonypi_misc_ioctl(struct file *fp, unsigned int cmd,
ret = -EFAULT;
break;
case SONYPI_IOCSBRT:
if (sony_backlight_device == NULL) {
if (sony_bl_props.dev == NULL) {
ret = -EIO;
break;
}
@ -2617,8 +2697,8 @@ static long sonypi_misc_ioctl(struct file *fp, unsigned int cmd,
break;
}
/* sync the backlight device status */
sony_backlight_device->props.brightness =
sony_backlight_get_brightness(sony_backlight_device);
sony_bl_props.dev->props.brightness =
sony_backlight_get_brightness(sony_bl_props.dev);
break;
case SONYPI_IOCGBAT1CAP:
if (ec_read16(SONYPI_BAT1_FULL, &val16)) {

6
drivers/platform/x86/thinkpad_acpi.c
View File

@ -128,7 +128,8 @@ enum {
};
/* ACPI HIDs */
#define TPACPI_ACPI_HKEY_HID "IBM0068"
#define TPACPI_ACPI_IBM_HKEY_HID "IBM0068"
#define TPACPI_ACPI_LENOVO_HKEY_HID "LEN0068"
#define TPACPI_ACPI_EC_HID "PNP0C09"
/* Input IDs */
@ -3879,7 +3880,8 @@ errexit:
}
static const struct acpi_device_id ibm_htk_device_ids[] = {
{TPACPI_ACPI_HKEY_HID, 0},
{TPACPI_ACPI_IBM_HKEY_HID, 0},
{TPACPI_ACPI_LENOVO_HKEY_HID, 0},
{"", 0},
};

7
drivers/scsi/scsi_lib.c
View File

@ -400,10 +400,15 @@ static inline int scsi_host_is_busy(struct Scsi_Host *shost)
static void scsi_run_queue(struct request_queue *q)
{
struct scsi_device *sdev = q->queuedata;
struct Scsi_Host *shost = sdev->host;
struct Scsi_Host *shost;
LIST_HEAD(starved_list);
unsigned long flags;
/* if the device is dead, sdev will be NULL, so no queue to run */
if (!sdev)
return;
shost = sdev->host;
if (scsi_target(sdev)->single_lun)
scsi_single_lun_run(sdev);

4
drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c
View File

@ -2288,7 +2288,3 @@ err_dev:
free_netdev(dev);
return NULL;
}
EXPORT_SYMBOL(init_ft1000_card);
EXPORT_SYMBOL(stop_ft1000_card);
EXPORT_SYMBOL(flarion_ft1000_cnt);

3
drivers/staging/ft1000/ft1000-pcmcia/ft1000_proc.c
View File

@ -214,6 +214,3 @@ void ft1000CleanupProc(struct net_device *dev)
remove_proc_entry(FT1000_PROC, init_net.proc_net);
unregister_netdevice_notifier(&ft1000_netdev_notifier);
}
EXPORT_SYMBOL(ft1000InitProc);
EXPORT_SYMBOL(ft1000CleanupProc);

2
drivers/staging/gma500/Kconfig
View File

@ -1,6 +1,6 @@
config DRM_PSB
tristate "Intel GMA500 KMS Framebuffer"
depends on DRM && PCI
depends on DRM && PCI && X86
select FB_CFB_COPYAREA
select FB_CFB_FILLRECT
select FB_CFB_IMAGEBLIT

1
drivers/staging/intel_sst/intelmid_v1_control.c
View File

@ -28,6 +28,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/file.h>
#include <asm/mrst.h>
#include <sound/pcm.h>

1
drivers/staging/intel_sst/intelmid_v2_control.c
View File

@ -29,6 +29,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/file.h>
#include "intel_sst.h"
#include "intelmid_snd_control.h"

1
drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
View File

@ -12,6 +12,7 @@
*/
#include <linux/cs5535.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <asm/olpc.h>
#include "olpc_dcon.h"

2
drivers/staging/rts_pstor/debug.h
View File

@ -28,7 +28,7 @@
#define RTSX_STOR "rts_pstor: "
#if CONFIG_RTS_PSTOR_DEBUG
#ifdef CONFIG_RTS_PSTOR_DEBUG
#define RTSX_DEBUGP(x...) printk(KERN_DEBUG RTSX_STOR x)
#define RTSX_DEBUGPN(x...) printk(KERN_DEBUG x)
#define RTSX_DEBUGPX(x...) printk(x)

1
drivers/staging/rts_pstor/ms.c
View File

@ -23,6 +23,7 @@
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"

5
drivers/staging/rts_pstor/rtsx_chip.c
View File

@ -24,6 +24,7 @@
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/workqueue.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"
@ -1311,11 +1312,11 @@ void rtsx_polling_func(struct rtsx_chip *chip)
#ifdef SUPPORT_OCP
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
#if CONFIG_RTS_PSTOR_DEBUG
#ifdef CONFIG_RTS_PSTOR_DEBUG
if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER)) {
RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
}
#endif
#endif
if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
if (chip->card_exist & SD_CARD) {

1
drivers/staging/rts_pstor/rtsx_scsi.c
View File

@ -23,6 +23,7 @@
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"

4
drivers/staging/rts_pstor/sd.c
View File

@ -909,7 +909,7 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
} else {
#if CONFIG_RTS_PSTOR_DEBUG
#ifdef CONFIG_RTS_PSTOR_DEBUG
rtsx_read_register(chip, SD_VP_CTL, &val);
RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
rtsx_read_register(chip, SD_DCMPS_CTL, &val);
@ -958,7 +958,7 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
return STATUS_SUCCESS;
Fail:
#if CONFIG_RTS_PSTOR_DEBUG
#ifdef CONFIG_RTS_PSTOR_DEBUG
rtsx_read_register(chip, SD_VP_CTL, &val);
RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
rtsx_read_register(chip, SD_DCMPS_CTL, &val);

2
drivers/staging/rts_pstor/trace.h
View File

@ -82,7 +82,7 @@ do { \
#define TRACE_GOTO(chip, label) goto label
#endif
#if CONFIG_RTS_PSTOR_DEBUG
#ifdef CONFIG_RTS_PSTOR_DEBUG
static inline void rtsx_dump(u8 *buf, int buf_len)
{
int i;

1
drivers/staging/rts_pstor/xd.c
View File

@ -23,6 +23,7 @@
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"

1
drivers/staging/solo6x10/Kconfig
View File

@ -2,6 +2,7 @@ config SOLO6X10
tristate "Softlogic 6x10 MPEG codec cards"
depends on PCI && VIDEO_DEV && SND && I2C
select VIDEOBUF_DMA_SG
select SND_PCM
---help---
This driver supports the Softlogic based MPEG-4 and h.264 codec
codec cards.

11
drivers/staging/usbip/vhci_hcd.c
View File

@ -876,8 +876,10 @@ static void vhci_shutdown_connection(struct usbip_device *ud)
}
/* kill threads related to this sdev, if v.c. exists */
kthread_stop(vdev->ud.tcp_rx);
kthread_stop(vdev->ud.tcp_tx);
if (vdev->ud.tcp_rx)
kthread_stop(vdev->ud.tcp_rx);
if (vdev->ud.tcp_tx)
kthread_stop(vdev->ud.tcp_tx);
usbip_uinfo("stop threads\n");
@ -949,9 +951,6 @@ static void vhci_device_init(struct vhci_device *vdev)
{
memset(vdev, 0, sizeof(*vdev));
vdev->ud.tcp_rx = kthread_create(vhci_rx_loop, &vdev->ud, "vhci_rx");
vdev->ud.tcp_tx = kthread_create(vhci_tx_loop, &vdev->ud, "vhci_tx");
vdev->ud.side = USBIP_VHCI;
vdev->ud.status = VDEV_ST_NULL;
/* vdev->ud.lock = SPIN_LOCK_UNLOCKED; */
@ -1139,7 +1138,7 @@ static int vhci_hcd_probe(struct platform_device *pdev)
usbip_uerr("create hcd failed\n");
return -ENOMEM;
}
hcd->has_tt = 1;
/* this is private data for vhci_hcd */
the_controller = hcd_to_vhci(hcd);

7
drivers/staging/usbip/vhci_sysfs.c
View File

@ -21,6 +21,7 @@
#include "vhci.h"
#include <linux/in.h>
#include <linux/kthread.h>
/* TODO: refine locking ?*/
@ -220,13 +221,13 @@ static ssize_t store_attach(struct device *dev, struct device_attribute *attr,
vdev->ud.tcp_socket = socket;
vdev->ud.status = VDEV_ST_NOTASSIGNED;
wake_up_process(vdev->ud.tcp_rx);
wake_up_process(vdev->ud.tcp_tx);
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
/* end the lock */
vdev->ud.tcp_rx = kthread_run(vhci_rx_loop, &vdev->ud, "vhci_rx");
vdev->ud.tcp_tx = kthread_run(vhci_tx_loop, &vdev->ud, "vhci_tx");
rh_port_connect(rhport, speed);
return count;

2
drivers/staging/wlan-ng/cfg80211.c
View File

@ -273,7 +273,7 @@ exit:
}
int prism2_set_default_key(struct wiphy *wiphy, struct net_device *dev,
u8 key_index)
u8 key_index, bool unicast, bool multicast)
{
wlandevice_t *wlandev = dev->ml_priv;

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