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gpio: bcm281xx: Centralize register locking
Rather than unlock/re-lock for every write access, unlock a GPIO when it is requested and re-lock it when it is freed. As a result, the GPIO helper functions no longer have to deal with unlocking and re-locking the register. In addition, only unlock a specific GPIO rather than unlocking the entire GPIO bank as before. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Markus Mayer
Linus Walleij
parent
d762bae45a
commit
bdb93c03c5
@ -83,22 +83,43 @@ static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
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return container_of(chip, struct bcm_kona_gpio, gpio_chip);
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}
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static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
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int bank_id, int lockcode)
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static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
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int bank_id, u32 lockcode)
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{
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writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
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writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
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}
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static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
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static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val |= BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
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int bank_id)
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static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val &= ~BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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@ -113,7 +134,6 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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kona_gpio = to_kona_gpio(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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/* determine the GPIO pin direction */
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val = readl(reg_base + GPIO_CONTROL(gpio));
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@ -130,7 +150,6 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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writel(val, reg_base + reg_offset);
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out:
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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@ -146,7 +165,6 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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kona_gpio = to_kona_gpio(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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/* determine the GPIO pin direction */
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val = readl(reg_base + GPIO_CONTROL(gpio));
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@ -157,32 +175,43 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
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val = readl(reg_base + reg_offset);
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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/* return the specified bit status */
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return !!(val & BIT(bit));
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}
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static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
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bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
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return 0;
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}
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static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
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bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
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}
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static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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kona_gpio = to_kona_gpio(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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@ -201,7 +230,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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kona_gpio = to_kona_gpio(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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@ -213,7 +241,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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@ -236,7 +263,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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void __iomem *reg_base;
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u32 val, res;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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kona_gpio = to_kona_gpio(chip);
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reg_base = kona_gpio->reg_base;
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@ -260,7 +286,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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/* spin lock for read-modify-write of the GPIO register */
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_DBR_MASK;
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@ -275,7 +300,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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writel(val, reg_base + GPIO_CONTROL(gpio));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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@ -284,6 +308,8 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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static struct gpio_chip template_chip = {
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.label = "bcm-kona-gpio",
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.owner = THIS_MODULE,
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.request = bcm_kona_gpio_request,
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.free = bcm_kona_gpio_free,
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.direction_input = bcm_kona_gpio_direction_input,
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.get = bcm_kona_gpio_get,
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.direction_output = bcm_kona_gpio_direction_output,
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@ -306,13 +332,11 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_INT_STATUS(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_STATUS(bank_id));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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@ -329,13 +353,11 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_INT_MASK(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MASK(bank_id));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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@ -352,13 +374,11 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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@ -370,7 +390,6 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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u32 lvl_type;
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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@ -397,14 +416,12 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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}
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spin_lock_irqsave(&kona_gpio->lock, flags);
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_ITR_MASK;
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val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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@ -427,7 +444,6 @@ static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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*/
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reg_base = bank->kona_gpio->reg_base;
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bank_id = bank->id;
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bcm_kona_gpio_unlock_bank(reg_base, bank_id);
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while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
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(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
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@ -447,8 +463,6 @@ static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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}
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}
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bcm_kona_gpio_lock_bank(reg_base, bank_id);
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chained_irq_exit(chip, desc);
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}
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@ -534,10 +548,12 @@ static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
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reg_base = kona_gpio->reg_base;
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/* disable interrupts and clear status */
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for (i = 0; i < kona_gpio->num_bank; i++) {
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bcm_kona_gpio_unlock_bank(reg_base, i);
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/* Unlock the entire bank first */
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bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
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writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
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writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
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bcm_kona_gpio_lock_bank(reg_base, i);
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/* Now re-lock the bank */
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bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
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}
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}
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