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ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
EQEP IP block integration data is not present in HWMOD data. Also address ranges specified for EACP & EHRPWM are not correct & HWMOD flags of ADDR_TYPE_RT are added to PWM subsystem register address space. This patch: 1. Corrects register address mapping for ECAP & EHRPWM 2. Removes HWMOD flags in PWM submodule register address space. 3. Adds EQEP HWMOD entries. Signed-off-by: Philip Avinash <avinashphilip@ti.com> [paul@pwsan.com: tweaked patch description] Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Philip Avinash
Paul Walmsley
parent
f6575c90f6
commit
bee76659e2
@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
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};
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/*
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* 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
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* 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
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*/
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static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
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.rev_offs = 0x0,
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@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
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},
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};
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/* eqep0 */
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static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
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{ .irq = 79 + OMAP_INTC_START, },
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{ .irq = -1 },
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};
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static struct omap_hwmod am33xx_eqep0_hwmod = {
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.name = "eqep0",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.mpu_irqs = am33xx_eqep0_irqs,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* eqep1 */
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static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
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{ .irq = 88 + OMAP_INTC_START, },
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{ .irq = -1 },
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};
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static struct omap_hwmod am33xx_eqep1_hwmod = {
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.name = "eqep1",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.mpu_irqs = am33xx_eqep1_irqs,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* eqep2 */
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static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
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{ .irq = 89 + OMAP_INTC_START, },
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{ .irq = -1 },
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};
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static struct omap_hwmod am33xx_eqep2_hwmod = {
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.name = "eqep2",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.mpu_irqs = am33xx_eqep2_irqs,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* ecap0 */
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static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
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{ .irq = 31 + OMAP_INTC_START, },
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@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
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},
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{
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.pa_start = 0x48300200,
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.pa_end = 0x48300200 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48300200 + SZ_128 - 1,
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},
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{ }
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};
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@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
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},
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{
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.pa_start = 0x48302200,
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.pa_end = 0x48302200 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48302200 + SZ_128 - 1,
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},
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{ }
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};
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@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
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},
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{
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.pa_start = 0x48304200,
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.pa_end = 0x48304200 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48304200 + SZ_128 - 1,
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},
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{ }
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};
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@ -2625,6 +2682,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
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.user = OCP_USER_MPU,
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};
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/*
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* Splitting the resources to handle access of PWMSS config space
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* and module specific part independently
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*/
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static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
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{
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.pa_start = 0x48300000,
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.pa_end = 0x48300000 + SZ_16 - 1,
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.flags = ADDR_TYPE_RT
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},
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{
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.pa_start = 0x48300180,
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.pa_end = 0x48300180 + SZ_128 - 1,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_eqep0_hwmod,
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.clk = "l4ls_gclk",
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.addr = am33xx_eqep0_addr_space,
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.user = OCP_USER_MPU,
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};
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/*
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* Splitting the resources to handle access of PWMSS config space
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* and module specific part independently
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*/
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static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
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{
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.pa_start = 0x48302000,
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.pa_end = 0x48302000 + SZ_16 - 1,
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.flags = ADDR_TYPE_RT
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},
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{
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.pa_start = 0x48302180,
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.pa_end = 0x48302180 + SZ_128 - 1,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_eqep1_hwmod,
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.clk = "l4ls_gclk",
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.addr = am33xx_eqep1_addr_space,
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.user = OCP_USER_MPU,
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};
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/*
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* Splitting the resources to handle access of PWMSS config space
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* and module specific part independently
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*/
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static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
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{
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.pa_start = 0x48304000,
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.pa_end = 0x48304000 + SZ_16 - 1,
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.flags = ADDR_TYPE_RT
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},
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{
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.pa_start = 0x48304180,
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.pa_end = 0x48304180 + SZ_128 - 1,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_eqep2_hwmod,
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.clk = "l4ls_gclk",
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.addr = am33xx_eqep2_addr_space,
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.user = OCP_USER_MPU,
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};
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/*
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* Splitting the resources to handle access of PWMSS config space
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* and module specific part independently
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@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
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},
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{
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.pa_start = 0x48300100,
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.pa_end = 0x48300100 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48300100 + SZ_128 - 1,
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},
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{ }
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};
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@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
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},
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{
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.pa_start = 0x48302100,
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.pa_end = 0x48302100 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48302100 + SZ_128 - 1,
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},
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{ }
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};
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@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
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},
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{
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.pa_start = 0x48304100,
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.pa_end = 0x48304100 + SZ_256 - 1,
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.flags = ADDR_TYPE_RT
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.pa_end = 0x48304100 + SZ_128 - 1,
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},
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{ }
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};
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@ -3395,6 +3524,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l4_ls__ehrpwm0,
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&am33xx_l4_ls__ehrpwm1,
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&am33xx_l4_ls__ehrpwm2,
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&am33xx_l4_ls__eqep0,
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&am33xx_l4_ls__eqep1,
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&am33xx_l4_ls__eqep2,
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&am33xx_l4_ls__ecap0,
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&am33xx_l4_ls__ecap1,
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&am33xx_l4_ls__ecap2,
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