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https://github.com/FEX-Emu/linux.git
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ARM: shmobile: sh73a0 dtsi: Add PM domain support
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Note that unlike on R-Mobile A1 (r8a7740), PM domain D4 can be powered down without ill effects on s2ram behavior, just like on SH-Mobile AP4 (sh7372). Hence we can postpone adding a (minimal) device node for the Coresight-ETM hardware block. The System Controller is also used by the R-Mobile Reset driver, which can now restart the system. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
Simon Horman
parent
05813a8112
commit
bee7a18e85
@ -27,12 +27,14 @@
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1196000000>;
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power-domains = <&pd_a2sl>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1196000000>;
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power-domains = <&pd_a2sl>;
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};
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};
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@ -57,6 +59,7 @@
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc1>;
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};
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sbsc1: memory-controller@fe400000 {
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@ -65,6 +68,7 @@
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc0>;
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};
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pmu {
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@ -77,11 +81,12 @@
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compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
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reg = <0xe6138000 0x200>;
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interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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renesas,channels-mask = <0x3f>;
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clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
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clock-names = "fck";
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status = "disabled";
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};
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@ -103,6 +108,7 @@
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0 7 IRQ_TYPE_LEVEL_HIGH
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0 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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@ -124,6 +130,7 @@
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0 15 IRQ_TYPE_LEVEL_HIGH
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0 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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@ -145,6 +152,7 @@
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0 23 IRQ_TYPE_LEVEL_HIGH
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0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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@ -166,6 +174,7 @@
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0 31 IRQ_TYPE_LEVEL_HIGH
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0 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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@ -179,6 +188,7 @@
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0 169 IRQ_TYPE_LEVEL_HIGH
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0 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -192,6 +202,7 @@
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0 53 IRQ_TYPE_LEVEL_HIGH
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0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -205,6 +216,7 @@
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0 173 IRQ_TYPE_LEVEL_HIGH
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0 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -218,6 +230,7 @@
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0 185 IRQ_TYPE_LEVEL_HIGH
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0 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -231,6 +244,7 @@
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0 189 IRQ_TYPE_LEVEL_HIGH
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0 190 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
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power-domains = <&pd_c5>;
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status = "disabled";
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};
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@ -240,6 +254,7 @@
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interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
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0 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
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power-domains = <&pd_a3sp>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -251,6 +266,7 @@
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0 84 IRQ_TYPE_LEVEL_HIGH
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0 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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status = "disabled";
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};
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@ -262,6 +278,7 @@
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
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0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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@ -273,6 +290,7 @@
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
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0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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@ -284,6 +302,7 @@
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interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -293,6 +312,7 @@
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -302,6 +322,7 @@
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -311,6 +332,7 @@
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -320,6 +342,7 @@
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interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -329,6 +352,7 @@
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -338,6 +362,7 @@
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -347,6 +372,7 @@
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interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -356,6 +382,7 @@
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -374,6 +401,117 @@
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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power-domains = <&pd_c5>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
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reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
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pm-domains {
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pd_c5: c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_c4: c4@0 {
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reg = <0>;
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#power-domain-cells = <0>;
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};
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pd_d4: d4@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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};
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pd_a4bc0: a4bc0@4 {
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reg = <4>;
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#power-domain-cells = <0>;
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};
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pd_a4bc1: a4bc1@5 {
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reg = <5>;
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#power-domain-cells = <0>;
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};
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pd_a4lc0: a4lc0@6 {
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reg = <6>;
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#power-domain-cells = <0>;
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};
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pd_a4lc1: a4lc1@7 {
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reg = <7>;
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#power-domain-cells = <0>;
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};
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pd_a4mp: a4mp@8 {
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reg = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3mp: a3mp@9 {
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reg = <9>;
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#power-domain-cells = <0>;
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};
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pd_a3vc: a3vc@10 {
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reg = <10>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4rm: a4rm@12 {
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reg = <12>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3r: a3r@13 {
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reg = <13>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2rv: a2rv@14 {
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reg = <14>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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};
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};
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};
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pd_a4s: a4s@16 {
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reg = <16>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3sp: a3sp@17 {
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reg = <17>;
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#power-domain-cells = <0>;
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};
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pd_a3sg: a3sg@18 {
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reg = <18>;
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#power-domain-cells = <0>;
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};
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pd_a3sm: a3sm@19 {
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reg = <19>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2sl: a2sl@20 {
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reg = <20>;
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#power-domain-cells = <0>;
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};
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};
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};
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};
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};
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};
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sh_fsi2: sound@ec230000 {
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@ -381,6 +519,7 @@
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compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
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reg = <0xec230000 0x400>;
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interrupts = <0 146 0x4>;
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power-domains = <&pd_a4mp>;
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status = "disabled";
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};
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@ -393,6 +532,7 @@
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reg = <0xfec10000 0x400>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zb_clk>;
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power-domains = <&pd_a4s>;
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};
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clocks {
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