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crypto: caam - fix LS1021A support on ARMv7 multiplatform kernel
When built using multi_v7_defconfig, driver does not work on LS1021A:
[...]
caam 1700000.crypto: can't identify CAAM ipg clk: -2
caam: probe of 1700000.crypto failed with error -2
[...]
It turns out we have to detect at runtime whether driver is running
on an i.MX platform or not.
Cc: <stable@vger.kernel.org>
Fixes: 6c3af95593
("crypto: caam - add support for LS1021A")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
3e1166b94e
commit
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@ -1,6 +1,7 @@
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config CRYPTO_DEV_FSL_CAAM
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tristate "Freescale CAAM-Multicore driver backend"
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depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
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select SOC_BUS
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help
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Enables the driver module for Freescale's Cryptographic Accelerator
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and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
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@ -141,10 +142,6 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API
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To compile this as a module, choose M here: the module
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will be called caamrng.
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config CRYPTO_DEV_FSL_CAAM_IMX
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def_bool SOC_IMX6 || SOC_IMX7D
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depends on CRYPTO_DEV_FSL_CAAM
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config CRYPTO_DEV_FSL_CAAM_DEBUG
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bool "Enable debug output in CAAM driver"
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depends on CRYPTO_DEV_FSL_CAAM
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@ -7,6 +7,7 @@
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sys_soc.h>
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#include "compat.h"
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#include "regs.h"
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@ -19,6 +20,8 @@ bool caam_little_end;
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EXPORT_SYMBOL(caam_little_end);
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bool caam_dpaa2;
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EXPORT_SYMBOL(caam_dpaa2);
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bool caam_imx;
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EXPORT_SYMBOL(caam_imx);
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#ifdef CONFIG_CAAM_QI
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#include "qi.h"
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@ -28,19 +31,11 @@ EXPORT_SYMBOL(caam_dpaa2);
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* i.MX targets tend to have clock control subsystems that can
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* enable/disable clocking to our device.
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*/
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#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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static inline struct clk *caam_drv_identify_clk(struct device *dev,
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char *clk_name)
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{
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return devm_clk_get(dev, clk_name);
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return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
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}
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#else
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static inline struct clk *caam_drv_identify_clk(struct device *dev,
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char *clk_name)
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{
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return NULL;
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}
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#endif
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/*
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* Descriptor to instantiate RNG State Handle 0 in normal mode and
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@ -430,6 +425,10 @@ static int caam_probe(struct platform_device *pdev)
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{
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int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
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u64 caam_id;
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static const struct soc_device_attribute imx_soc[] = {
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{.family = "Freescale i.MX"},
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{},
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};
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struct device *dev;
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struct device_node *nprop, *np;
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struct caam_ctrl __iomem *ctrl;
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@ -451,6 +450,8 @@ static int caam_probe(struct platform_device *pdev)
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dev_set_drvdata(dev, ctrlpriv);
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nprop = pdev->dev.of_node;
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caam_imx = (bool)soc_device_match(imx_soc);
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/* Enable clocking */
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clk = caam_drv_identify_clk(&pdev->dev, "ipg");
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if (IS_ERR(clk)) {
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@ -67,6 +67,7 @@
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*/
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extern bool caam_little_end;
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extern bool caam_imx;
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#define caam_to_cpu(len) \
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static inline u##len caam##len ## _to_cpu(u##len val) \
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@ -154,13 +155,10 @@ static inline u64 rd_reg64(void __iomem *reg)
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#else /* CONFIG_64BIT */
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static inline void wr_reg64(void __iomem *reg, u64 data)
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{
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#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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if (caam_little_end) {
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if (!caam_imx && caam_little_end) {
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wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
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wr_reg32((u32 __iomem *)(reg), data);
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} else
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#endif
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{
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} else {
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wr_reg32((u32 __iomem *)(reg), data >> 32);
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wr_reg32((u32 __iomem *)(reg) + 1, data);
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}
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@ -168,41 +166,40 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
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static inline u64 rd_reg64(void __iomem *reg)
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{
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#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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if (caam_little_end)
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if (!caam_imx && caam_little_end)
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return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
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(u64)rd_reg32((u32 __iomem *)(reg)));
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else
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#endif
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return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
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(u64)rd_reg32((u32 __iomem *)(reg) + 1));
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return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
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(u64)rd_reg32((u32 __iomem *)(reg) + 1));
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}
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#endif /* CONFIG_64BIT */
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static inline u64 cpu_to_caam_dma64(dma_addr_t value)
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{
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if (caam_imx)
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return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
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(u64)cpu_to_caam32(upper_32_bits(value)));
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return cpu_to_caam64(value);
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}
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static inline u64 caam_dma64_to_cpu(u64 value)
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{
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if (caam_imx)
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return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
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(u64)caam32_to_cpu(upper_32_bits(value)));
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return caam64_to_cpu(value);
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}
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_SOC_IMX7D
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#define cpu_to_caam_dma(value) \
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(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
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(u64)cpu_to_caam32(upper_32_bits(value)))
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#define caam_dma_to_cpu(value) \
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(((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \
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(u64)caam32_to_cpu(upper_32_bits(value)))
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#else
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#define cpu_to_caam_dma(value) cpu_to_caam64(value)
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#define caam_dma_to_cpu(value) caam64_to_cpu(value)
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#endif /* CONFIG_SOC_IMX7D */
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#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
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#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
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#else
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#define cpu_to_caam_dma(value) cpu_to_caam32(value)
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#define caam_dma_to_cpu(value) caam32_to_cpu(value)
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#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
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#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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#define cpu_to_caam_dma64(value) \
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(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
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(u64)cpu_to_caam32(upper_32_bits(value)))
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#else
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#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
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#endif
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#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
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/*
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* jr_outentry
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