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[IA64] hotplug/ia64: SN Hotplug Driver: moving of header files

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This patch moves header files out of the arch/ia64/sn directories and into
include/asm-ia64/sn.  These files were being included by other subsystems
and should be under include/asm-ia64/sn.

Signed-off-by: Prarit Bhargava <prarit@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Prarit Bhargava 2005-07-06 15:26:51 -07:00 committed by Tony Luck
parent cb4cb2cb9b
commit c13cf3714f
12 changed files with 49 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/ia64/sn/include/xtalk/hubdev.h
View File

@ -8,6 +8,8 @@
#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
#define _ASM_IA64_SN_XTALK_HUBDEV_H
#include "xtalk/xwidgetdev.h"
#define HUB_WIDGET_ID_MAX 0xf
#define DEV_PER_WIDGET (2*2*8)
#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */

14
arch/ia64/sn/kernel/io_init.c
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@ -9,17 +9,17 @@
#include <linux/bootmem.h>
#include <linux/nodemask.h>
#include <asm/sn/types.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include <asm/sn/io.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/pcibr_provider.h"
#include "xtalk/xwidgetdev.h"
#include <asm/sn/geo.h>
#include "xtalk/hubdev.h"
#include <asm/sn/io.h>
#include <asm/sn/simulator.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/tioca_provider.h>
#include "xtalk/hubdev.h"
#include "xtalk/xwidgetdev.h"
nasid_t master_nasid = INVALID_NASID; /* Partition Master */
@ -226,7 +226,7 @@ static void sn_fixup_ionodes(void)
* from our PCI provider include PIO maps to BAR space and interrupt
* objects.
*/
static void sn_pci_fixup_slot(struct pci_dev *dev)
void sn_pci_fixup_slot(struct pci_dev *dev)
{
int idx;
int segment = 0;

5
arch/ia64/sn/kernel/irq.c
View File

@ -10,13 +10,12 @@
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/sn/intr.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include "xtalk/xwidgetdev.h"
#include <asm/sn/intr.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/pcibr_provider.h"
#include <asm/sn/shub_mmr.h>
#include <asm/sn/sn_sal.h>

3
arch/ia64/sn/pci/pci_dma.c
View File

@ -11,9 +11,10 @@
#include <linux/module.h>
#include <asm/dma.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>
#define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))

2
arch/ia64/sn/pci/pcibr/pcibr_ate.c
View File

@ -8,9 +8,9 @@
#include <linux/types.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/pcibr_provider.h"
int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */

15
arch/ia64/sn/pci/pcibr/pcibr_dma.c
View File

@ -8,18 +8,17 @@
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/tiocp.h"
#include "pci/pic.h"
#include "pci/pcibr_provider.h"
#include "pci/tiocp.h"
#include <asm/sn/pic.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/tiocp.h>
#include "tio.h"
#include <asm/sn/addrs.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"
extern int sn_ioif_inited;

13
arch/ia64/sn/pci/pcibr/pcibr_provider.c
View File

@ -6,18 +6,17 @@
* Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
*/
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/sn/sn_sal.h>
#include "xtalk/xwidgetdev.h"
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include "xtalk/hubdev.h"
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/pcibr_provider.h"
#include <asm/sn/addrs.h>
#include <asm/sn/sn_sal.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"
static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
{

8
arch/ia64/sn/pci/pcibr/pcibr_reg.c
View File

@ -6,13 +6,13 @@
* Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
*/
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include "pci/tiocp.h"
#include "pci/pic.h"
#include "pci/pcibr_provider.h"
#include <asm/sn/pic.h>
#include <asm/sn/tiocp.h>
union br_ptr {
struct tiocp tio;

7
arch/ia64/sn/include/pci/pcibr_provider.h → include/asm-ia64/sn/pcibr_provider.h
View File

@ -8,6 +8,9 @@
#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
#include <asm/sn/intr.h>
#include <asm/sn/pcibus_provider_defs.h>
/* Workarounds */
#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
@ -20,7 +23,7 @@
#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
/*
/*
* The different PCI Bridge types supported on the SGI Altix platforms
*/
#define PCIBR_BRIDGETYPE_UNKNOWN -1
@ -100,7 +103,7 @@ struct pcibus_info {
struct ate_resource pbi_int_ate_resource;
uint64_t pbi_int_ate_size;
uint64_t pbi_dir_xbase;
char pbi_hub_xid;

6
include/asm-ia64/sn/pcidev.h
View File

@ -13,6 +13,8 @@
#define SN_PCIDEV_INFO(pci_dev) \
((struct pcidev_info *)(pci_dev)->sysdata)
#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
(struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
/*
* Given a pci_bus, return the sn pcibus_bussoft struct. Note that
* this only works for root busses, not for busses represented by PPB's.
@ -53,6 +55,8 @@ struct pcidev_info {
extern void sn_irq_fixup(struct pci_dev *pci_dev,
struct sn_irq_info *sn_irq_info);
extern void sn_irq_unfixup(struct pci_dev *pci_dev);
extern void sn_pci_fixup_slot(struct pci_dev *dev);
extern void sn_pci_unfixup_slot(struct pci_dev *dev);
extern void sn_irq_lh_init(void);
#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */

14
arch/ia64/sn/include/pci/pic.h → include/asm-ia64/sn/pic.h
View File

@ -15,7 +15,7 @@
* PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
* be designated as 'device 0'. That is a departure from earlier SGI
* PCI bridges. Because of that we use config space 1 to access the
* config space of the first actual PCI device on the bus.
* config space of the first actual PCI device on the bus.
* Here's what the PIC manual says:
*
* The current PCI-X bus specification now defines that the parent
@ -29,14 +29,14 @@
* correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
* PCI-X requires we start a 1, not 0 and currently the PX brick
* does associate our:
*
*
* device 0 with configuration space window 1,
* device 1 with configuration space window 2,
* device 1 with configuration space window 2,
* device 2 with configuration space window 3,
* device 3 with configuration space window 4.
*
* The net effect is that all config space access are off-by-one with
* relation to other per-slot accesses on the PIC.
* The net effect is that all config space access are off-by-one with
* relation to other per-slot accesses on the PIC.
* Here is a table that shows some of that:
*
* Internal Slot#
@ -65,7 +65,7 @@
*****************************************************************************/
/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
* of a 64-bit register. When writing PIC registers, always write the
* of a 64-bit register. When writing PIC registers, always write the
* entire 64 bits.
*/
@ -164,7 +164,7 @@ struct pic {
uint64_t clear_all; /* 0x000{438,,,5F8} */
} p_buf_count[8];
/* 0x000600-0x0009FF -- PCI/X registers */
uint64_t p_pcix_bus_err_addr; /* 0x000600 */
uint64_t p_pcix_bus_err_attr; /* 0x000608 */

2
arch/ia64/sn/include/pci/tiocp.h → include/asm-ia64/sn/tiocp.h
View File

@ -111,7 +111,7 @@ struct tiocp{
uint64_t clear_all; /* 0x000{438,,,5F8} */
} cp_buf_count[8];
/* 0x000600-0x0009FF -- PCI/X registers */
uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
uint64_t cp_pcix_bus_err_attr; /* 0x000608 */