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drm/stm: Add STM32 DSI controller driver
Add the STM32 DSI controller driver that uses the Synopsys DesignWare MIPI DSI host controller bridge. Signed-off-by: Philippe CORNU <philippe.cornu@st.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/1500277223-29553-8-git-send-email-philippe.cornu@st.com
This commit is contained in:
Philippe CORNU
Benjamin Gaignard
parent
4c308b987a
commit
c1c026dbc1
@ -14,3 +14,10 @@ config DRM_STM
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STMicroelectronics STM32 MCUs.
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To compile this driver as a module, choose M here: the module
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will be called stm-drm.
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config DRM_STM_DSI
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tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
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depends on DRM_STM
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select DRM_DW_MIPI_DSI
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help
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Choose this option for MIPI DSI support on STMicroelectronics SoC.
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@ -2,4 +2,6 @@ stm-drm-y := \
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drv.o \
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ltdc.o
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obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o
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obj-$(CONFIG_DRM_STM) += stm-drm.o
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352
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
Normal file
352
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
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@ -0,0 +1,352 @@
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/*
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* Copyright (C) STMicroelectronics SA 2017
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*
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* Authors: Philippe Cornu <philippe.cornu@st.com>
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* Yannick Fertre <yannick.fertre@st.com>
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/bridge/dw_mipi_dsi.h>
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#include <video/mipi_display.h>
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/* DSI wrapper register & bit definitions */
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/* Note: registers are named as in the Reference Manual */
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#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
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#define WCFGR_DSIM BIT(0) /* DSI Mode */
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#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
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#define DSI_WCR 0x0404 /* Wrapper Control Reg */
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#define WCR_DSIEN BIT(3) /* DSI ENable */
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#define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
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#define WISR_PLLLS BIT(8) /* PLL Lock Status */
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#define WISR_RRS BIT(12) /* Regulator Ready Status */
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#define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
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#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
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#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
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#define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
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#define WRPCR_PLLEN BIT(0) /* PLL ENable */
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#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
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#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
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#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
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#define WRPCR_REGEN BIT(24) /* REGulator ENable */
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#define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
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#define IDF_MIN 1
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#define IDF_MAX 7
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#define NDIV_MIN 10
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#define NDIV_MAX 125
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#define ODF_MIN 1
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#define ODF_MAX 8
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/* dsi color format coding according to the datasheet */
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enum dsi_color {
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DSI_RGB565_CONF1,
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DSI_RGB565_CONF2,
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DSI_RGB565_CONF3,
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DSI_RGB666_CONF1,
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DSI_RGB666_CONF2,
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DSI_RGB888,
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};
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#define LANE_MIN_KBPS 31250
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#define LANE_MAX_KBPS 500000
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/* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
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#define SLEEP_US 1000
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#define TIMEOUT_US 200000
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struct dw_mipi_dsi_stm {
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void __iomem *base;
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struct clk *pllref_clk;
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};
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static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
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{
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writel(val, dsi->base + reg);
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}
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static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
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{
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return readl(dsi->base + reg);
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}
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static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
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{
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dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
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}
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static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
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{
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dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
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}
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static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
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u32 mask, u32 val)
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{
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dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
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}
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static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
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{
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switch (fmt) {
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case MIPI_DSI_FMT_RGB888:
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return DSI_RGB888;
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case MIPI_DSI_FMT_RGB666:
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return DSI_RGB666_CONF2;
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case MIPI_DSI_FMT_RGB666_PACKED:
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return DSI_RGB666_CONF1;
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case MIPI_DSI_FMT_RGB565:
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return DSI_RGB565_CONF1;
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default:
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DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
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}
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return DSI_RGB888;
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}
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static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
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{
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/* prevent from division by 0 */
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if (idf * odf)
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return DIV_ROUND_CLOSEST(clkin_khz * ndiv, idf * odf);
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return 0;
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}
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static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
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int *idf, int *ndiv, int *odf)
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{
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int i, o, n, n_min, n_max;
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int fvco_min, fvco_max, delta, best_delta; /* all in khz */
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/* Early checks preventing division by 0 & odd results */
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if ((clkin_khz <= 0) || (clkout_khz <= 0))
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return -EINVAL;
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fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX;
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fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN;
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best_delta = 1000000; /* big started value (1000000khz) */
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for (i = IDF_MIN; i <= IDF_MAX; i++) {
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/* Compute ndiv range according to Fvco */
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n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
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n_max = (fvco_max * i) / (2 * clkin_khz);
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/* No need to continue idf loop if we reach ndiv max */
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if (n_min >= NDIV_MAX)
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break;
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/* Clamp ndiv to valid values */
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if (n_min < NDIV_MIN)
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n_min = NDIV_MIN;
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if (n_max > NDIV_MAX)
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n_max = NDIV_MAX;
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for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
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n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
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/* Check ndiv according to vco range */
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if ((n < n_min) || (n > n_max))
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continue;
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/* Check if new delta is better & saves parameters */
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delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
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clkout_khz;
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if (delta < 0)
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delta = -delta;
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if (delta < best_delta) {
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*idf = i;
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*ndiv = n;
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*odf = o;
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best_delta = delta;
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}
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/* fast return in case of "perfect result" */
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if (!delta)
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return 0;
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}
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}
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return 0;
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}
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static int dw_mipi_dsi_phy_init(void *priv_data)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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u32 val;
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int ret;
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/* Enable the regulator */
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dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
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SLEEP_US, TIMEOUT_US);
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if (ret)
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DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
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/* Enable the DSI PLL & wait for its lock */
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dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
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SLEEP_US, TIMEOUT_US);
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if (ret)
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DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
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/* Enable the DSI wrapper */
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dsi_set(dsi, DSI_WCR, WCR_DSIEN);
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return 0;
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}
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static int
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dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
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unsigned long mode_flags, u32 lanes, u32 format,
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unsigned int *lane_mbps)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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int ret, bpp;
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u32 val;
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pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
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/* Compute requested pll out */
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bpp = mipi_dsi_pixel_format_to_bpp(format);
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pll_out_khz = mode->clock * bpp / lanes;
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/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
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pll_out_khz = (pll_out_khz * 12) / 10;
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if (pll_out_khz > LANE_MAX_KBPS) {
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pll_out_khz = LANE_MAX_KBPS;
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DRM_WARN("Warning max phy mbps is used\n");
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}
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if (pll_out_khz < LANE_MIN_KBPS) {
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pll_out_khz = LANE_MIN_KBPS;
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DRM_WARN("Warning min phy mbps is used\n");
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}
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/* Compute best pll parameters */
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idf = 0;
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ndiv = 0;
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odf = 0;
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ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
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if (ret)
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DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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/* Set the PLL division factors */
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dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
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(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
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/* Compute uix4 & set the bit period in high-speed mode */
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val = 4000000 / pll_out_khz;
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dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
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/* Select video mode by resetting DSIM bit */
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dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
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/* Select the color coding */
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dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
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dsi_color_from_mipi(format) << 1);
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*lane_mbps = pll_out_khz / 1000;
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DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
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pll_in_khz, pll_out_khz, *lane_mbps);
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return 0;
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}
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static struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
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.init = dw_mipi_dsi_phy_init,
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.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
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};
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static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
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.max_data_lanes = 2,
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.phy_ops = &dw_mipi_dsi_stm_phy_ops,
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};
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static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
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{ .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
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static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_mipi_dsi_stm *dsi;
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struct resource *res;
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int ret;
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dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
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if (!dsi)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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DRM_ERROR("Unable to get resource\n");
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return -ENODEV;
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}
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dsi->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(dsi->base)) {
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DRM_ERROR("Unable to get dsi registers\n");
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return PTR_ERR(dsi->base);
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}
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dsi->pllref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(dsi->pllref_clk)) {
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ret = PTR_ERR(dsi->pllref_clk);
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dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(dsi->pllref_clk);
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if (ret) {
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dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
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return ret;
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}
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dw_mipi_dsi_stm_plat_data.base = dsi->base;
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dw_mipi_dsi_stm_plat_data.priv_data = dsi;
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ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
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if (ret) {
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DRM_ERROR("Failed to initialize mipi dsi host\n");
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clk_disable_unprepare(dsi->pllref_clk);
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}
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return ret;
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}
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static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
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{
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struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
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clk_disable_unprepare(dsi->pllref_clk);
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dw_mipi_dsi_remove(pdev);
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return 0;
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}
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static struct platform_driver dw_mipi_dsi_stm_driver = {
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.probe = dw_mipi_dsi_stm_probe,
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.remove = dw_mipi_dsi_stm_remove,
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.driver = {
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.of_match_table = dw_mipi_dsi_stm_dt_ids,
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.name = "dw_mipi_dsi-stm",
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},
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};
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module_platform_driver(dw_mipi_dsi_stm_driver);
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MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
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MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
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MODULE_LICENSE("GPL v2");
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