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perf/x86/uncore: move NHM-EX/WSM-EX specific code to seperate file
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Borislav Petkov <bp@suse.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1406704935-27708-4-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Yan, Zheng
Ingo Molnar
parent
8268fdfc45
commit
c1e46580c3
@ -37,7 +37,7 @@ endif
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore.o perf_event_intel_uncore_snb.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore_snbep.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore_snbep.o perf_event_intel_uncore_nhmex.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o
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endif
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File diff suppressed because it is too large
Load Diff
@ -24,188 +24,6 @@
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#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
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/* NHM-EX event control */
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#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
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#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
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#define NHMEX_PMON_CTL_EN_BIT0 (1 << 0)
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#define NHMEX_PMON_CTL_EDGE_DET (1 << 18)
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#define NHMEX_PMON_CTL_PMI_EN (1 << 20)
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#define NHMEX_PMON_CTL_EN_BIT22 (1 << 22)
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#define NHMEX_PMON_CTL_INVERT (1 << 23)
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#define NHMEX_PMON_CTL_TRESH_MASK 0xff000000
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#define NHMEX_PMON_RAW_EVENT_MASK (NHMEX_PMON_CTL_EV_SEL_MASK | \
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NHMEX_PMON_CTL_UMASK_MASK | \
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NHMEX_PMON_CTL_EDGE_DET | \
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NHMEX_PMON_CTL_INVERT | \
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NHMEX_PMON_CTL_TRESH_MASK)
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/* NHM-EX Ubox */
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#define NHMEX_U_MSR_PMON_GLOBAL_CTL 0xc00
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#define NHMEX_U_MSR_PMON_CTR 0xc11
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#define NHMEX_U_MSR_PMON_EV_SEL 0xc10
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#define NHMEX_U_PMON_GLOBAL_EN (1 << 0)
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#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL 0x0000001e
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#define NHMEX_U_PMON_GLOBAL_EN_ALL (1 << 28)
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#define NHMEX_U_PMON_GLOBAL_RST_ALL (1 << 29)
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#define NHMEX_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
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#define NHMEX_U_PMON_RAW_EVENT_MASK \
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(NHMEX_PMON_CTL_EV_SEL_MASK | \
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NHMEX_PMON_CTL_EDGE_DET)
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/* NHM-EX Cbox */
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#define NHMEX_C0_MSR_PMON_GLOBAL_CTL 0xd00
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#define NHMEX_C0_MSR_PMON_CTR0 0xd11
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#define NHMEX_C0_MSR_PMON_EV_SEL0 0xd10
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#define NHMEX_C_MSR_OFFSET 0x20
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/* NHM-EX Bbox */
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#define NHMEX_B0_MSR_PMON_GLOBAL_CTL 0xc20
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#define NHMEX_B0_MSR_PMON_CTR0 0xc31
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#define NHMEX_B0_MSR_PMON_CTL0 0xc30
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#define NHMEX_B_MSR_OFFSET 0x40
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#define NHMEX_B0_MSR_MATCH 0xe45
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#define NHMEX_B0_MSR_MASK 0xe46
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#define NHMEX_B1_MSR_MATCH 0xe4d
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#define NHMEX_B1_MSR_MASK 0xe4e
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#define NHMEX_B_PMON_CTL_EN (1 << 0)
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#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT 1
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#define NHMEX_B_PMON_CTL_EV_SEL_MASK \
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(0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
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#define NHMEX_B_PMON_CTR_SHIFT 6
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#define NHMEX_B_PMON_CTR_MASK \
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(0x3 << NHMEX_B_PMON_CTR_SHIFT)
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#define NHMEX_B_PMON_RAW_EVENT_MASK \
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(NHMEX_B_PMON_CTL_EV_SEL_MASK | \
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NHMEX_B_PMON_CTR_MASK)
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/* NHM-EX Sbox */
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#define NHMEX_S0_MSR_PMON_GLOBAL_CTL 0xc40
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#define NHMEX_S0_MSR_PMON_CTR0 0xc51
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#define NHMEX_S0_MSR_PMON_CTL0 0xc50
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#define NHMEX_S_MSR_OFFSET 0x80
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#define NHMEX_S0_MSR_MM_CFG 0xe48
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#define NHMEX_S0_MSR_MATCH 0xe49
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#define NHMEX_S0_MSR_MASK 0xe4a
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#define NHMEX_S1_MSR_MM_CFG 0xe58
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#define NHMEX_S1_MSR_MATCH 0xe59
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#define NHMEX_S1_MSR_MASK 0xe5a
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#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
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#define NHMEX_S_EVENT_TO_R_PROG_EV 0
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/* NHM-EX Mbox */
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#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
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#define NHMEX_M0_MSR_PMU_DSP 0xca5
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#define NHMEX_M0_MSR_PMU_ISS 0xca6
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#define NHMEX_M0_MSR_PMU_MAP 0xca7
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#define NHMEX_M0_MSR_PMU_MSC_THR 0xca8
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#define NHMEX_M0_MSR_PMU_PGT 0xca9
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#define NHMEX_M0_MSR_PMU_PLD 0xcaa
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#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC 0xcab
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#define NHMEX_M0_MSR_PMU_CTL0 0xcb0
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#define NHMEX_M0_MSR_PMU_CNT0 0xcb1
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#define NHMEX_M_MSR_OFFSET 0x40
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#define NHMEX_M0_MSR_PMU_MM_CFG 0xe54
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#define NHMEX_M1_MSR_PMU_MM_CFG 0xe5c
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#define NHMEX_M_PMON_MM_CFG_EN (1ULL << 63)
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#define NHMEX_M_PMON_ADDR_MATCH_MASK 0x3ffffffffULL
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#define NHMEX_M_PMON_ADDR_MASK_MASK 0x7ffffffULL
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#define NHMEX_M_PMON_ADDR_MASK_SHIFT 34
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#define NHMEX_M_PMON_CTL_EN (1 << 0)
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#define NHMEX_M_PMON_CTL_PMI_EN (1 << 1)
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#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT 2
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#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK \
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(0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
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#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT 4
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#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK \
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(0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
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#define NHMEX_M_PMON_CTL_WRAP_MODE (1 << 6)
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#define NHMEX_M_PMON_CTL_FLAG_MODE (1 << 7)
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#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT 9
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#define NHMEX_M_PMON_CTL_INC_SEL_MASK \
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(0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
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#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT 19
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#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK \
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(0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
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#define NHMEX_M_PMON_RAW_EVENT_MASK \
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(NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
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NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
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NHMEX_M_PMON_CTL_WRAP_MODE | \
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NHMEX_M_PMON_CTL_FLAG_MODE | \
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NHMEX_M_PMON_CTL_INC_SEL_MASK | \
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NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 11) - 1) | (1 << 23))
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#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7ULL << (11 + 3 * (n)))
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#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 12) - 1) | (1 << 24))
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#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7ULL << (12 + 3 * (n)))
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/*
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* use the 9~13 bits to select event If the 7th bit is not set,
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* otherwise use the 19~21 bits to select event.
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*/
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#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
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#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_INC_SEL_EXTAR_REG(c, r) \
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EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
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MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
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#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
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EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
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MBOX_SET_FLAG_SEL_MASK, \
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(u64)-1, NHMEX_M_##r)
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/* NHM-EX Rbox */
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#define NHMEX_R_MSR_GLOBAL_CTL 0xe00
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#define NHMEX_R_MSR_PMON_CTL0 0xe10
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#define NHMEX_R_MSR_PMON_CNT0 0xe11
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#define NHMEX_R_MSR_OFFSET 0x20
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#define NHMEX_R_MSR_PORTN_QLX_CFG(n) \
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((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
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#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) (0xe04 + (n))
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#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) (0xe24 + (n))
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#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) \
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(((n) < 4 ? 0 : 0x10) + (n) * 4)
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) \
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(0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
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#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) \
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(0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
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#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
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#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
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#define NHMEX_R_PMON_CTL_EN (1 << 0)
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#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT 1
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#define NHMEX_R_PMON_CTL_EV_SEL_MASK \
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(0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
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#define NHMEX_R_PMON_CTL_PMI_EN (1 << 6)
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#define NHMEX_R_PMON_RAW_EVENT_MASK NHMEX_R_PMON_CTL_EV_SEL_MASK
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/* NHM-EX Wbox */
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#define NHMEX_W_MSR_GLOBAL_CTL 0xc80
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#define NHMEX_W_MSR_PMON_CNT0 0xc90
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#define NHMEX_W_MSR_PMON_EVT_SEL0 0xc91
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#define NHMEX_W_MSR_PMON_FIXED_CTR 0x394
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#define NHMEX_W_MSR_PMON_FIXED_CTL 0x395
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#define NHMEX_W_PMON_GLOBAL_FIXED_EN (1ULL << 31)
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struct intel_uncore_ops;
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struct intel_uncore_pmu;
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struct intel_uncore_box;
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@ -514,3 +332,6 @@ int snbep_uncore_pci_init(void);
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void snbep_uncore_cpu_init(void);
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int ivt_uncore_pci_init(void);
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void ivt_uncore_cpu_init(void);
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/* perf_event_intel_uncore_nhmex.c */
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void nhmex_uncore_cpu_init(void);
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1221
arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c
Normal file
1221
arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c
Normal file
File diff suppressed because it is too large
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