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powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live
At present, the analyse_instr/emulate_step code checks for the relevant MSR_FP/VEC/VSX bit being set when a FP/VMX/VSX load or store is decoded, but doesn't recheck the bit before reading or writing the relevant FP/VMX/VSX register in emulate_step(). Since we don't have preemption disabled, it is possible that we get preempted between checking the MSR bit and doing the register access. If that happened, then the registers would have been saved to the thread_struct for the current process. Accesses to the CPU registers would then potentially read stale values, or write values that would never be seen by the user process. Another way that the registers can become non-live is if a page fault occurs when accessing user memory, and the page fault code calls a copy routine that wants to use the VMX or VSX registers. To fix this, the code for all the FP/VMX/VSX loads gets restructured so that it forms an image in a local variable of the desired register contents, then disables preemption, checks the MSR bit and either sets the CPU register or writes the value to the thread struct. Similarly, the code for stores checks the MSR bit, copies either the CPU register or the thread struct to a local variable, then reenables preemption and then copies the register image to memory. If the instruction being emulated is in the kernel, then we must not use the register values in the thread_struct. In this case, if the relevant MSR enable bit is not set, then emulate_step refuses to emulate the instruction. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Paul Mackerras
Michael Ellerman
parent
e0a0986b44
commit
c22435a5f3
@ -119,6 +119,7 @@ union vsx_reg {
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unsigned long d[2];
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float fp[4];
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double dp[2];
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__vector128 v;
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};
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/*
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@ -21,27 +21,19 @@
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#define STKFRM (PPC_MIN_STKFRM + 16)
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.macro inst32 op
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reg = 0
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.rept 32
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20: \op reg,0,r4
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b 3f
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EX_TABLE(20b,99f)
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reg = reg + 1
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.endr
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.endm
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/* Get the contents of frN into fr0; N is in r3. */
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/* Get the contents of frN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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blr /* fr0 is already in fr0 */
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nop
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reg = 1
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.rept 31
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fmr fr0,reg
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blr
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reg = 0
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.rept 32
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stfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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@ -49,18 +41,23 @@ reg = reg + 1
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of fr0 into frN; N is in r3. */
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/* Put the contents of *p into frN; N is in r3 and p is in r4. */
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_GLOBAL(put_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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blr /* fr0 is already in fr0 */
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nop
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reg = 1
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.rept 31
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fmr reg,fr0
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blr
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reg = 0
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.rept 32
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lfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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@ -68,127 +65,24 @@ reg = reg + 1
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mtctr r5
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mtlr r0
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bctr
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/* Load FP reg N from float at *p. N is in r3, p in r4. */
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_GLOBAL(do_lfs)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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ori r7,r6,MSR_FP
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cmpwi cr7,r3,0
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MTMSRD(r7)
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2: MTMSRD(r6)
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isync
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beq cr7,1f
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stfd fr0,STKFRM-16(r1)
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1: li r9,-EFAULT
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2: lfs fr0,0(r4)
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li r9,0
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3: bl put_fpr
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beq cr7,4f
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lfd fr0,STKFRM-16(r1)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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/* Load FP reg N from double at *p. N is in r3, p in r4. */
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_GLOBAL(do_lfd)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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ori r7,r6,MSR_FP
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cmpwi cr7,r3,0
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MTMSRD(r7)
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isync
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beq cr7,1f
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stfd fr0,STKFRM-16(r1)
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1: li r9,-EFAULT
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2: lfd fr0,0(r4)
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li r9,0
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3: beq cr7,4f
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bl put_fpr
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lfd fr0,STKFRM-16(r1)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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/* Store FP reg N to float at *p. N is in r3, p in r4. */
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_GLOBAL(do_stfs)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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ori r7,r6,MSR_FP
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cmpwi cr7,r3,0
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MTMSRD(r7)
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isync
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beq cr7,1f
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stfd fr0,STKFRM-16(r1)
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bl get_fpr
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1: li r9,-EFAULT
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2: stfs fr0,0(r4)
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li r9,0
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3: beq cr7,4f
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lfd fr0,STKFRM-16(r1)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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/* Store FP reg N to double at *p. N is in r3, p in r4. */
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_GLOBAL(do_stfd)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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ori r7,r6,MSR_FP
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cmpwi cr7,r3,0
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MTMSRD(r7)
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isync
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beq cr7,1f
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stfd fr0,STKFRM-16(r1)
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bl get_fpr
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1: li r9,-EFAULT
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2: stfd fr0,0(r4)
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li r9,0
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3: beq cr7,4f
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lfd fr0,STKFRM-16(r1)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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#ifdef CONFIG_ALTIVEC
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/* Get the contents of vrN into v0; N is in r3. Doesn't touch r3 or r4. */
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/* Get the contents of vrN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r6,r3,3,0xf8
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bcl 20,31,1f
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blr /* v0 is already in v0 */
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nop
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reg = 1
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.rept 31
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vor v0,reg,reg /* assembler doesn't know vmr? */
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blr
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reg = 0
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.rept 32
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stvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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@ -196,18 +90,23 @@ reg = reg + 1
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of v0 into vrN; N is in r3. Doesn't touch r3 or r4. */
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/* Put the contents of *p into vrN; N is in r3 and p is in r4. */
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_GLOBAL(put_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r6,r3,3,0xf8
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bcl 20,31,1f
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blr /* v0 is already in v0 */
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nop
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reg = 1
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.rept 31
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vor reg,v0,v0
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blr
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reg = 0
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.rept 32
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lvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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@ -215,62 +114,9 @@ reg = reg + 1
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mtctr r5
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mtlr r0
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bctr
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/* Load vector reg N from *p. N is in r3, p in r4. */
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_GLOBAL(do_lvx)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VEC@h
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cmpwi cr7,r3,0
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li r8,STKFRM-16
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MTMSRD(r7)
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2: MTMSRD(r6)
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isync
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beq cr7,1f
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stvx v0,r1,r8
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1: li r9,-EFAULT
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2: lvx v0,0,r4
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li r9,0
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3: beq cr7,4f
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bl put_vr
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lvx v0,r1,r8
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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/* Store vector reg N to *p. N is in r3, p in r4. */
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_GLOBAL(do_stvx)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VEC@h
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cmpwi cr7,r3,0
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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beq cr7,1f
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stvx v0,r1,r8
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bl get_vr
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1: li r9,-EFAULT
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2: stvx v0,0,r4
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li r9,0
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3: beq cr7,4f
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lvx v0,r1,r8
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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@ -363,7 +209,6 @@ _GLOBAL(store_vsrn)
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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EX_TABLE(2b,3b)
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#endif /* CONFIG_VSX */
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/* Convert single-precision to double, without disturbing FPRs. */
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@ -36,12 +36,10 @@ extern char system_call_common[];
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/*
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* Functions in ldstfp.S
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*/
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extern int do_lfs(int rn, unsigned long ea);
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extern int do_lfd(int rn, unsigned long ea);
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extern int do_stfs(int rn, unsigned long ea);
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extern int do_stfd(int rn, unsigned long ea);
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extern int do_lvx(int rn, unsigned long ea);
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extern int do_stvx(int rn, unsigned long ea);
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extern void get_fpr(int rn, double *p);
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extern void put_fpr(int rn, const double *p);
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extern void get_vr(int rn, __vector128 *p);
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extern void put_vr(int rn, __vector128 *p);
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extern void load_vsrn(int vsr, const void *p);
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extern void store_vsrn(int vsr, void *p);
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extern void conv_sp_to_dp(const float *sp, double *dp);
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@ -409,63 +407,108 @@ NOKPROBE_SYMBOL(write_mem);
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#ifdef CONFIG_PPC_FPU
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/*
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* Check the address and alignment, and call func to do the actual
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* load or store.
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* These access either the real FP register or the image in the
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* thread_struct, depending on regs->msr & MSR_FP.
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*/
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static int do_fp_load(int rn, int (*func)(int, unsigned long),
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unsigned long ea, int nb,
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struct pt_regs *regs)
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static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)
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{
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int err;
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u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double))));
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union {
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float f;
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double d;
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unsigned long l;
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u8 b[sizeof(double)];
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} u;
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if (!address_ok(regs, ea, nb))
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return -EFAULT;
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if (ea & 3) {
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err = copy_mem_in(buf, ea, nb);
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if (err)
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return err;
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ea = (unsigned long) buf;
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}
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return (*func)(rn, ea);
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err = copy_mem_in(u.b, ea, nb);
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if (err)
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return err;
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preempt_disable();
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if (nb == 4)
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conv_sp_to_dp(&u.f, &u.d);
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if (regs->msr & MSR_FP)
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put_fpr(rn, &u.d);
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else
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current->thread.TS_FPR(rn) = u.l;
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preempt_enable();
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return 0;
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}
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NOKPROBE_SYMBOL(do_fp_load);
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static int do_fp_store(int rn, int (*func)(int, unsigned long),
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unsigned long ea, int nb,
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struct pt_regs *regs)
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static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)
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{
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int err;
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u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double))));
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union {
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float f;
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double d;
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unsigned long l;
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u8 b[sizeof(double)];
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} u;
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if (!address_ok(regs, ea, nb))
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return -EFAULT;
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if ((ea & 3) == 0)
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return (*func)(rn, ea);
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err = (*func)(rn, (unsigned long) buf);
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if (!err)
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err = copy_mem_out(buf, ea, nb);
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return err;
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preempt_disable();
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if (regs->msr & MSR_FP)
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get_fpr(rn, &u.d);
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else
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u.l = current->thread.TS_FPR(rn);
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if (nb == 4)
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conv_dp_to_sp(&u.d, &u.f);
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preempt_enable();
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return copy_mem_out(u.b, ea, nb);
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}
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NOKPROBE_SYMBOL(do_fp_store);
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#endif
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#ifdef CONFIG_ALTIVEC
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/* For Altivec/VMX, no need to worry about alignment */
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static nokprobe_inline int do_vec_load(int rn, int (*func)(int, unsigned long),
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unsigned long ea, struct pt_regs *regs)
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static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
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int size, struct pt_regs *regs)
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{
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int err;
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union {
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__vector128 v;
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u8 b[sizeof(__vector128)];
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} u = {};
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if (!address_ok(regs, ea & ~0xfUL, 16))
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return -EFAULT;
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return (*func)(rn, ea);
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/* align to multiple of size */
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ea &= ~(size - 1);
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err = copy_mem_in(u.b, ea, size);
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if (err)
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return err;
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preempt_disable();
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if (regs->msr & MSR_VEC)
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put_vr(rn, &u.v);
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else
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current->thread.vr_state.vr[rn] = u.v;
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preempt_enable();
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return 0;
|
||||
}
|
||||
|
||||
static nokprobe_inline int do_vec_store(int rn, int (*func)(int, unsigned long),
|
||||
unsigned long ea, struct pt_regs *regs)
|
||||
static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
|
||||
int size, struct pt_regs *regs)
|
||||
{
|
||||
union {
|
||||
__vector128 v;
|
||||
u8 b[sizeof(__vector128)];
|
||||
} u;
|
||||
|
||||
if (!address_ok(regs, ea & ~0xfUL, 16))
|
||||
return -EFAULT;
|
||||
return (*func)(rn, ea);
|
||||
/* align to multiple of size */
|
||||
ea &= ~(size - 1);
|
||||
|
||||
preempt_disable();
|
||||
if (regs->msr & MSR_VEC)
|
||||
get_vr(rn, &u.v);
|
||||
else
|
||||
u.v = current->thread.vr_state.vr[rn];
|
||||
preempt_enable();
|
||||
return copy_mem_out(u.b, ea, size);
|
||||
}
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
|
||||
@ -658,6 +701,68 @@ void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(emulate_vsx_store);
|
||||
NOKPROBE_SYMBOL(emulate_vsx_store);
|
||||
|
||||
static nokprobe_inline int do_vsx_load(struct instruction_op *op,
|
||||
unsigned long ea, struct pt_regs *regs)
|
||||
{
|
||||
int reg = op->reg;
|
||||
u8 mem[16];
|
||||
union vsx_reg buf;
|
||||
int size = GETSIZE(op->type);
|
||||
|
||||
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size))
|
||||
return -EFAULT;
|
||||
|
||||
emulate_vsx_load(op, &buf, mem);
|
||||
preempt_disable();
|
||||
if (reg < 32) {
|
||||
/* FP regs + extensions */
|
||||
if (regs->msr & MSR_FP) {
|
||||
load_vsrn(reg, &buf);
|
||||
} else {
|
||||
current->thread.fp_state.fpr[reg][0] = buf.d[0];
|
||||
current->thread.fp_state.fpr[reg][1] = buf.d[1];
|
||||
}
|
||||
} else {
|
||||
if (regs->msr & MSR_VEC)
|
||||
load_vsrn(reg, &buf);
|
||||
else
|
||||
current->thread.vr_state.vr[reg - 32] = buf.v;
|
||||
}
|
||||
preempt_enable();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static nokprobe_inline int do_vsx_store(struct instruction_op *op,
|
||||
unsigned long ea, struct pt_regs *regs)
|
||||
{
|
||||
int reg = op->reg;
|
||||
u8 mem[16];
|
||||
union vsx_reg buf;
|
||||
int size = GETSIZE(op->type);
|
||||
|
||||
if (!address_ok(regs, ea, size))
|
||||
return -EFAULT;
|
||||
|
||||
preempt_disable();
|
||||
if (reg < 32) {
|
||||
/* FP regs + extensions */
|
||||
if (regs->msr & MSR_FP) {
|
||||
store_vsrn(reg, &buf);
|
||||
} else {
|
||||
buf.d[0] = current->thread.fp_state.fpr[reg][0];
|
||||
buf.d[1] = current->thread.fp_state.fpr[reg][1];
|
||||
}
|
||||
} else {
|
||||
if (regs->msr & MSR_VEC)
|
||||
store_vsrn(reg, &buf);
|
||||
else
|
||||
buf.v = current->thread.vr_state.vr[reg - 32];
|
||||
}
|
||||
preempt_enable();
|
||||
emulate_vsx_store(op, &buf, mem);
|
||||
return copy_mem_out(mem, ea, size);
|
||||
}
|
||||
#endif /* CONFIG_VSX */
|
||||
|
||||
#define __put_user_asmx(x, addr, err, op, cr) \
|
||||
@ -2524,25 +2629,26 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
|
||||
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
case LOAD_FP:
|
||||
if (!(regs->msr & MSR_FP))
|
||||
/*
|
||||
* If the instruction is in userspace, we can emulate it even
|
||||
* if the VMX state is not live, because we have the state
|
||||
* stored in the thread_struct. If the instruction is in
|
||||
* the kernel, we must not touch the state in the thread_struct.
|
||||
*/
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
|
||||
return 0;
|
||||
if (size == 4)
|
||||
err = do_fp_load(op.reg, do_lfs, ea, size, regs);
|
||||
else
|
||||
err = do_fp_load(op.reg, do_lfd, ea, size, regs);
|
||||
err = do_fp_load(op.reg, ea, size, regs);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
case LOAD_VMX:
|
||||
if (!(regs->msr & MSR_VEC))
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
|
||||
return 0;
|
||||
err = do_vec_load(op.reg, do_lvx, ea, regs);
|
||||
err = do_vec_load(op.reg, ea, size, regs);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_VSX
|
||||
case LOAD_VSX: {
|
||||
u8 mem[16];
|
||||
union vsx_reg buf;
|
||||
unsigned long msrbit = MSR_VSX;
|
||||
|
||||
/*
|
||||
@ -2551,14 +2657,9 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
|
||||
*/
|
||||
if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
|
||||
msrbit = MSR_VEC;
|
||||
if (!(regs->msr & msrbit))
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
|
||||
return 0;
|
||||
if (!address_ok(regs, ea, size) ||
|
||||
copy_mem_in(mem, ea, size))
|
||||
return 0;
|
||||
|
||||
emulate_vsx_load(&op, &buf, mem);
|
||||
load_vsrn(op.reg, &buf);
|
||||
err = do_vsx_load(&op, ea, regs);
|
||||
goto ldst_done;
|
||||
}
|
||||
#endif
|
||||
@ -2599,25 +2700,20 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
|
||||
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
case STORE_FP:
|
||||
if (!(regs->msr & MSR_FP))
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
|
||||
return 0;
|
||||
if (size == 4)
|
||||
err = do_fp_store(op.reg, do_stfs, ea, size, regs);
|
||||
else
|
||||
err = do_fp_store(op.reg, do_stfd, ea, size, regs);
|
||||
err = do_fp_store(op.reg, ea, size, regs);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
case STORE_VMX:
|
||||
if (!(regs->msr & MSR_VEC))
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
|
||||
return 0;
|
||||
err = do_vec_store(op.reg, do_stvx, ea, regs);
|
||||
err = do_vec_store(op.reg, ea, size, regs);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_VSX
|
||||
case STORE_VSX: {
|
||||
u8 mem[16];
|
||||
union vsx_reg buf;
|
||||
unsigned long msrbit = MSR_VSX;
|
||||
|
||||
/*
|
||||
@ -2626,15 +2722,9 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
|
||||
*/
|
||||
if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
|
||||
msrbit = MSR_VEC;
|
||||
if (!(regs->msr & msrbit))
|
||||
return 0;
|
||||
if (!address_ok(regs, ea, size))
|
||||
return 0;
|
||||
|
||||
store_vsrn(op.reg, &buf);
|
||||
emulate_vsx_store(&op, &buf, mem);
|
||||
if (copy_mem_out(mem, ea, size))
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
|
||||
return 0;
|
||||
err = do_vsx_store(&op, ea, regs);
|
||||
goto ldst_done;
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user