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irqchip/mvebu-odmi: Add new driver for platform MSI on Marvell 7K/8K
This commits adds a new irqchip driver that handles the ODMI controller found on Marvell 7K/8K processors. The ODMI controller provide MSI interrupt functionality to on-board peripherals, much like the GIC-v2m. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -0,0 +1,41 @@
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* Marvell ODMI for MSI support
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Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
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which can be used by on-board peripheral for MSI interrupts.
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Required properties:
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- compatible : The value here should contain "marvell,odmi-controller".
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- interrupt,controller : Identifies the node as an interrupt controller.
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- msi-controller : Identifies the node as an MSI controller.
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- marvell,odmi-frames : Number of ODMI frames available. Each frame
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provides a number of events.
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- reg : List of register definitions, one for each
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ODMI frame.
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- marvell,spi-base : List of GIC base SPI interrupts, one for each
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ODMI frame. Those SPI interrupts are 0-based,
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i.e marvell,spi-base = <128> will use SPI #96.
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See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
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for details about the GIC Device Tree binding.
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- interrupt-parent : Reference to the parent interrupt controller.
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Example:
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odmi: odmi@300000 {
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compatible = "marvell,odmi-controller";
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interrupt-controller;
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msi-controller;
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marvell,odmi-frames = <4>;
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reg = <0x300000 0x4000>,
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<0x304000 0x4000>,
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<0x308000 0x4000>,
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<0x30C000 0x4000>;
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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@ -223,3 +223,7 @@ config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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@ -59,3 +59,4 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
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obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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248
drivers/irqchip/irq-mvebu-odmi.c
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248
drivers/irqchip/irq-mvebu-odmi.c
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@ -0,0 +1,248 @@
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/*
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* Copyright (C) 2016 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "GIC-ODMI: " fmt
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define GICP_ODMIN_SET 0x40
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#define GICP_ODMI_INT_NUM_SHIFT 12
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#define GICP_ODMIN_GM_EP_R0 0x110
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#define GICP_ODMIN_GM_EP_R1 0x114
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#define GICP_ODMIN_GM_EA_R0 0x108
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#define GICP_ODMIN_GM_EA_R1 0x118
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/*
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* We don't support the group events, so we simply have 8 interrupts
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* per frame.
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*/
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#define NODMIS_SHIFT 3
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#define NODMIS_PER_FRAME (1 << NODMIS_SHIFT)
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#define NODMIS_MASK (NODMIS_PER_FRAME - 1)
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struct odmi_data {
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struct resource res;
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void __iomem *base;
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unsigned int spi_base;
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};
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static struct odmi_data *odmis;
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static unsigned long *odmis_bm;
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static unsigned int odmis_count;
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/* Protects odmis_bm */
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static DEFINE_SPINLOCK(odmis_bm_lock);
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static int odmi_set_affinity(struct irq_data *d,
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const struct cpumask *mask, bool force)
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{
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int ret;
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ret = irq_chip_set_affinity_parent(d, mask, force);
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if (ret == IRQ_SET_MASK_OK)
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ret = IRQ_SET_MASK_OK_DONE;
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return ret;
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}
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static void odmi_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct odmi_data *odmi;
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phys_addr_t addr;
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unsigned int odmin;
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if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME))
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return;
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odmi = &odmis[d->hwirq >> NODMIS_SHIFT];
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odmin = d->hwirq & NODMIS_MASK;
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addr = odmi->res.start + GICP_ODMIN_SET;
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msg->address_hi = upper_32_bits(addr);
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msg->address_lo = lower_32_bits(addr);
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msg->data = odmin << GICP_ODMI_INT_NUM_SHIFT;
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}
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static struct irq_chip odmi_irq_chip = {
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.name = "ODMI",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = odmi_set_affinity,
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.irq_compose_msi_msg = odmi_compose_msi_msg,
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};
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static int odmi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct odmi_data *odmi = NULL;
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struct irq_fwspec fwspec;
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struct irq_data *d;
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unsigned int hwirq, odmin;
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int ret;
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spin_lock(&odmis_bm_lock);
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hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count);
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if (hwirq >= NODMIS_PER_FRAME * odmis_count) {
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spin_unlock(&odmis_bm_lock);
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return -ENOSPC;
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}
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__set_bit(hwirq, odmis_bm);
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spin_unlock(&odmis_bm_lock);
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odmi = &odmis[hwirq >> NODMIS_SHIFT];
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odmin = hwirq & NODMIS_MASK;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = GIC_SPI;
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fwspec.param[1] = odmi->spi_base - 32 + odmin;
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (ret) {
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pr_err("Cannot allocate parent IRQ\n");
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spin_lock(&odmis_bm_lock);
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__clear_bit(odmin, odmis_bm);
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spin_unlock(&odmis_bm_lock);
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return ret;
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}
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/* Configure the interrupt line to be edge */
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d = irq_domain_get_irq_data(domain->parent, virq);
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d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&odmi_irq_chip, NULL);
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return 0;
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}
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static void odmi_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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if (d->hwirq >= odmis_count * NODMIS_PER_FRAME) {
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pr_err("Failed to teardown msi. Invalid hwirq %lu\n", d->hwirq);
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return;
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}
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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/* Actually free the MSI */
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spin_lock(&odmis_bm_lock);
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__clear_bit(d->hwirq, odmis_bm);
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spin_unlock(&odmis_bm_lock);
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}
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static const struct irq_domain_ops odmi_domain_ops = {
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.alloc = odmi_irq_domain_alloc,
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.free = odmi_irq_domain_free,
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};
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static struct irq_chip odmi_msi_irq_chip = {
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.name = "ODMI",
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};
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static struct msi_domain_ops odmi_msi_ops = {
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};
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static struct msi_domain_info odmi_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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.ops = &odmi_msi_ops,
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.chip = &odmi_msi_irq_chip,
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};
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static int __init mvebu_odmi_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *inner_domain, *plat_domain;
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int ret, i;
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if (of_property_read_u32(node, "marvell,odmi-frames", &odmis_count))
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return -EINVAL;
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odmis = kcalloc(odmis_count, sizeof(struct odmi_data), GFP_KERNEL);
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if (!odmis)
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return -ENOMEM;
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odmis_bm = kcalloc(BITS_TO_LONGS(odmis_count * NODMIS_PER_FRAME),
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sizeof(long), GFP_KERNEL);
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if (!odmis_bm) {
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ret = -ENOMEM;
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goto err_alloc;
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}
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for (i = 0; i < odmis_count; i++) {
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struct odmi_data *odmi = &odmis[i];
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ret = of_address_to_resource(node, i, &odmi->res);
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if (ret)
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goto err_unmap;
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odmi->base = of_io_request_and_map(node, i, "odmi");
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if (IS_ERR(odmi->base)) {
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ret = PTR_ERR(odmi->base);
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goto err_unmap;
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}
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if (of_property_read_u32_index(node, "marvell,spi-base",
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i, &odmi->spi_base)) {
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ret = -EINVAL;
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goto err_unmap;
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}
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}
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inner_domain = irq_domain_create_linear(of_node_to_fwnode(node),
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odmis_count * NODMIS_PER_FRAME,
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&odmi_domain_ops, NULL);
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if (!inner_domain) {
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ret = -ENOMEM;
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goto err_unmap;
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}
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inner_domain->parent = irq_find_host(parent);
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plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
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&odmi_msi_domain_info,
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inner_domain);
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if (!plat_domain) {
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ret = -ENOMEM;
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goto err_remove_inner;
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}
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return 0;
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err_remove_inner:
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irq_domain_remove(inner_domain);
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err_unmap:
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for (i = 0; i < odmis_count; i++) {
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struct odmi_data *odmi = &odmis[i];
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if (odmi->base && !IS_ERR(odmi->base))
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iounmap(odmis[i].base);
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}
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kfree(odmis_bm);
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err_alloc:
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kfree(odmis);
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return ret;
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}
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IRQCHIP_DECLARE(mvebu_odmi, "marvell,odmi-controller", mvebu_odmi_init);
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