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drivers: clk: st: Fix FSYN channel values
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -489,7 +489,7 @@ static int quadfs_pll_is_enabled(struct clk_hw *hw)
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struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
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struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
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u32 npda = CLKGEN_READ(pll, npda);
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u32 npda = CLKGEN_READ(pll, npda);
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return !!npda;
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return pll->data->powerup_polarity ? !npda : !!npda;
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}
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}
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static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
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static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
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@ -774,7 +774,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
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if (fs->lock)
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if (fs->lock)
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spin_lock_irqsave(fs->lock, flags);
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spin_lock_irqsave(fs->lock, flags);
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CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
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CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
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if (fs->lock)
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if (fs->lock)
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spin_unlock_irqrestore(fs->lock, flags);
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spin_unlock_irqrestore(fs->lock, flags);
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