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[PATCH] Change address of ppc64 initial segment table

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On ppc64 machines with segment tables, CPU0's segment table is at a
fixed address, currently 0x9000.  This patch moves it to the free
space at 0x6000, just below the fwnmi data area.  This saves 8k of
space in vmlinux and the runtime kernel image.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson 2005-08-19 14:52:31 +10:00 committed by Paul Mackerras
parent ec465515ee
commit c59c464a3e
3 changed files with 24 additions and 19 deletions
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32
arch/ppc64/kernel/head.S
View File

@ -52,9 +52,10 @@
* We layout physical memory as follows:
* 0x0000 - 0x00ff : Secondary processor spin code
* 0x0100 - 0x2fff : pSeries Interrupt prologs
* 0x3000 - 0x6fff : interrupt support, iSeries and common interrupt prologs
* 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
* 0x6000 - 0x6fff : Initial (CPU0) segment table
* 0x7000 - 0x7fff : FWNMI data area
* 0x9000 - 0x9fff : Initial segment table
* 0x8000 - : Early init and support code
*/
/*
@ -1256,6 +1257,20 @@ unrecov_slb:
bl .unrecoverable_exception
b 1b
/*
* Space for CPU0's segment table.
*
* On iSeries, the hypervisor must fill in at least one entry before
* we get control (with relocate on). The address is give to the hv
* as a page number (see xLparMap in LparData.c), so this must be at a
* fixed address (the linker can't compute (u64)&initial_stab >>
* PAGE_SHIFT).
*/
. = STAB0_PHYS_ADDR /* 0x6000 */
.globl initial_stab
initial_stab:
.space 4096
/*
* Data area reserved for FWNMI option.
* This address (0x7000) is fixed by the RPA.
@ -1265,19 +1280,6 @@ unrecov_slb:
fwnmi_data_area:
.space PAGE_SIZE
/*
* Space for the initial segment table
* For LPAR, the hypervisor must fill in at least one entry
* before we get control (with relocate on)
*/
. = STAB0_PHYS_ADDR
.globl __start_stab
__start_stab:
. = (STAB0_PHYS_ADDR + PAGE_SIZE)
.globl __end_stab
__end_stab:
/*
* On pSeries, secondary processors spin in the following code.
* At entry, r3 = this processor's number (physical cpu id)

4
arch/ppc64/kernel/pacaData.c
View File

@ -78,7 +78,7 @@ extern unsigned long __toc_start;
#define BOOTCPU_PACA_INIT(number) \
{ \
PACA_INIT_COMMON(number, 1, 0, STAB0_VIRT_ADDR) \
PACA_INIT_COMMON(number, 1, 0, (u64)&initial_stab) \
PACA_INIT_ISERIES(number) \
}
@ -90,7 +90,7 @@ extern unsigned long __toc_start;
#define BOOTCPU_PACA_INIT(number) \
{ \
PACA_INIT_COMMON(number, 1, STAB0_PHYS_ADDR, STAB0_VIRT_ADDR) \
PACA_INIT_COMMON(number, 1, STAB0_PHYS_ADDR, (u64)&initial_stab) \
}
#endif

7
include/asm-ppc64/mmu.h
View File

@ -28,9 +28,12 @@
#define STE_VSID_SHIFT 12
/* Location of cpu0's segment table */
#define STAB0_PAGE 0x9
#define STAB0_PAGE 0x6
#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
#ifndef __ASSEMBLY__
extern char initial_stab[];
#endif /* ! __ASSEMBLY */
/*
* SLB