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https://github.com/FEX-Emu/linux.git
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Merge branch 'mvpp2-optional-PHYs-and-GoP-link-irq'
Antoine Tenart says:
====================
net: mvpp2: optional PHYs and GoP link irq
This series aims at making the driver work when no PHY is connected
between a port and the physical layer and not described as a fixed-phy.
This is useful for some usecases such as when a switch is connected
directly to the serdes lanes. It can also be used for SFP ports on the
7k-db and 8k-db while waiting for the phylink support to land in (which
should be part of another series).
This series makes the phy optional in the PPv2 driver, and then adds
the support for the GoP port link interrupt to handle link status
changes on such ports.
This was tested using the SFP ports on the 7k-db and 8k-db boards.
Since v1:
- Now use phy_interface_mode_is_rgmii() in the GoP link patch.
- Added one cosmetic patch to take advantage of phy_interface_mode_is_rgmii()
in the whole PPv2 driver.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
c5b2cef3b6
@ -44,7 +44,7 @@ Optional properties (port):
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- interrupt-names: if more than a single interrupt for rx is given, must
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be the name associated to the interrupts listed. Valid
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names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",
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"rx-shared".
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"rx-shared", "link".
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- marvell,system-controller: a phandle to the system controller.
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Example for marvell,armada-375-pp2:
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@ -348,16 +348,24 @@
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#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
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#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVPP2_GMAC_STATUS0 0x10
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#define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
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#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
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MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
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#define MVPP22_GMAC_INT_STAT 0x20
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#define MVPP22_GMAC_INT_STAT_LINK BIT(1)
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#define MVPP22_GMAC_INT_MASK 0x24
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#define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)
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#define MVPP22_GMAC_CTRL_4_REG 0x90
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#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
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#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
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#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
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#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
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#define MVPP22_GMAC_INT_SUM_MASK 0xa4
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#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
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/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
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* relative to port->base.
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@ -370,11 +378,19 @@
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#define MVPP22_XLG_CTRL1_REG 0x104
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#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
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#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
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#define MVPP22_XLG_STATUS 0x10c
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#define MVPP22_XLG_STATUS_LINK_UP BIT(0)
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#define MVPP22_XLG_INT_STAT 0x114
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#define MVPP22_XLG_INT_STAT_LINK BIT(1)
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#define MVPP22_XLG_INT_MASK 0x118
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#define MVPP22_XLG_INT_MASK_LINK BIT(1)
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#define MVPP22_XLG_CTRL3_REG 0x11c
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#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
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#define MVPP22_XLG_EXT_INT_MASK 0x15c
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#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
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#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
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#define MVPP22_XLG_CTRL4_REG 0x184
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#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
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#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
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@ -837,6 +853,8 @@ struct mvpp2_port {
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*/
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int gop_id;
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int link_irq;
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struct mvpp2 *priv;
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/* Per-port registers' base address */
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@ -4422,6 +4440,68 @@ invalid_conf:
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return -EINVAL;
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}
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static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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/* Enable the GMAC link status irq for this port */
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val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
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val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
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}
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if (port->gop_id == 0) {
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/* Enable the XLG/GIG irqs for this port */
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val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
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if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
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val |= MVPP22_XLG_EXT_INT_MASK_XLG;
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else
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val |= MVPP22_XLG_EXT_INT_MASK_GIG;
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writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
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}
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}
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static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (port->gop_id == 0) {
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val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
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val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
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MVPP22_XLG_EXT_INT_MASK_GIG);
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writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
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}
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
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val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
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}
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}
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static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_MASK);
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val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_MASK);
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}
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if (port->gop_id == 0) {
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val = readl(port->base + MVPP22_XLG_INT_MASK);
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val |= MVPP22_XLG_INT_MASK_LINK;
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writel(val, port->base + MVPP22_XLG_INT_MASK);
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}
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mvpp22_gop_unmask_irq(port);
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}
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static int mvpp22_comphy_init(struct mvpp2_port *port)
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{
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enum phy_mode mode;
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@ -4463,10 +4543,7 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
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val |= MVPP2_GMAC_DISABLE_PADDING;
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val &= ~MVPP2_GMAC_FLOW_CTRL_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
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val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
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MVPP22_CTRL4_SYNC_BYPASS_DIS |
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@ -4512,10 +4589,7 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
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} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
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val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
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val |= MVPP2_GMAC_PORT_RGMII_MASK;
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}
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@ -4575,10 +4649,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
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if (port->priv->hw_version == MVPP22)
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mvpp22_port_mii_set(port);
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if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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mvpp2_port_mii_gmac_configure(port);
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else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
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@ -5735,6 +5806,60 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/* Per-port interrupt for link status changes */
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static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
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{
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struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
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struct net_device *dev = port->dev;
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bool event = false, link = false;
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u32 val;
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mvpp22_gop_mask_irq(port);
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if (port->gop_id == 0 &&
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port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
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val = readl(port->base + MVPP22_XLG_INT_STAT);
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if (val & MVPP22_XLG_INT_STAT_LINK) {
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event = true;
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val = readl(port->base + MVPP22_XLG_STATUS);
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if (val & MVPP22_XLG_STATUS_LINK_UP)
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link = true;
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}
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} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_STAT);
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if (val & MVPP22_GMAC_INT_STAT_LINK) {
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event = true;
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val = readl(port->base + MVPP2_GMAC_STATUS0);
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if (val & MVPP2_GMAC_STATUS0_LINK_UP)
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link = true;
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}
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}
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if (!netif_running(dev) || !event)
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goto handled;
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if (link) {
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mvpp2_interrupts_enable(port);
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mvpp2_egress_enable(port);
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mvpp2_ingress_enable(port);
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netif_carrier_on(dev);
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netif_tx_wake_all_queues(dev);
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} else {
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netif_tx_stop_all_queues(dev);
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netif_carrier_off(dev);
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mvpp2_ingress_disable(port);
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mvpp2_egress_disable(port);
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mvpp2_interrupts_disable(port);
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}
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handled:
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mvpp22_gop_unmask_irq(port);
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return IRQ_HANDLED;
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}
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static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,
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struct phy_device *phydev)
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{
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@ -5763,7 +5888,6 @@ static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,
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val |= MVPP2_GMAC_CONFIG_MII_SPEED;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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/* Adjust link */
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@ -6484,7 +6608,8 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
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mvpp2_port_mii_set(port);
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mvpp2_port_enable(port);
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phy_start(ndev->phydev);
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if (ndev->phydev)
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phy_start(ndev->phydev);
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netif_tx_start_all_queues(port->dev);
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}
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@ -6510,7 +6635,8 @@ static void mvpp2_stop_dev(struct mvpp2_port *port)
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mvpp2_egress_disable(port);
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mvpp2_port_disable(port);
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phy_stop(ndev->phydev);
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if (ndev->phydev)
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phy_stop(ndev->phydev);
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phy_power_off(port->comphy);
|
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}
|
||||
|
||||
@ -6567,6 +6693,10 @@ static int mvpp2_phy_connect(struct mvpp2_port *port)
|
||||
{
|
||||
struct phy_device *phy_dev;
|
||||
|
||||
/* No PHY is attached */
|
||||
if (!port->phy_node)
|
||||
return 0;
|
||||
|
||||
phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0,
|
||||
port->phy_interface);
|
||||
if (!phy_dev) {
|
||||
@ -6587,6 +6717,9 @@ static void mvpp2_phy_disconnect(struct mvpp2_port *port)
|
||||
{
|
||||
struct net_device *ndev = port->dev;
|
||||
|
||||
if (!ndev->phydev)
|
||||
return;
|
||||
|
||||
phy_disconnect(ndev->phydev);
|
||||
}
|
||||
|
||||
@ -6633,6 +6766,7 @@ static void mvpp2_irqs_deinit(struct mvpp2_port *port)
|
||||
static int mvpp2_open(struct net_device *dev)
|
||||
{
|
||||
struct mvpp2_port *port = netdev_priv(dev);
|
||||
struct mvpp2 *priv = port->priv;
|
||||
unsigned char mac_bcast[ETH_ALEN] = {
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
||||
int err;
|
||||
@ -6678,12 +6812,24 @@ static int mvpp2_open(struct net_device *dev)
|
||||
goto err_cleanup_txqs;
|
||||
}
|
||||
|
||||
if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) {
|
||||
err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
|
||||
dev->name, port);
|
||||
if (err) {
|
||||
netdev_err(port->dev, "cannot request link IRQ %d\n",
|
||||
port->link_irq);
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
mvpp22_gop_setup_irq(port);
|
||||
}
|
||||
|
||||
/* In default link is down */
|
||||
netif_carrier_off(port->dev);
|
||||
|
||||
err = mvpp2_phy_connect(port);
|
||||
if (err < 0)
|
||||
goto err_free_irq;
|
||||
goto err_free_link_irq;
|
||||
|
||||
/* Unmask interrupts on all CPUs */
|
||||
on_each_cpu(mvpp2_interrupts_unmask, port, 1);
|
||||
@ -6693,6 +6839,9 @@ static int mvpp2_open(struct net_device *dev)
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_link_irq:
|
||||
if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
|
||||
free_irq(port->link_irq, port);
|
||||
err_free_irq:
|
||||
mvpp2_irqs_deinit(port);
|
||||
err_cleanup_txqs:
|
||||
@ -6706,6 +6855,7 @@ static int mvpp2_stop(struct net_device *dev)
|
||||
{
|
||||
struct mvpp2_port *port = netdev_priv(dev);
|
||||
struct mvpp2_port_pcpu *port_pcpu;
|
||||
struct mvpp2 *priv = port->priv;
|
||||
int cpu;
|
||||
|
||||
mvpp2_stop_dev(port);
|
||||
@ -6715,6 +6865,9 @@ static int mvpp2_stop(struct net_device *dev)
|
||||
on_each_cpu(mvpp2_interrupts_mask, port, 1);
|
||||
mvpp2_shared_interrupt_mask_unmask(port, true);
|
||||
|
||||
if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
|
||||
free_irq(port->link_irq, port);
|
||||
|
||||
mvpp2_irqs_deinit(port);
|
||||
if (!port->has_tx_irqs) {
|
||||
for_each_present_cpu(cpu) {
|
||||
@ -7349,12 +7502,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
phy_node = of_parse_phandle(port_node, "phy", 0);
|
||||
if (!phy_node) {
|
||||
dev_err(&pdev->dev, "missing phy\n");
|
||||
err = -ENODEV;
|
||||
goto err_free_netdev;
|
||||
}
|
||||
|
||||
phy_mode = of_get_phy_mode(port_node);
|
||||
if (phy_mode < 0) {
|
||||
dev_err(&pdev->dev, "incorrect phy mode\n");
|
||||
@ -7393,6 +7540,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
|
||||
if (err)
|
||||
goto err_free_netdev;
|
||||
|
||||
port->link_irq = of_irq_get_byname(port_node, "link");
|
||||
if (port->link_irq == -EPROBE_DEFER) {
|
||||
err = -EPROBE_DEFER;
|
||||
goto err_deinit_qvecs;
|
||||
}
|
||||
if (port->link_irq <= 0)
|
||||
/* the link irq is optional */
|
||||
port->link_irq = 0;
|
||||
|
||||
if (of_property_read_bool(port_node, "marvell,loopback"))
|
||||
port->flags |= MVPP2_F_LOOPBACK;
|
||||
|
||||
@ -7411,7 +7567,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
|
||||
port->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(port->base)) {
|
||||
err = PTR_ERR(port->base);
|
||||
goto err_deinit_qvecs;
|
||||
goto err_free_irq;
|
||||
}
|
||||
} else {
|
||||
if (of_property_read_u32(port_node, "gop-port-id",
|
||||
@ -7428,7 +7584,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
|
||||
port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
|
||||
if (!port->stats) {
|
||||
err = -ENOMEM;
|
||||
goto err_deinit_qvecs;
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
dt_mac_addr = of_get_mac_address(port_node);
|
||||
@ -7512,6 +7668,9 @@ err_free_txq_pcpu:
|
||||
free_percpu(port->txqs[i]->pcpu);
|
||||
err_free_stats:
|
||||
free_percpu(port->stats);
|
||||
err_free_irq:
|
||||
if (port->link_irq)
|
||||
irq_dispose_mapping(port->link_irq);
|
||||
err_deinit_qvecs:
|
||||
mvpp2_queue_vectors_deinit(port);
|
||||
err_free_netdev:
|
||||
@ -7532,6 +7691,8 @@ static void mvpp2_port_remove(struct mvpp2_port *port)
|
||||
for (i = 0; i < port->ntxqs; i++)
|
||||
free_percpu(port->txqs[i]->pcpu);
|
||||
mvpp2_queue_vectors_deinit(port);
|
||||
if (port->link_irq)
|
||||
irq_dispose_mapping(port->link_irq);
|
||||
free_netdev(port->dev);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user