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OHCI: final fix for NVIDIA problems (I hope)

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Problems with NVIDIA's OHCI host controllers persist.  After looking
carefully through the spec, I finally realized that when a controller
is reset it then automatically goes into a SUSPEND state in which it
is completely quiescent (no DMA and no IRQs) and from which it will
not awaken until the system puts it into the OPERATIONAL state.

Therefore there's no need to worry about controllers being in the
RESET state for extended periods, or remaining in the OPERATIONAL
state during system shutdown.  The proper action for device
initialization is to put the controller into the RESET state (if it's
not there already) and then to issue a software reset.  Similarly, the
proper action for device shutdown is simply to do a software reset.

This patch (as1499) implements such an approach.  It simplifies
initialization and shutdown, and allows the NVIDIA shutdown-quirk code
to be removed.

Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Tested-by: Andre "Osku" Schmidt <andre.osku.schmidt@googlemail.com>
Tested-by: Arno Augustin <Arno.Augustin@web.de>
Cc: stable <stable@vger.kernel.org> [after tested in 3.2 for a while]
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Stern 2011-11-17 16:41:45 -05:00 committed by Greg Kroah-Hartman
parent 46b5a277ed
commit c618759774
4 changed files with 29 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/usb/host/ohci-hcd.c
View File

@ -389,17 +389,14 @@ ohci_shutdown (struct usb_hcd *hcd)
struct ohci_hcd *ohci; struct ohci_hcd *ohci;
ohci = hcd_to_ohci (hcd); ohci = hcd_to_ohci (hcd);
ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
/* If the SHUTDOWN quirk is set, don't put the controller in RESET */ /* Software reset, after which the controller goes into SUSPEND */
ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ? ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
OHCI_CTRL_RWC | OHCI_CTRL_HCFS : ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
OHCI_CTRL_RWC); udelay(10);
ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
/* flush the writes */ ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
(void) ohci_readl (ohci, &ohci->regs->control);
} }
static int check_ed(struct ohci_hcd *ohci, struct ed *ed) static int check_ed(struct ohci_hcd *ohci, struct ed *ed)

26
drivers/usb/host/ohci-pci.c
View File

@ -175,28 +175,6 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
return 0; return 0;
} }
/* nVidia controllers continue to drive Reset signalling on the bus
* even after system shutdown, wasting power. This flag tells the
* shutdown routine to leave the controller OPERATIONAL instead of RESET.
*/
static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd)
{
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
/* Evidently nVidia fixed their later hardware; this is a guess at
* the changeover point.
*/
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB 0x026d
if (pdev->device < PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB) {
ohci->flags |= OHCI_QUIRK_SHUTDOWN;
ohci_dbg(ohci, "enabled nVidia shutdown quirk\n");
}
return 0;
}
static void sb800_prefetch(struct ohci_hcd *ohci, int on) static void sb800_prefetch(struct ohci_hcd *ohci, int on)
{ {
struct pci_dev *pdev; struct pci_dev *pdev;
@ -260,10 +238,6 @@ static const struct pci_device_id ohci_pci_quirks[] = {
PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
.driver_data = (unsigned long)ohci_quirk_amd700, .driver_data = (unsigned long)ohci_quirk_amd700,
}, },
{
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
.driver_data = (unsigned long) ohci_quirk_nvidia_shutdown,
},
/* FIXME for some of the early AMD 760 southbridges, OHCI /* FIXME for some of the early AMD 760 southbridges, OHCI
* won't work at all. blacklist them. * won't work at all. blacklist them.

1
drivers/usb/host/ohci.h
View File

@ -403,7 +403,6 @@ struct ohci_hcd {
#define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */
#define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/ #define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/
#define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */
#define OHCI_QUIRK_SHUTDOWN 0x800 /* nVidia power bug */
// there are also chip quirks/bugs in init logic // there are also chip quirks/bugs in init logic
struct work_struct nec_work; /* Worker for NEC quirk */ struct work_struct nec_work; /* Worker for NEC quirk */

52
drivers/usb/host/pci-quirks.c
View File

@ -37,6 +37,7 @@
#define OHCI_INTRENABLE 0x10 #define OHCI_INTRENABLE 0x10
#define OHCI_INTRDISABLE 0x14 #define OHCI_INTRDISABLE 0x14
#define OHCI_FMINTERVAL 0x34 #define OHCI_FMINTERVAL 0x34
#define OHCI_HCFS (3 << 6) /* hc functional state */
#define OHCI_HCR (1 << 0) /* host controller reset */ #define OHCI_HCR (1 << 0) /* host controller reset */
#define OHCI_OCR (1 << 3) /* ownership change request */ #define OHCI_OCR (1 << 3) /* ownership change request */
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
@ -466,6 +467,8 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
{ {
void __iomem *base; void __iomem *base;
u32 control; u32 control;
u32 fminterval;
int cnt;
if (!mmio_resource_enabled(pdev, 0)) if (!mmio_resource_enabled(pdev, 0))
return; return;
@ -498,41 +501,32 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
} }
#endif #endif
/* reset controller, preserving RWC (and possibly IR) */ /* disable interrupts */
writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); writel((u32) ~0, base + OHCI_INTRDISABLE);
readl(base + OHCI_CONTROL);
/* Some NVIDIA controllers stop working if kept in RESET for too long */ /* Reset the USB bus, if the controller isn't already in RESET */
if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { if (control & OHCI_HCFS) {
u32 fminterval; /* Go into RESET, preserving RWC (and possibly IR) */
int cnt; writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
readl(base + OHCI_CONTROL);
/* drive reset for at least 50 ms (7.1.7.5) */ /* drive bus reset for at least 50 ms (7.1.7.5) */
msleep(50); msleep(50);
/* software reset of the controller, preserving HcFmInterval */
fminterval = readl(base + OHCI_FMINTERVAL);
writel(OHCI_HCR, base + OHCI_CMDSTATUS);
/* reset requires max 10 us delay */
for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
break;
udelay(1);
}
writel(fminterval, base + OHCI_FMINTERVAL);
/* Now we're in the SUSPEND state with all devices reset
* and wakeups and interrupts disabled
*/
} }
/* /* software reset of the controller, preserving HcFmInterval */
* disable interrupts fminterval = readl(base + OHCI_FMINTERVAL);
*/ writel(OHCI_HCR, base + OHCI_CMDSTATUS);
writel(~(u32)0, base + OHCI_INTRDISABLE);
writel(~(u32)0, base + OHCI_INTRSTATUS);
/* reset requires max 10 us delay */
for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
break;
udelay(1);
}
writel(fminterval, base + OHCI_FMINTERVAL);
/* Now the controller is safely in SUSPEND and nothing can wake it up */
iounmap(base); iounmap(base);
} }