mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-16 22:10:24 +00:00
Merge branch 'fix/hda' into for-linus
This commit is contained in:
Takashi Iwai
commit
c7a441bba9
1
.gitignore
vendored
1
.gitignore
vendored
@ -28,6 +28,7 @@ modules.builtin
|
||||
*.gz
|
||||
*.bz2
|
||||
*.lzma
|
||||
*.lzo
|
||||
*.patch
|
||||
*.gcno
|
||||
|
||||
|
||||
7
Documentation/.gitignore
vendored
Normal file
7
Documentation/.gitignore
vendored
Normal file
@ -0,0 +1,7 @@
|
||||
filesystems/dnotify_test
|
||||
laptops/dslm
|
||||
timers/hpet_example
|
||||
vm/hugepage-mmap
|
||||
vm/hugepage-shm
|
||||
vm/map_hugetlb
|
||||
|
||||
@ -65,7 +65,7 @@ CROSS_COMPILE
|
||||
Specify an optional fixed part of the binutils filename.
|
||||
CROSS_COMPILE can be a part of the filename or the full path.
|
||||
|
||||
CROSS_COMPILE is also used for ccache is some setups.
|
||||
CROSS_COMPILE is also used for ccache in some setups.
|
||||
|
||||
CF
|
||||
--------------------------------------------------
|
||||
@ -162,3 +162,7 @@ For tags/TAGS/cscope targets, you can specify more than one arch
|
||||
to be included in the databases, separated by blank space. E.g.:
|
||||
|
||||
$ make ALLSOURCE_ARCHS="x86 mips arm" tags
|
||||
|
||||
To get all available archs you can also specify all. E.g.:
|
||||
|
||||
$ make ALLSOURCE_ARCHS=all tags
|
||||
|
||||
@ -66,14 +66,14 @@ of advantages of mutexes:
|
||||
|
||||
c0377ccb <mutex_lock>:
|
||||
c0377ccb: f0 ff 08 lock decl (%eax)
|
||||
c0377cce: 78 0e js c0377cde <.text.lock.mutex>
|
||||
c0377cce: 78 0e js c0377cde <.text..lock.mutex>
|
||||
c0377cd0: c3 ret
|
||||
|
||||
the unlocking fastpath is equally tight:
|
||||
|
||||
c0377cd1 <mutex_unlock>:
|
||||
c0377cd1: f0 ff 00 lock incl (%eax)
|
||||
c0377cd4: 7e 0f jle c0377ce5 <.text.lock.mutex+0x7>
|
||||
c0377cd4: 7e 0f jle c0377ce5 <.text..lock.mutex+0x7>
|
||||
c0377cd6: c3 ret
|
||||
|
||||
- 'struct mutex' semantics are well-defined and are enforced if
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
obj- := dummy.o
|
||||
|
||||
# List of programs to build
|
||||
hostprogs-y := hpet_example
|
||||
hostprogs-$(CONFIG_X86) := hpet_example
|
||||
|
||||
# Tell kbuild to always build the programs
|
||||
always := $(hostprogs-y)
|
||||
|
||||
@ -3242,7 +3242,7 @@ L: autofs@linux.kernel.org
|
||||
S: Maintained
|
||||
F: fs/autofs4/
|
||||
|
||||
KERNEL BUILD
|
||||
KERNEL BUILD + files below scripts/ (unless maintained elsewhere)
|
||||
M: Michal Marek <mmarek@suse.cz>
|
||||
T: git git://repo.or.cz/linux-kbuild.git for-next
|
||||
T: git git://repo.or.cz/linux-kbuild.git for-linus
|
||||
@ -3251,6 +3251,9 @@ S: Maintained
|
||||
F: Documentation/kbuild/
|
||||
F: Makefile
|
||||
F: scripts/Makefile.*
|
||||
F: scripts/basic/
|
||||
F: scripts/mk*
|
||||
F: scripts/package/
|
||||
|
||||
KERNEL JANITORS
|
||||
L: kernel-janitors@vger.kernel.org
|
||||
|
||||
65
Makefile
65
Makefile
@ -183,11 +183,14 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
|
||||
# CROSS_COMPILE can be set on the command line
|
||||
# make CROSS_COMPILE=ia64-linux-
|
||||
# Alternatively CROSS_COMPILE can be set in the environment.
|
||||
# A third alternative is to store a setting in .config so that plain
|
||||
# "make" in the configured kernel build directory always uses that.
|
||||
# Default value for CROSS_COMPILE is not to prefix executables
|
||||
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
|
||||
export KBUILD_BUILDHOST := $(SUBARCH)
|
||||
ARCH ?= $(SUBARCH)
|
||||
CROSS_COMPILE ?=
|
||||
CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
|
||||
|
||||
# Architecture as present in compile.h
|
||||
UTS_MACHINE := $(ARCH)
|
||||
@ -576,9 +579,6 @@ KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,)
|
||||
# disable invalid "can't wrap" optimizations for signed / pointers
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow)
|
||||
|
||||
# revert to pre-gcc-4.4 behaviour of .eh_frame
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
|
||||
|
||||
# conserve stack if available
|
||||
KBUILD_CFLAGS += $(call cc-option,-fconserve-stack)
|
||||
|
||||
@ -882,9 +882,6 @@ $(sort $(vmlinux-init) $(vmlinux-main)) $(vmlinux-lds): $(vmlinux-dirs) ;
|
||||
PHONY += $(vmlinux-dirs)
|
||||
$(vmlinux-dirs): prepare scripts
|
||||
$(Q)$(MAKE) $(build)=$@
|
||||
ifdef CONFIG_MODULES
|
||||
$(Q)$(MAKE) $(modbuiltin)=$@
|
||||
endif
|
||||
|
||||
# Build the kernel release string
|
||||
#
|
||||
@ -907,14 +904,19 @@ endif
|
||||
# $(localver)
|
||||
# localversion* (files without backups, containing '~')
|
||||
# $(CONFIG_LOCALVERSION) (from kernel config setting)
|
||||
# $(localver-auto) (only if CONFIG_LOCALVERSION_AUTO is set)
|
||||
# ./scripts/setlocalversion (SCM tag, if one exists)
|
||||
# $(LOCALVERSION) (from make command line if provided)
|
||||
# $(LOCALVERSION) (from make command line, if provided)
|
||||
# $(localver-extra)
|
||||
# $(scm-identifier) (unique SCM tag, if one exists)
|
||||
# ./scripts/setlocalversion (only with CONFIG_LOCALVERSION_AUTO)
|
||||
# .scmversion (only with CONFIG_LOCALVERSION_AUTO)
|
||||
# + (only without CONFIG_LOCALVERSION_AUTO
|
||||
# and without LOCALVERSION= and
|
||||
# repository is at non-tagged commit)
|
||||
#
|
||||
# Note how the final $(localver-auto) string is included *only* if the
|
||||
# kernel config option CONFIG_LOCALVERSION_AUTO is selected. Also, at the
|
||||
# moment, only git is supported but other SCMs can edit the script
|
||||
# scripts/setlocalversion and add the appropriate checks as needed.
|
||||
# For kernels without CONFIG_LOCALVERSION_AUTO compiled from an SCM that has
|
||||
# been revised beyond a tagged commit, `+' is appended to the version string
|
||||
# when not overridden by using "make LOCALVERSION=". This indicates that the
|
||||
# kernel is not a vanilla release version and has been modified.
|
||||
|
||||
pattern = ".*/localversion[^~]*"
|
||||
string = $(shell cat /dev/null \
|
||||
@ -923,26 +925,32 @@ string = $(shell cat /dev/null \
|
||||
localver = $(subst $(space),, $(string) \
|
||||
$(patsubst "%",%,$(CONFIG_LOCALVERSION)))
|
||||
|
||||
# If CONFIG_LOCALVERSION_AUTO is set scripts/setlocalversion is called
|
||||
# and if the SCM is know a tag from the SCM is appended.
|
||||
# The appended tag is determined by the SCM used.
|
||||
# scripts/setlocalversion is called to create a unique identifier if the source
|
||||
# is managed by a known SCM and the repository has been revised since the last
|
||||
# tagged (release) commit. The format of the identifier is determined by the
|
||||
# SCM's implementation.
|
||||
#
|
||||
# .scmversion is used when generating rpm packages so we do not loose
|
||||
# the version information from the SCM when we do the build of the kernel
|
||||
# from the copied source
|
||||
ifdef CONFIG_LOCALVERSION_AUTO
|
||||
|
||||
ifeq ($(wildcard .scmversion),)
|
||||
_localver-auto = $(shell $(CONFIG_SHELL) \
|
||||
scm-identifier = $(shell $(CONFIG_SHELL) \
|
||||
$(srctree)/scripts/setlocalversion $(srctree))
|
||||
else
|
||||
_localver-auto = $(shell cat .scmversion 2> /dev/null)
|
||||
scm-identifier = $(shell cat .scmversion 2> /dev/null)
|
||||
endif
|
||||
|
||||
localver-auto = $(LOCALVERSION)$(_localver-auto)
|
||||
ifdef CONFIG_LOCALVERSION_AUTO
|
||||
localver-extra = $(scm-identifier)
|
||||
else
|
||||
ifneq ($(scm-identifier),)
|
||||
ifeq ($(LOCALVERSION),)
|
||||
localver-extra = +
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
localver-full = $(localver)$(localver-auto)
|
||||
localver-full = $(localver)$(LOCALVERSION)$(localver-extra)
|
||||
|
||||
# Store (new) KERNELRELASE string in include/config/kernel.release
|
||||
kernelrelease = $(KERNELVERSION)$(localver-full)
|
||||
@ -1089,11 +1097,16 @@ all: modules
|
||||
PHONY += modules
|
||||
modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux)
|
||||
$(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.order) > $(objtree)/modules.order
|
||||
$(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.builtin) > $(objtree)/modules.builtin
|
||||
@$(kecho) ' Building modules, stage 2.';
|
||||
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
|
||||
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modbuild
|
||||
|
||||
modules.builtin: $(vmlinux-dirs:%=%/modules.builtin)
|
||||
$(Q)$(AWK) '!x[$$0]++' $^ > $(objtree)/modules.builtin
|
||||
|
||||
%/modules.builtin: include/config/auto.conf
|
||||
$(Q)$(MAKE) $(modbuiltin)=$*
|
||||
|
||||
|
||||
# Target to prepare building external modules
|
||||
PHONY += modules_prepare
|
||||
@ -1104,7 +1117,7 @@ PHONY += modules_install
|
||||
modules_install: _modinst_ _modinst_post
|
||||
|
||||
PHONY += _modinst_
|
||||
_modinst_:
|
||||
_modinst_: modules.builtin
|
||||
@if [ -z "`$(DEPMOD) -V 2>/dev/null | grep module-init-tools`" ]; then \
|
||||
echo "Warning: you may need to install module-init-tools"; \
|
||||
echo "See http://www.codemonkey.org.uk/docs/post-halloween-2.6.txt";\
|
||||
@ -1247,7 +1260,9 @@ help:
|
||||
@echo ' firmware_install- Install all firmware to INSTALL_FW_PATH'
|
||||
@echo ' (default: $$(INSTALL_MOD_PATH)/lib/firmware)'
|
||||
@echo ' dir/ - Build all files in dir and below'
|
||||
@echo ' dir/file.[ois] - Build specified target only'
|
||||
@echo ' dir/file.[oisS] - Build specified target only'
|
||||
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
|
||||
@echo ' (requires a recent binutils and recent build (System.map))'
|
||||
@echo ' dir/file.ko - Build module including final link'
|
||||
@echo ' modules_prepare - Set up for building external modules'
|
||||
@echo ' tags/TAGS - Generate tags file for editors'
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/smp_lock.h>
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/capability.h>
|
||||
|
||||
@ -238,9 +239,7 @@ static unsigned char days_in_mo[] =
|
||||
|
||||
/* ioctl that supports RTC_RD_TIME and RTC_SET_TIME (read and set time/date). */
|
||||
|
||||
static int
|
||||
rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
static int rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
@ -354,6 +353,17 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
|
||||
}
|
||||
}
|
||||
|
||||
static long rtc_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
lock_kernel();
|
||||
ret = rtc_ioctl(file, cmd, arg);
|
||||
unlock_kernel();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
print_rtc_status(void)
|
||||
{
|
||||
@ -375,8 +385,8 @@ print_rtc_status(void)
|
||||
/* The various file operations we support. */
|
||||
|
||||
static const struct file_operations rtc_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.ioctl = rtc_ioctl,
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = rtc_unlocked_ioctl,
|
||||
};
|
||||
|
||||
/* Probe for the chip by writing something to its RAM and try reading it back. */
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/smp_lock.h>
|
||||
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/system.h>
|
||||
@ -53,7 +54,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
|
||||
static const unsigned char days_in_month[] =
|
||||
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
|
||||
|
||||
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
|
||||
static long pcf8563_unlocked_ioctl(struct file *, unsigned int, unsigned long);
|
||||
|
||||
/* Cache VL bit value read at driver init since writing the RTC_SECOND
|
||||
* register clears the VL status.
|
||||
@ -62,7 +63,7 @@ static int voltage_low;
|
||||
|
||||
static const struct file_operations pcf8563_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.ioctl = pcf8563_ioctl,
|
||||
.unlocked_ioctl = pcf8563_unlocked_ioctl,
|
||||
};
|
||||
|
||||
unsigned char
|
||||
@ -212,8 +213,7 @@ pcf8563_exit(void)
|
||||
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
|
||||
* POSIX says so!
|
||||
*/
|
||||
int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
/* Some sanity checks. */
|
||||
if (_IOC_TYPE(cmd) != RTC_MAGIC)
|
||||
@ -339,6 +339,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
lock_kernel();
|
||||
return pcf8563_ioctl(filp, cmd, arg);
|
||||
unlock_kernel();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init pcf8563_register(void)
|
||||
{
|
||||
if (pcf8563_init() < 0) {
|
||||
|
||||
@ -17,8 +17,8 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
|
||||
#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
|
||||
#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
|
||||
#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
|
||||
|
||||
/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
|
||||
* global just so that the kernel gdb can use it.
|
||||
@ -116,12 +116,12 @@ static unsigned int startup_crisv10_irq(unsigned int irq)
|
||||
|
||||
static void enable_crisv10_irq(unsigned int irq)
|
||||
{
|
||||
unmask_irq(irq);
|
||||
crisv10_unmask_irq(irq);
|
||||
}
|
||||
|
||||
static void disable_crisv10_irq(unsigned int irq)
|
||||
{
|
||||
mask_irq(irq);
|
||||
crisv10_mask_irq(irq);
|
||||
}
|
||||
|
||||
static void ack_crisv10_irq(unsigned int irq)
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
/* $Id: dmacopy.c,v 1.1 2001/12/17 13:59:27 bjornw Exp $
|
||||
*
|
||||
/*
|
||||
* memcpy for large blocks, using memory-memory DMA channels 6 and 7 in Etrax
|
||||
*/
|
||||
|
||||
@ -13,11 +12,11 @@ void *dma_memcpy(void *pdst,
|
||||
unsigned int pn)
|
||||
{
|
||||
static etrax_dma_descr indma, outdma;
|
||||
|
||||
D(printk("dma_memcpy %d bytes... ", pn));
|
||||
|
||||
D(printk(KERN_DEBUG "dma_memcpy %d bytes... ", pn));
|
||||
|
||||
#if 0
|
||||
*R_GEN_CONFIG = genconfig_shadow =
|
||||
*R_GEN_CONFIG = genconfig_shadow =
|
||||
(genconfig_shadow & ~0x3c0000) |
|
||||
IO_STATE(R_GEN_CONFIG, dma6, intdma7) |
|
||||
IO_STATE(R_GEN_CONFIG, dma7, intdma6);
|
||||
@ -32,11 +31,11 @@ void *dma_memcpy(void *pdst,
|
||||
*R_DMA_CH7_FIRST = &outdma;
|
||||
*R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start);
|
||||
*R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start);
|
||||
|
||||
while(*R_DMA_CH7_CMD == 1) /* wait for completion */ ;
|
||||
|
||||
D(printk("done\n"));
|
||||
while (*R_DMA_CH7_CMD == 1)
|
||||
/* wait for completion */;
|
||||
|
||||
D(printk(KERN_DEBUG "done\n"));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,13 +1,11 @@
|
||||
/*
|
||||
* $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
|
||||
*
|
||||
* This table is used by some tools to extract hardware parameters.
|
||||
* The table should be included in the kernel and the decompressor.
|
||||
* Don't forget to update the tools if you change this table.
|
||||
*
|
||||
* Copyright (C) 2001 Axis Communications AB
|
||||
*
|
||||
* Authors: Mikael Starvik (starvik@axis.com)
|
||||
* Authors: Mikael Starvik (starvik@axis.com)
|
||||
*/
|
||||
|
||||
#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
|
||||
@ -15,13 +13,13 @@
|
||||
#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
|
||||
(CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
|
||||
(CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
|
||||
|
||||
|
||||
.ascii "HW_PARAM_MAGIC" ; Magic number
|
||||
.dword 0xc0004000 ; Kernel start address
|
||||
|
||||
; Debug port
|
||||
#ifdef CONFIG_ETRAX_DEBUG_PORT0
|
||||
.dword 0
|
||||
.dword 0
|
||||
#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
|
||||
.dword 1
|
||||
#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
|
||||
@ -30,7 +28,7 @@
|
||||
.dword 3
|
||||
#else
|
||||
.dword 4 ; No debug
|
||||
#endif
|
||||
#endif
|
||||
|
||||
; SDRAM or EDO DRAM?
|
||||
#ifdef CONFIG_ETRAX_SDRAM
|
||||
@ -39,7 +37,7 @@
|
||||
.dword 0
|
||||
#endif
|
||||
|
||||
; Register values
|
||||
; Register values
|
||||
.dword R_WAITSTATES
|
||||
.dword CONFIG_ETRAX_DEF_R_WAITSTATES
|
||||
.dword R_BUS_CONFIG
|
||||
@ -56,7 +54,7 @@
|
||||
.dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
|
||||
#endif
|
||||
.dword R_PORT_PA_SET
|
||||
.dword PA_SET_VALUE
|
||||
.dword PA_SET_VALUE
|
||||
.dword R_PORT_PB_SET
|
||||
.dword PB_SET_VALUE
|
||||
.dword 0 ; No more register values
|
||||
|
||||
@ -360,24 +360,10 @@ config ETRAX_SER4_DSR_BIT
|
||||
string "Ser 4 DSR bit (empty = not used)"
|
||||
depends on ETRAX_SERIAL_PORT4
|
||||
|
||||
config ETRAX_SER3_CD_BIT
|
||||
config ETRAX_SER4_CD_BIT
|
||||
string "Ser 4 CD bit (empty = not used)"
|
||||
depends on ETRAX_SERIAL_PORT4
|
||||
|
||||
config ETRAX_RS485
|
||||
bool "RS-485 support"
|
||||
depends on ETRAXFS_SERIAL
|
||||
help
|
||||
Enables support for RS-485 serial communication. For a primer on
|
||||
RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
|
||||
|
||||
config ETRAX_RS485_DISABLE_RECEIVER
|
||||
bool "Disable serial receiver"
|
||||
depends on ETRAX_RS485
|
||||
help
|
||||
It is necessary to disable the serial receiver to avoid serial
|
||||
loopback. Not all products are able to do this in software only.
|
||||
|
||||
config ETRAX_SYNCHRONOUS_SERIAL
|
||||
bool "Synchronous serial-port support"
|
||||
depends on ETRAX_ARCH_V32
|
||||
|
||||
@ -649,10 +649,10 @@ i2c_release(struct inode *inode, struct file *filp)
|
||||
/* Main device API. ioctl's to write or read to/from i2c registers.
|
||||
*/
|
||||
|
||||
static int
|
||||
i2c_ioctl(struct inode *inode, struct file *file,
|
||||
unsigned int cmd, unsigned long arg)
|
||||
static long
|
||||
i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret;
|
||||
if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
|
||||
return -ENOTTY;
|
||||
}
|
||||
@ -665,9 +665,13 @@ i2c_ioctl(struct inode *inode, struct file *file,
|
||||
I2C_ARGREG(arg),
|
||||
I2C_ARGVALUE(arg)));
|
||||
|
||||
return i2c_writereg(I2C_ARGSLAVE(arg),
|
||||
lock_kernel();
|
||||
ret = i2c_writereg(I2C_ARGSLAVE(arg),
|
||||
I2C_ARGREG(arg),
|
||||
I2C_ARGVALUE(arg));
|
||||
unlock_kernel();
|
||||
return ret;
|
||||
|
||||
case I2C_READREG:
|
||||
{
|
||||
unsigned char val;
|
||||
@ -675,7 +679,9 @@ i2c_ioctl(struct inode *inode, struct file *file,
|
||||
D(printk("i2cr %d %d ",
|
||||
I2C_ARGSLAVE(arg),
|
||||
I2C_ARGREG(arg)));
|
||||
lock_kernel();
|
||||
val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
|
||||
unlock_kernel();
|
||||
D(printk("= %d\n", val));
|
||||
return val;
|
||||
}
|
||||
@ -688,10 +694,10 @@ i2c_ioctl(struct inode *inode, struct file *file,
|
||||
}
|
||||
|
||||
static const struct file_operations i2c_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.ioctl = i2c_ioctl,
|
||||
.open = i2c_open,
|
||||
.release = i2c_release,
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = i2c_ioctl,
|
||||
.open = i2c_open,
|
||||
.release = i2c_release,
|
||||
};
|
||||
|
||||
static int __init i2c_init(void)
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/smp_lock.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/mutex.h>
|
||||
@ -49,7 +50,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
|
||||
static const unsigned char days_in_month[] =
|
||||
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
|
||||
|
||||
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
|
||||
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
|
||||
|
||||
/* Cache VL bit value read at driver init since writing the RTC_SECOND
|
||||
* register clears the VL status.
|
||||
@ -57,8 +58,8 @@ int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
|
||||
static int voltage_low;
|
||||
|
||||
static const struct file_operations pcf8563_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.ioctl = pcf8563_ioctl
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = pcf8563_unlocked_ioctl,
|
||||
};
|
||||
|
||||
unsigned char
|
||||
@ -208,8 +209,7 @@ pcf8563_exit(void)
|
||||
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
|
||||
* POSIX says so!
|
||||
*/
|
||||
int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
/* Some sanity checks. */
|
||||
if (_IOC_TYPE(cmd) != RTC_MAGIC)
|
||||
@ -335,6 +335,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
lock_kernel();
|
||||
return pcf8563_ioctl(filp, cmd, arg);
|
||||
unlock_kernel();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init pcf8563_register(void)
|
||||
{
|
||||
if (pcf8563_init() < 0) {
|
||||
|
||||
@ -24,5 +24,5 @@ EXPORT_SYMBOL(crisv32_io_get_name);
|
||||
EXPORT_SYMBOL(crisv32_io_get);
|
||||
|
||||
/* Functions masking/unmasking interrupts */
|
||||
EXPORT_SYMBOL(mask_irq);
|
||||
EXPORT_SYMBOL(unmask_irq);
|
||||
EXPORT_SYMBOL(crisv32_mask_irq);
|
||||
EXPORT_SYMBOL(crisv32_unmask_irq);
|
||||
|
||||
@ -280,8 +280,7 @@ out:
|
||||
return cpu;
|
||||
}
|
||||
|
||||
void
|
||||
mask_irq(int irq)
|
||||
void crisv32_mask_irq(int irq)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
@ -289,8 +288,7 @@ mask_irq(int irq)
|
||||
block_irq(irq, cpu);
|
||||
}
|
||||
|
||||
void
|
||||
unmask_irq(int irq)
|
||||
void crisv32_unmask_irq(int irq)
|
||||
{
|
||||
unblock_irq(irq, irq_cpu(irq));
|
||||
}
|
||||
@ -298,23 +296,23 @@ unmask_irq(int irq)
|
||||
|
||||
static unsigned int startup_crisv32_irq(unsigned int irq)
|
||||
{
|
||||
unmask_irq(irq);
|
||||
crisv32_unmask_irq(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void shutdown_crisv32_irq(unsigned int irq)
|
||||
{
|
||||
mask_irq(irq);
|
||||
crisv32_mask_irq(irq);
|
||||
}
|
||||
|
||||
static void enable_crisv32_irq(unsigned int irq)
|
||||
{
|
||||
unmask_irq(irq);
|
||||
crisv32_unmask_irq(irq);
|
||||
}
|
||||
|
||||
static void disable_crisv32_irq(unsigned int irq)
|
||||
{
|
||||
mask_irq(irq);
|
||||
crisv32_mask_irq(irq);
|
||||
}
|
||||
|
||||
static void ack_crisv32_irq(unsigned int irq)
|
||||
|
||||
@ -168,8 +168,8 @@ void __init smp_callin(void)
|
||||
|
||||
/* Enable IRQ and idle */
|
||||
REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
|
||||
unmask_irq(IPI_INTR_VECT);
|
||||
unmask_irq(TIMER0_INTR_VECT);
|
||||
crisv32_unmask_irq(IPI_INTR_VECT);
|
||||
crisv32_unmask_irq(TIMER0_INTR_VECT);
|
||||
preempt_disable();
|
||||
notify_cpu_starting(cpu);
|
||||
local_irq_enable();
|
||||
|
||||
@ -93,15 +93,16 @@ void set_break_vector(int n, irqvectptr addr);
|
||||
"push $r10\n\t" /* push orig_r10 */ \
|
||||
"clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
|
||||
|
||||
/* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */
|
||||
/* BLOCK_IRQ and UNBLOCK_IRQ do the same as
|
||||
* crisv10_mask_irq and crisv10_unmask_irq */
|
||||
|
||||
#define BLOCK_IRQ(mask,nr) \
|
||||
"move.d " #mask ",$r0\n\t" \
|
||||
"move.d $r0,[0xb00000d8]\n\t"
|
||||
|
||||
"move.d $r0,[0xb00000d8]\n\t"
|
||||
|
||||
#define UNBLOCK_IRQ(mask) \
|
||||
"move.d " #mask ",$r0\n\t" \
|
||||
"move.d $r0,[0xb00000dc]\n\t"
|
||||
"move.d $r0,[0xb00000dc]\n\t"
|
||||
|
||||
#define IRQ_NAME2(nr) nr##_interrupt(void)
|
||||
#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
|
||||
|
||||
@ -23,8 +23,8 @@ struct etrax_interrupt_vector {
|
||||
|
||||
extern struct etrax_interrupt_vector *etrax_irv; /* head.S */
|
||||
|
||||
void mask_irq(int irq);
|
||||
void unmask_irq(int irq);
|
||||
void crisv32_mask_irq(int irq);
|
||||
void crisv32_unmask_irq(int irq);
|
||||
|
||||
void set_exception_vector(int n, irqvectptr addr);
|
||||
|
||||
|
||||
@ -2,22 +2,9 @@
|
||||
#define _ASMCRIS_PARAM_H
|
||||
|
||||
/* Currently we assume that HZ=100 is good for CRIS. */
|
||||
#ifdef __KERNEL__
|
||||
# define HZ CONFIG_HZ /* Internal kernel timer frequency */
|
||||
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
|
||||
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
|
||||
#endif
|
||||
|
||||
#ifndef HZ
|
||||
#define HZ 100
|
||||
#endif
|
||||
|
||||
#define EXEC_PAGESIZE 8192
|
||||
|
||||
#ifndef NOGROUP
|
||||
#define NOGROUP (-1)
|
||||
#endif
|
||||
#include <asm-generic/param.h>
|
||||
|
||||
#define MAXHOSTNAMELEN 64 /* max length of hostname */
|
||||
|
||||
#endif
|
||||
#endif /* _ASMCRIS_PARAM_H */
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#
|
||||
# the break handler has its own stack
|
||||
#
|
||||
.section .bss.stack
|
||||
.section .bss..stack
|
||||
.globl __break_user_context
|
||||
.balign THREAD_SIZE
|
||||
__break_stack:
|
||||
@ -63,7 +63,7 @@ __break_trace_through_exceptions:
|
||||
# entry point for Break Exceptions/Interrupts
|
||||
#
|
||||
###############################################################################
|
||||
.section .text.break
|
||||
.section .text..break
|
||||
.balign 4
|
||||
.globl __entry_break
|
||||
__entry_break:
|
||||
|
||||
@ -38,7 +38,7 @@
|
||||
|
||||
#define nr_syscalls ((syscall_table_size)/4)
|
||||
|
||||
.section .text.entry
|
||||
.section .text..entry
|
||||
.balign 4
|
||||
|
||||
.macro LEDS val
|
||||
|
||||
@ -542,7 +542,7 @@ __head_end:
|
||||
.size _boot, .-_boot
|
||||
|
||||
# provide a point for GDB to place a break
|
||||
.section .text.start,"ax"
|
||||
.section .text..start,"ax"
|
||||
.globl _start
|
||||
.balign 4
|
||||
_start:
|
||||
|
||||
@ -57,10 +57,10 @@ SECTIONS
|
||||
_text = .;
|
||||
_stext = .;
|
||||
.text : {
|
||||
*(.text.start)
|
||||
*(.text.entry)
|
||||
*(.text.break)
|
||||
*(.text.tlbmiss)
|
||||
*(.text..start)
|
||||
*(.text..entry)
|
||||
*(.text..break)
|
||||
*(.text..tlbmiss)
|
||||
TEXT_TEXT
|
||||
SCHED_TEXT
|
||||
LOCK_TEXT
|
||||
@ -114,7 +114,7 @@ SECTIONS
|
||||
|
||||
.sbss : { *(.sbss .sbss.*) }
|
||||
.bss : { *(.bss .bss.*) }
|
||||
.bss.stack : { *(.bss) }
|
||||
.bss..stack : { *(.bss) }
|
||||
|
||||
__bss_stop = .;
|
||||
_end = . ;
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/spr-regs.h>
|
||||
|
||||
.section .text.tlbmiss
|
||||
.section .text..tlbmiss
|
||||
.balign 4
|
||||
|
||||
.globl __entry_insn_mmu_miss
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
|
||||
#define SRAM_START 0xff4000
|
||||
|
||||
.section .text.startup
|
||||
.section .text..startup
|
||||
.global startup
|
||||
startup:
|
||||
mov.l #SRAM_START+0x8000, sp
|
||||
|
||||
@ -4,7 +4,7 @@ SECTIONS
|
||||
{
|
||||
__stext = . ;
|
||||
__text = .;
|
||||
*(.text.startup)
|
||||
*(.text..startup)
|
||||
*(.text)
|
||||
__etext = . ;
|
||||
}
|
||||
|
||||
@ -70,12 +70,12 @@ name:
|
||||
* path (ivt.S - TLB miss processing) or in places where it might not be
|
||||
* safe to use a "tpa" instruction (mca_asm.S - error recovery).
|
||||
*/
|
||||
.section ".data.patch.vtop", "a" // declare section & section attributes
|
||||
.section ".data..patch.vtop", "a" // declare section & section attributes
|
||||
.previous
|
||||
|
||||
#define LOAD_PHYSICAL(pr, reg, obj) \
|
||||
[1:](pr)movl reg = obj; \
|
||||
.xdata4 ".data.patch.vtop", 1b-.
|
||||
.xdata4 ".data..patch.vtop", 1b-.
|
||||
|
||||
/*
|
||||
* For now, we always put in the McKinley E9 workaround. On CPUs that don't need it,
|
||||
@ -84,11 +84,11 @@ name:
|
||||
#define DO_MCKINLEY_E9_WORKAROUND
|
||||
|
||||
#ifdef DO_MCKINLEY_E9_WORKAROUND
|
||||
.section ".data.patch.mckinley_e9", "a"
|
||||
.section ".data..patch.mckinley_e9", "a"
|
||||
.previous
|
||||
/* workaround for Itanium 2 Errata 9: */
|
||||
# define FSYS_RETURN \
|
||||
.xdata4 ".data.patch.mckinley_e9", 1f-.; \
|
||||
.xdata4 ".data..patch.mckinley_e9", 1f-.; \
|
||||
1:{ .mib; \
|
||||
nop.m 0; \
|
||||
mov r16=ar.pfs; \
|
||||
@ -107,11 +107,11 @@ name:
|
||||
* If physical stack register size is different from DEF_NUM_STACK_REG,
|
||||
* dynamically patch the kernel for correct size.
|
||||
*/
|
||||
.section ".data.patch.phys_stack_reg", "a"
|
||||
.section ".data..patch.phys_stack_reg", "a"
|
||||
.previous
|
||||
#define LOAD_PHYS_STACK_REG_SIZE(reg) \
|
||||
[1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \
|
||||
.xdata4 ".data.patch.phys_stack_reg", 1b-.
|
||||
.xdata4 ".data..patch.phys_stack_reg", 1b-.
|
||||
|
||||
/*
|
||||
* Up until early 2004, use of .align within a function caused bad unwind info.
|
||||
|
||||
@ -24,6 +24,6 @@
|
||||
# define SMP_CACHE_BYTES (1 << 3)
|
||||
#endif
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#endif /* _ASM_IA64_CACHE_H */
|
||||
|
||||
@ -31,7 +31,7 @@ extern void *per_cpu_init(void);
|
||||
|
||||
#endif /* SMP */
|
||||
|
||||
#define PER_CPU_BASE_SECTION ".data.percpu"
|
||||
#define PER_CPU_BASE_SECTION ".data..percpu"
|
||||
|
||||
/*
|
||||
* Be extremely careful when taking the address of this variable! Due to virtual
|
||||
|
||||
@ -21,7 +21,7 @@ GATECFLAGS_gate-syms.o = -r
|
||||
$(obj)/gate-syms.o: $(obj)/gate.lds $(obj)/gate.o FORCE
|
||||
$(call if_changed,gate)
|
||||
|
||||
# gate-data.o contains the gate DSO image as data in section .data.gate.
|
||||
# gate-data.o contains the gate DSO image as data in section .data..gate.
|
||||
# We must build gate.so before we can assemble it.
|
||||
# Note: kbuild does not track this dependency due to usage of .incbin
|
||||
$(obj)/gate-data.o: $(obj)/gate.so
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
.section .data.gate, "aw"
|
||||
.section .data..gate, "aw"
|
||||
|
||||
.incbin "arch/ia64/kernel/gate.so"
|
||||
|
||||
@ -21,18 +21,18 @@
|
||||
* to targets outside the shared object) and to avoid multi-phase kernel builds, we
|
||||
* simply create minimalistic "patch lists" in special ELF sections.
|
||||
*/
|
||||
.section ".data.patch.fsyscall_table", "a"
|
||||
.section ".data..patch.fsyscall_table", "a"
|
||||
.previous
|
||||
#define LOAD_FSYSCALL_TABLE(reg) \
|
||||
[1:] movl reg=0; \
|
||||
.xdata4 ".data.patch.fsyscall_table", 1b-.
|
||||
.xdata4 ".data..patch.fsyscall_table", 1b-.
|
||||
|
||||
.section ".data.patch.brl_fsys_bubble_down", "a"
|
||||
.section ".data..patch.brl_fsys_bubble_down", "a"
|
||||
.previous
|
||||
#define BRL_COND_FSYS_BUBBLE_DOWN(pr) \
|
||||
[1:](pr)brl.cond.sptk 0; \
|
||||
;; \
|
||||
.xdata4 ".data.patch.brl_fsys_bubble_down", 1b-.
|
||||
.xdata4 ".data..patch.brl_fsys_bubble_down", 1b-.
|
||||
|
||||
GLOBAL_ENTRY(__kernel_syscall_via_break)
|
||||
.prologue
|
||||
|
||||
@ -33,21 +33,21 @@ SECTIONS
|
||||
*/
|
||||
. = GATE_ADDR + 0x600;
|
||||
|
||||
.data.patch : {
|
||||
.data..patch : {
|
||||
__paravirt_start_gate_mckinley_e9_patchlist = .;
|
||||
*(.data.patch.mckinley_e9)
|
||||
*(.data..patch.mckinley_e9)
|
||||
__paravirt_end_gate_mckinley_e9_patchlist = .;
|
||||
|
||||
__paravirt_start_gate_vtop_patchlist = .;
|
||||
*(.data.patch.vtop)
|
||||
*(.data..patch.vtop)
|
||||
__paravirt_end_gate_vtop_patchlist = .;
|
||||
|
||||
__paravirt_start_gate_fsyscall_patchlist = .;
|
||||
*(.data.patch.fsyscall_table)
|
||||
*(.data..patch.fsyscall_table)
|
||||
__paravirt_end_gate_fsyscall_patchlist = .;
|
||||
|
||||
__paravirt_start_gate_brl_fsys_bubble_down_patchlist = .;
|
||||
*(.data.patch.brl_fsys_bubble_down)
|
||||
*(.data..patch.brl_fsys_bubble_down)
|
||||
__paravirt_end_gate_brl_fsys_bubble_down_patchlist = .;
|
||||
} :readable
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@ static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
|
||||
* Initial task structure.
|
||||
*
|
||||
* We need to make sure that this is properly aligned due to the way process stacks are
|
||||
* handled. This is done by having a special ".data.init_task" section...
|
||||
* handled. This is done by having a special ".data..init_task" section...
|
||||
*/
|
||||
#define init_thread_info init_task_mem.s.thread_info
|
||||
|
||||
|
||||
@ -82,7 +82,7 @@
|
||||
mov r19=n;; /* prepare to save predicates */ \
|
||||
br.sptk.many dispatch_to_fault_handler
|
||||
|
||||
.section .text.ivt,"ax"
|
||||
.section .text..ivt,"ax"
|
||||
|
||||
.align 32768 // align on 32KB boundary
|
||||
.global ia64_ivt
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
#define ACCOUNT_SYS_ENTER
|
||||
#endif
|
||||
|
||||
.section ".data.patch.rse", "a"
|
||||
.section ".data..patch.rse", "a"
|
||||
.previous
|
||||
|
||||
/*
|
||||
@ -215,7 +215,7 @@
|
||||
(pUStk) extr.u r17=r18,3,6; \
|
||||
(pUStk) sub r16=r18,r22; \
|
||||
[1:](pKStk) br.cond.sptk.many 1f; \
|
||||
.xdata4 ".data.patch.rse",1b-. \
|
||||
.xdata4 ".data..patch.rse",1b-. \
|
||||
;; \
|
||||
cmp.ge p6,p7 = 33,r17; \
|
||||
;; \
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
#include "entry.h"
|
||||
|
||||
#define DATA8(sym, init_value) \
|
||||
.pushsection .data.read_mostly ; \
|
||||
.pushsection .data..read_mostly ; \
|
||||
.align 8 ; \
|
||||
.global sym ; \
|
||||
sym: ; \
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
#define IVT_TEXT \
|
||||
VMLINUX_SYMBOL(__start_ivt_text) = .; \
|
||||
*(.text.ivt) \
|
||||
*(.text..ivt) \
|
||||
VMLINUX_SYMBOL(__end_ivt_text) = .;
|
||||
|
||||
OUTPUT_FORMAT("elf64-ia64-little")
|
||||
@ -54,8 +54,8 @@ SECTIONS
|
||||
.text2 : AT(ADDR(.text2) - LOAD_OFFSET)
|
||||
{ *(.text2) }
|
||||
#ifdef CONFIG_SMP
|
||||
.text.lock : AT(ADDR(.text.lock) - LOAD_OFFSET)
|
||||
{ *(.text.lock) }
|
||||
.text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET)
|
||||
{ *(.text..lock) }
|
||||
#endif
|
||||
_etext = .;
|
||||
|
||||
@ -75,10 +75,10 @@ SECTIONS
|
||||
__stop___mca_table = .;
|
||||
}
|
||||
|
||||
.data.patch.phys_stack_reg : AT(ADDR(.data.patch.phys_stack_reg) - LOAD_OFFSET)
|
||||
.data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET)
|
||||
{
|
||||
__start___phys_stack_reg_patchlist = .;
|
||||
*(.data.patch.phys_stack_reg)
|
||||
*(.data..patch.phys_stack_reg)
|
||||
__end___phys_stack_reg_patchlist = .;
|
||||
}
|
||||
|
||||
@ -110,24 +110,24 @@ SECTIONS
|
||||
INIT_TEXT_SECTION(PAGE_SIZE)
|
||||
INIT_DATA_SECTION(16)
|
||||
|
||||
.data.patch.vtop : AT(ADDR(.data.patch.vtop) - LOAD_OFFSET)
|
||||
.data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET)
|
||||
{
|
||||
__start___vtop_patchlist = .;
|
||||
*(.data.patch.vtop)
|
||||
*(.data..patch.vtop)
|
||||
__end___vtop_patchlist = .;
|
||||
}
|
||||
|
||||
.data.patch.rse : AT(ADDR(.data.patch.rse) - LOAD_OFFSET)
|
||||
.data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET)
|
||||
{
|
||||
__start___rse_patchlist = .;
|
||||
*(.data.patch.rse)
|
||||
*(.data..patch.rse)
|
||||
__end___rse_patchlist = .;
|
||||
}
|
||||
|
||||
.data.patch.mckinley_e9 : AT(ADDR(.data.patch.mckinley_e9) - LOAD_OFFSET)
|
||||
.data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET)
|
||||
{
|
||||
__start___mckinley_e9_bundles = .;
|
||||
*(.data.patch.mckinley_e9)
|
||||
*(.data..patch.mckinley_e9)
|
||||
__end___mckinley_e9_bundles = .;
|
||||
}
|
||||
|
||||
@ -175,17 +175,17 @@ SECTIONS
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
__init_end = .;
|
||||
|
||||
.data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET)
|
||||
.data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET)
|
||||
{
|
||||
PAGE_ALIGNED_DATA(PAGE_SIZE)
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
__start_gate_section = .;
|
||||
*(.data.gate)
|
||||
*(.data..gate)
|
||||
__stop_gate_section = .;
|
||||
#ifdef CONFIG_XEN
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
__xen_start_gate_section = .;
|
||||
*(.data.gate.xen)
|
||||
*(.data..gate.xen)
|
||||
__xen_stop_gate_section = .;
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -104,7 +104,7 @@ GLOBAL_ENTRY(kvm_vmm_panic)
|
||||
br.call.sptk.many b6=vmm_panic_handler;
|
||||
END(kvm_vmm_panic)
|
||||
|
||||
.section .text.ivt,"ax"
|
||||
.section .text..ivt,"ax"
|
||||
|
||||
.align 32768 // align on 32KB boundary
|
||||
.global kvm_ia64_ivt
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
#!/usr/bin/env python
|
||||
#!/usr/bin/python
|
||||
#
|
||||
# Usage: unwcheck.py FILE
|
||||
#
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
.section .data.gate.xen, "aw"
|
||||
.section .data..gate.xen, "aw"
|
||||
|
||||
.incbin "arch/ia64/xen/gate.so"
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <xen/interface/elfnote.h>
|
||||
|
||||
.section .data.read_mostly
|
||||
.section .data..read_mostly
|
||||
.align 8
|
||||
.global xen_domain_type
|
||||
xen_domain_type:
|
||||
|
||||
@ -57,7 +57,7 @@ SECTIONS {
|
||||
.romvec : {
|
||||
__rom_start = . ;
|
||||
_romvec = .;
|
||||
*(.data.initvect)
|
||||
*(.data..initvect)
|
||||
} > romvec
|
||||
#endif
|
||||
|
||||
@ -68,7 +68,7 @@ SECTIONS {
|
||||
TEXT_TEXT
|
||||
SCHED_TEXT
|
||||
LOCK_TEXT
|
||||
*(.text.lock)
|
||||
*(.text..lock)
|
||||
|
||||
. = ALIGN(16); /* Exception table */
|
||||
__start___ex_table = .;
|
||||
|
||||
@ -280,7 +280,7 @@ _dprbase:
|
||||
* and then overwritten as needed.
|
||||
*/
|
||||
|
||||
.section ".data.initvect","awx"
|
||||
.section ".data..initvect","awx"
|
||||
.long RAMEND /* Reset: Initial Stack Pointer - 0. */
|
||||
.long _start /* Reset: Initial Program Counter - 1. */
|
||||
.long buserr /* Bus Error - 2. */
|
||||
|
||||
@ -291,7 +291,7 @@ _dprbase:
|
||||
* and then overwritten as needed.
|
||||
*/
|
||||
|
||||
.section ".data.initvect","awx"
|
||||
.section ".data..initvect","awx"
|
||||
.long RAMEND /* Reset: Initial Stack Pointer - 0. */
|
||||
.long _start /* Reset: Initial Program Counter - 1. */
|
||||
.long buserr /* Bus Error - 2. */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#include <asm/lasat/head.h>
|
||||
|
||||
.text
|
||||
.section .text.start, "ax"
|
||||
.section .text..start, "ax"
|
||||
.set noreorder
|
||||
.set mips3
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@ SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
*(.text.start)
|
||||
*(.text..start)
|
||||
}
|
||||
|
||||
/* Data in ROM */
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
|
||||
#define SMP_CACHE_BYTES L1_CACHE_BYTES
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
void parisc_cache_init(void); /* initializes cache-flushing */
|
||||
void disable_sr_hashing_asm(int); /* low level support for above */
|
||||
|
||||
@ -174,7 +174,7 @@ static inline void set_eiem(unsigned long val)
|
||||
})
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
|
||||
# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
|
||||
#endif
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
||||
@ -345,7 +345,7 @@ smp_slave_stext:
|
||||
ENDPROC(stext)
|
||||
|
||||
#ifndef CONFIG_64BIT
|
||||
.section .data.read_mostly
|
||||
.section .data..read_mostly
|
||||
|
||||
.align 4
|
||||
.export $global$,data
|
||||
|
||||
@ -53,11 +53,11 @@ union thread_union init_thread_union __init_task_data
|
||||
* guarantee that global objects will be laid out in memory in the same order
|
||||
* as the order of declaration, so put these in different sections and use
|
||||
* the linker script to order them. */
|
||||
pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data.vm0.pmd"), aligned(PAGE_SIZE)));
|
||||
pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data..vm0.pmd"), aligned(PAGE_SIZE)));
|
||||
#endif
|
||||
|
||||
pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data.vm0.pgd"), aligned(PAGE_SIZE)));
|
||||
pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data.vm0.pte"), aligned(PAGE_SIZE)));
|
||||
pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data..vm0.pgd"), aligned(PAGE_SIZE)));
|
||||
pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pte"), aligned(PAGE_SIZE)));
|
||||
|
||||
/*
|
||||
* Initial task structure.
|
||||
|
||||
@ -94,8 +94,8 @@ SECTIONS
|
||||
|
||||
/* PA-RISC locks requires 16-byte alignment */
|
||||
. = ALIGN(16);
|
||||
.data.lock_aligned : {
|
||||
*(.data.lock_aligned)
|
||||
.data..lock_aligned : {
|
||||
*(.data..lock_aligned)
|
||||
}
|
||||
|
||||
/* End of data section */
|
||||
@ -105,10 +105,10 @@ SECTIONS
|
||||
__bss_start = .;
|
||||
/* page table entries need to be PAGE_SIZE aligned */
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
.data.vmpages : {
|
||||
*(.data.vm0.pmd)
|
||||
*(.data.vm0.pgd)
|
||||
*(.data.vm0.pte)
|
||||
.data..vmpages : {
|
||||
*(.data..vm0.pmd)
|
||||
*(.data..vm0.pgd)
|
||||
*(.data..vm0.pte)
|
||||
}
|
||||
.bss : {
|
||||
*(.bss)
|
||||
|
||||
@ -351,7 +351,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
|
||||
|
||||
config KEXEC
|
||||
bool "kexec system call (EXPERIMENTAL)"
|
||||
depends on PPC_BOOK3S && EXPERIMENTAL
|
||||
depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
||||
@ -112,6 +112,11 @@ KBUILD_CFLAGS += $(call cc-option,-mspe=no)
|
||||
# kernel considerably.
|
||||
KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time)
|
||||
|
||||
# FIXME: the module load should be taught about the additional relocs
|
||||
# generated by this.
|
||||
# revert to pre-gcc-4.4 behaviour of .eh_frame
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
|
||||
|
||||
# Never use string load/store instructions as they are
|
||||
# often slow when they are implemented at all
|
||||
KBUILD_CFLAGS += -mno-string
|
||||
|
||||
@ -519,7 +519,7 @@ void ibm440ep_fixup_clocks(unsigned int sys_clk,
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
|
||||
@ -532,7 +532,7 @@ void ibm440gx_fixup_clocks(unsigned int sys_clk,
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
|
||||
}
|
||||
@ -543,10 +543,10 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk,
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
|
||||
|
||||
447
arch/powerpc/boot/dts/icon.dts
Normal file
447
arch/powerpc/boot/dts/icon.dts
Normal file
@ -0,0 +1,447 @@
|
||||
/*
|
||||
* Device Tree Source for Mosaix Technologies, Inc. ICON board
|
||||
*
|
||||
* Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "mosaixtech,icon";
|
||||
compatible = "mosaixtech,icon";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440SPe";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
reset-type = <2>; /* Use chip-reset */
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440spe";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440spe";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
MQ0: mq {
|
||||
compatible = "ibm,mq-440spe";
|
||||
dcr-reg = <0x040 0x020>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* addr-child addr-parent size */
|
||||
ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
|
||||
0x4 0x00200000 0x4 0x00200000 0x00000400
|
||||
0x4 0xe0000000 0x4 0xe0000000 0x20000000
|
||||
0xc 0x00000000 0xc 0x00000000 0x20000000
|
||||
0xd 0x00000000 0xd 0x00000000 0x80000000
|
||||
0xd 0x80000000 0xd 0x80000000 0x80000000
|
||||
0xe 0x00000000 0xe 0x00000000 0x80000000
|
||||
0xe 0x80000000 0xe 0x80000000 0x80000000
|
||||
0xf 0x00000000 0xf 0x00000000 0x80000000
|
||||
0xf 0x80000000 0xf 0x80000000 0x80000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
|
||||
/*RXEOB*/ 0x1 &UIC1 0x7 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x1 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x2 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x3 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x01000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x00400000 0x00b60000>;
|
||||
};
|
||||
partition@f60000 {
|
||||
label = "env";
|
||||
reg = <0x00f60000 0x00040000>;
|
||||
};
|
||||
partition@fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x00fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
SysACE_CompactFlash: sysace@1,0 {
|
||||
compatible = "xlnx,sysace";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <24 0x4>;
|
||||
reg = <0x00000001 0x00000000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@f0000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xf0000200 0x00000008>;
|
||||
virtual-reg = <0xa0000200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@f0000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xf0000300 0x00000008>;
|
||||
virtual-reg = <0xa0000300>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
|
||||
UART2: serial@f0000600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xf0000600 0x00000008>;
|
||||
virtual-reg = <0xa0000600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x5 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@f0000400 {
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xf0000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@f0000500 {
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xf0000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
EMAC0: ethernet@f0000800 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440spe", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0xf0000800 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "gmii";
|
||||
phy-map = <0x00000000>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 4GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 4GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
/* This drives busses 0x10 to 0x1f */
|
||||
bus-range = <0x10 0x1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 4GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
/* This drives busses 0x20 to 0x2f */
|
||||
bus-range = <0x20 0x2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
I2O: i2o@400100000 {
|
||||
compatible = "ibm,i2o-440spe";
|
||||
reg = <0x00000004 0x00100000 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
};
|
||||
|
||||
DMA0: dma0@400100100 {
|
||||
compatible = "ibm,dma-440spe";
|
||||
cell-index = <0>;
|
||||
reg = <0x00000004 0x00100100 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
interrupt-parent = <&DMA0>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x14 4
|
||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
DMA1: dma1@400100200 {
|
||||
compatible = "ibm,dma-440spe";
|
||||
cell-index = <1>;
|
||||
reg = <0x00000004 0x00100200 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
interrupt-parent = <&DMA1>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x16 4
|
||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
xor-accel@400200000 {
|
||||
compatible = "amcc,xor-accelerator";
|
||||
reg = <0x00000004 0x00200000 0x400>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1f 4>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@f0000200";
|
||||
};
|
||||
};
|
||||
@ -44,6 +44,7 @@
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
reset-type = <2>; /* Use chip-reset */
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -20,10 +20,8 @@
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
/*
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
*/
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
@ -254,7 +252,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 3/4 are currently broken
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -310,7 +307,6 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
|
||||
@ -215,6 +215,18 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x80>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
@ -243,8 +255,7 @@
|
||||
protected-sources = <
|
||||
31 32 33 37 38 39 /* enet2 enet3 */
|
||||
76 77 78 79 26 42 /* dma2 pci2 serial*/
|
||||
0xe0 0xe1 0xe2 0xe3 /* msi */
|
||||
0xe4 0xe5 0xe6 0xe7
|
||||
0xe4 0xe5 0xe6 0xe7 /* msi */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -154,12 +154,8 @@
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
msi-available-ranges = <0x80 0x80>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
@ -190,6 +186,7 @@
|
||||
0x1 0x2 0x3 0x4 /* pci slot */
|
||||
0x9 0xa 0xb 0xc /* usb */
|
||||
0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
|
||||
0xe0 0xe1 0xe2 0xe3 /* msi */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
698
arch/powerpc/boot/dts/p1021mds.dts
Normal file
698
arch/powerpc/boot/dts/p1021mds.dts
Normal file
@ -0,0 +1,698 @@
|
||||
/*
|
||||
* P1021 MDS Device Tree Source
|
||||
*
|
||||
* Copyright 2010 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "fsl,P1021";
|
||||
compatible = "fsl,P1021MDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1021@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1021@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
/* NAND Flash, BCSR, PMC0/1*/
|
||||
ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
|
||||
0x1 0x0 0x0 0xf8000000 0x00008000
|
||||
0x2 0x0 0x0 0xf8010000 0x00020000
|
||||
0x3 0x0 0x0 0xf8020000 0x00020000>;
|
||||
|
||||
nand@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1021-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x0 0x0 0x40000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND (RO) U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND (RO) DTB Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00400000>;
|
||||
label = "NAND (RO) Linux Kernel Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
/* 5MB for Compressed Root file System Image */
|
||||
reg = <0x00600000 0x00500000>;
|
||||
label = "NAND (RO) Compressed RFS Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b00000 {
|
||||
/* 6MB for JFFS2 based Root file System */
|
||||
reg = <0x00a00000 0x00600000>;
|
||||
label = "NAND (RW) JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@1100000 {
|
||||
/* 14MB for JFFS2 based Root file System */
|
||||
reg = <0x01100000 0x00e00000>;
|
||||
label = "NAND (RW) Writable User area";
|
||||
};
|
||||
|
||||
partition@1f00000 {
|
||||
/* 1MB for microcode */
|
||||
reg = <0x01f00000 0x00100000>;
|
||||
label = "NAND (RO) QE Ucode";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1021mds-bcsr";
|
||||
reg = <1 0 0x8000>;
|
||||
ranges = <0 1 0 0x8000>;
|
||||
};
|
||||
|
||||
pib@2,0 {
|
||||
compatible = "fsl,p1021mds-pib";
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
|
||||
pib@3,0 {
|
||||
compatible = "fsl,p1021mds-pib";
|
||||
reg = <3 0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1021-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1021-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1021-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
espi,num-ss-bits = <4>;
|
||||
mode = "cpu";
|
||||
|
||||
fsl_m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,espi-flash";
|
||||
reg = <0>;
|
||||
linux,modalias = "fsl_m25p80";
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
label = "u-boot-spi";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@kernel {
|
||||
label = "kernel-spi";
|
||||
reg = <0x00100000 0x00500000>;
|
||||
read-only;
|
||||
};
|
||||
partition@dtb {
|
||||
label = "dtb-spi";
|
||||
reg = <0x00600000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@fs {
|
||||
label = "file system-spi";
|
||||
reg = <0x00700000 0x00900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1021-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <1 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@B0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
queue-group@0{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
};
|
||||
queue-group@1{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB4000 0x1000>;
|
||||
interrupts = <17 2 18 2 24 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@B1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy4>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
queue-group@0{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB1000 0x1000>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
};
|
||||
queue-group@1{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB5000 0x1000>;
|
||||
interrupts = <51 2 52 2 67 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@B2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
queue-group@0{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB2000 0x1000>;
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
};
|
||||
queue-group@1{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB6000 0x1000>;
|
||||
interrupts = <25 2 26 2 27 2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p1021-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.3", "fsl,sec3.1",
|
||||
"fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x97c>;
|
||||
fsl,descriptor-types-mask = <0x3a30abf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1021-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1021-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0100 0x60>;
|
||||
ranges = <0x0 0xe0100 0x60>;
|
||||
device_type = "par_io";
|
||||
num-ports = <3>;
|
||||
pio1: ucc_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
|
||||
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
|
||||
0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
|
||||
0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9
|
||||
*/
|
||||
0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
|
||||
0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
|
||||
0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
|
||||
0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
|
||||
0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
|
||||
0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
|
||||
0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
|
||||
0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
|
||||
0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
|
||||
0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
|
||||
0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
|
||||
0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
|
||||
0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
|
||||
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
|
||||
};
|
||||
|
||||
pio2: ucc_pin@02 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
|
||||
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
|
||||
0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
|
||||
0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
|
||||
0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
|
||||
0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
|
||||
0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
|
||||
0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
|
||||
0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
|
||||
0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 4 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 0 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
qe@ffe80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0x0 0xffe80000 0x40000>;
|
||||
reg = <0 0xffe80000 0 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <63 2 60 2>; //high:47 low:44
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
enet3: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "clk12";
|
||||
tx-clock-name = "clk9";
|
||||
pio-handle = <&pio1>;
|
||||
phy-handle = <&qe_phy0>;
|
||||
phy-connection-type = "mii";
|
||||
};
|
||||
|
||||
mdio@2120 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2120 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
qe_phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy1: ethernet-phy@03 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet4: ucc@2400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk13";
|
||||
pio-handle = <&pio2>;
|
||||
phy-handle = <&qe_phy1>;
|
||||
phy-connection-type = "rmii";
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -234,10 +234,132 @@
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x10 0x1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x20 0x2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@d40000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10002000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x140 0x020>;
|
||||
sdr-base = <0x370>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x30 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600200";
|
||||
};
|
||||
|
||||
1451
arch/powerpc/configs/44x/icon_defconfig
Normal file
1451
arch/powerpc/configs/44x/icon_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -42,7 +42,7 @@ extern struct ppc64_caches ppc64_caches;
|
||||
#endif /* __powerpc64__ && ! __ASSEMBLY__ */
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@ -70,6 +70,7 @@ struct pt_regs;
|
||||
extern int machine_check_generic(struct pt_regs *regs);
|
||||
extern int machine_check_4xx(struct pt_regs *regs);
|
||||
extern int machine_check_440A(struct pt_regs *regs);
|
||||
extern int machine_check_e500mc(struct pt_regs *regs);
|
||||
extern int machine_check_e500(struct pt_regs *regs);
|
||||
extern int machine_check_e200(struct pt_regs *regs);
|
||||
extern int machine_check_47x(struct pt_regs *regs);
|
||||
|
||||
@ -2,6 +2,18 @@
|
||||
#define _ASM_POWERPC_KEXEC_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifdef CONFIG_FSL_BOOKE
|
||||
|
||||
/*
|
||||
* On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
|
||||
* and therefore we can only deal with memory within this range
|
||||
*/
|
||||
#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
|
||||
#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
|
||||
#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Maximum page that is mapped directly into kernel memory.
|
||||
* XXX: Since we copy virt we can use any page we allocate
|
||||
@ -21,6 +33,7 @@
|
||||
/* TASK_SIZE, probably left over from use_mm ?? */
|
||||
#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define KEXEC_CONTROL_PAGE_SIZE 4096
|
||||
|
||||
|
||||
@ -162,14 +162,6 @@ do { \
|
||||
|
||||
#endif /* !CONFIG_HUGETLB_PAGE */
|
||||
|
||||
#ifdef MODULE
|
||||
#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
|
||||
#else
|
||||
#define __page_aligned \
|
||||
__attribute__((__aligned__(PAGE_SIZE), \
|
||||
__section__(".data.page_aligned")))
|
||||
#endif
|
||||
|
||||
#define VM_DATA_DEFAULT_FLAGS \
|
||||
(test_thread_flag(TIF_32BIT) ? \
|
||||
VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
|
||||
|
||||
@ -4,6 +4,12 @@
|
||||
* are not true Book E PowerPCs, they borrowed a number of features
|
||||
* before Book E was finalized, and are included here as well. Unfortunatly,
|
||||
* they sometimes used different locations than true Book E CPUs did.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_POWERPC_REG_BOOKE_H__
|
||||
@ -88,6 +94,7 @@
|
||||
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
|
||||
#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
|
||||
#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
|
||||
#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
|
||||
#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
|
||||
#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
|
||||
#define SPRN_MCSR 0x23C /* Machine Check Status Register */
|
||||
@ -196,8 +203,11 @@
|
||||
#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
|
||||
|
||||
#ifdef CONFIG_E500
|
||||
/* All e500 */
|
||||
#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
|
||||
#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
|
||||
|
||||
/* e500v1/v2 */
|
||||
#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
|
||||
#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
|
||||
#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
|
||||
@ -209,12 +219,20 @@
|
||||
#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
|
||||
#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
|
||||
|
||||
/* e500 parts may set unused bits in MCSR; mask these off */
|
||||
#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
|
||||
MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
|
||||
MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
|
||||
MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
|
||||
/* e500mc */
|
||||
#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
|
||||
#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */
|
||||
#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
|
||||
#define MCSR_MAV 0x00080000UL /* MCAR address valid */
|
||||
#define MCSR_MEA 0x00040000UL /* MCAR is effective address */
|
||||
#define MCSR_IF 0x00010000UL /* Instruction Fetch */
|
||||
#define MCSR_LD 0x00008000UL /* Load */
|
||||
#define MCSR_ST 0x00004000UL /* Store */
|
||||
#define MCSR_LDG 0x00002000UL /* Guarded Load */
|
||||
#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
|
||||
#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_E200
|
||||
#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
|
||||
#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
|
||||
@ -225,11 +243,6 @@
|
||||
#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
|
||||
#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
|
||||
store or cache line push */
|
||||
|
||||
/* e200 parts may set unused bits in MCSR; mask these off */
|
||||
#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
|
||||
MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
|
||||
MCSR_BUS_WRERR)
|
||||
#endif
|
||||
|
||||
/* Bit definitions for the DBSR. */
|
||||
|
||||
@ -57,8 +57,12 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
|
||||
obj-$(CONFIG_E500) += idle_e500.o
|
||||
obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
|
||||
obj-$(CONFIG_TAU) += tau_6xx.o
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
|
||||
swsusp_$(CONFIG_WORD_SIZE).o
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o
|
||||
ifeq ($(CONFIG_FSL_BOOKE),y)
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp_booke.o
|
||||
else
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp_$(CONFIG_WORD_SIZE).o
|
||||
endif
|
||||
obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
|
||||
obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
|
||||
obj-$(CONFIG_44x) += cpu_setup_44x.o
|
||||
|
||||
@ -1840,7 +1840,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.oprofile_cpu_type = "ppc/e500mc",
|
||||
.oprofile_type = PPC_OPROFILE_FSL_EMB,
|
||||
.cpu_setup = __setup_cpu_e500mc,
|
||||
.machine_check = machine_check_e500,
|
||||
.machine_check = machine_check_e500mc,
|
||||
.platform = "ppce500mc",
|
||||
},
|
||||
{ /* default match */
|
||||
|
||||
@ -163,6 +163,7 @@ static void crash_kexec_prepare_cpus(int cpu)
|
||||
}
|
||||
|
||||
/* wait for all the CPUs to hit real mode but timeout if they don't come in */
|
||||
#ifdef CONFIG_PPC_STD_MMU_64
|
||||
static void crash_kexec_wait_realmode(int cpu)
|
||||
{
|
||||
unsigned int msecs;
|
||||
@ -187,6 +188,7 @@ static void crash_kexec_wait_realmode(int cpu)
|
||||
}
|
||||
mb();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This function will be called by secondary cpus or by kexec cpu
|
||||
@ -445,7 +447,9 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
|
||||
crash_kexec_prepare_cpus(crashing_cpu);
|
||||
cpu_set(crashing_cpu, cpus_in_crash);
|
||||
crash_kexec_stop_spus();
|
||||
#ifdef CONFIG_PPC_STD_MMU_64
|
||||
crash_kexec_wait_realmode(crashing_cpu);
|
||||
#endif
|
||||
if (ppc_md.kexec_cpu_down)
|
||||
ppc_md.kexec_cpu_down(1, 0);
|
||||
}
|
||||
|
||||
237
arch/powerpc/kernel/fsl_booke_entry_mapping.S
Normal file
237
arch/powerpc/kernel/fsl_booke_entry_mapping.S
Normal file
@ -0,0 +1,237 @@
|
||||
|
||||
/* 1. Find the index of the entry we're executing in */
|
||||
bl invstr /* Find our address */
|
||||
invstr: mflr r6 /* Make it accessible */
|
||||
mfmsr r7
|
||||
rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
|
||||
mfspr r7, SPRN_PID0
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
|
||||
mfspr r7,SPRN_MAS1
|
||||
andis. r7,r7,MAS1_VALID@h
|
||||
bne match_TLB
|
||||
|
||||
mfspr r7,SPRN_MMUCFG
|
||||
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
|
||||
cmpwi r7,3
|
||||
bne match_TLB /* skip if NPIDS != 3 */
|
||||
|
||||
mfspr r7,SPRN_PID1
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
|
||||
mfspr r7,SPRN_MAS1
|
||||
andis. r7,r7,MAS1_VALID@h
|
||||
bne match_TLB
|
||||
mfspr r7, SPRN_PID2
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* Fall through, we had to match */
|
||||
|
||||
match_TLB:
|
||||
mfspr r7,SPRN_MAS0
|
||||
rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
|
||||
|
||||
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
|
||||
oris r7,r7,MAS1_IPROT@h
|
||||
mtspr SPRN_MAS1,r7
|
||||
tlbwe
|
||||
|
||||
/* 2. Invalidate all entries except the entry we're executing in */
|
||||
mfspr r9,SPRN_TLB1CFG
|
||||
andi. r9,r9,0xfff
|
||||
li r6,0 /* Set Entry counter to 0 */
|
||||
1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r7,SPRN_MAS1
|
||||
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
|
||||
cmpw r3,r6
|
||||
beq skpinv /* Dont update the current execution TLB */
|
||||
mtspr SPRN_MAS1,r7
|
||||
tlbwe
|
||||
isync
|
||||
skpinv: addi r6,r6,1 /* Increment */
|
||||
cmpw r6,r9 /* Are we done? */
|
||||
bne 1b /* If not, repeat */
|
||||
|
||||
/* Invalidate TLB0 */
|
||||
li r6,0x04
|
||||
tlbivax 0,r6
|
||||
TLBSYNC
|
||||
/* Invalidate TLB1 */
|
||||
li r6,0x0c
|
||||
tlbivax 0,r6
|
||||
TLBSYNC
|
||||
|
||||
/* 3. Setup a temp mapping and jump to it */
|
||||
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
|
||||
addi r5, r5, 0x1
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
|
||||
/* grab and fixup the RPN */
|
||||
mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
|
||||
rlwinm r6,r6,25,27,31
|
||||
li r8,-1
|
||||
addi r6,r6,10
|
||||
slw r6,r8,r6 /* convert to mask */
|
||||
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r7
|
||||
|
||||
mfspr r8,SPRN_MAS3
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
mfspr r23,SPRN_MAS7
|
||||
#endif
|
||||
and r8,r6,r8
|
||||
subfic r9,r6,-4096
|
||||
and r9,r9,r7
|
||||
|
||||
or r25,r8,r9
|
||||
ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
|
||||
|
||||
/* Just modify the entry ID and EPN for the temp mapping */
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
|
||||
slwi r6,r6,12
|
||||
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
|
||||
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
|
||||
mtspr SPRN_MAS1,r6
|
||||
mfspr r6,SPRN_MAS2
|
||||
li r7,0 /* temp EPN = 0 */
|
||||
rlwimi r7,r6,0,20,31
|
||||
mtspr SPRN_MAS2,r7
|
||||
mtspr SPRN_MAS3,r8
|
||||
tlbwe
|
||||
|
||||
xori r6,r4,1
|
||||
slwi r6,r6,5 /* setup new context with other address space */
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r9
|
||||
rlwimi r7,r9,0,20,31
|
||||
addi r7,r7,(2f - 1b)
|
||||
mtspr SPRN_SRR0,r7
|
||||
mtspr SPRN_SRR1,r6
|
||||
rfi
|
||||
2:
|
||||
/* 4. Clear out PIDs & Search info */
|
||||
li r6,0
|
||||
mtspr SPRN_MAS6,r6
|
||||
mtspr SPRN_PID0,r6
|
||||
|
||||
mfspr r7,SPRN_MMUCFG
|
||||
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
|
||||
cmpwi r7,3
|
||||
bne 2f /* skip if NPIDS != 3 */
|
||||
|
||||
mtspr SPRN_PID1,r6
|
||||
mtspr SPRN_PID2,r6
|
||||
|
||||
/* 5. Invalidate mapping we started in */
|
||||
2:
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r6,SPRN_MAS1
|
||||
rlwinm r6,r6,0,2,0 /* clear IPROT */
|
||||
mtspr SPRN_MAS1,r6
|
||||
tlbwe
|
||||
/* Invalidate TLB1 */
|
||||
li r9,0x0c
|
||||
tlbivax 0,r9
|
||||
TLBSYNC
|
||||
|
||||
/* The mapping only needs to be cache-coherent on SMP */
|
||||
#ifdef CONFIG_SMP
|
||||
#define M_IF_SMP MAS2_M
|
||||
#else
|
||||
#define M_IF_SMP 0
|
||||
#endif
|
||||
|
||||
#if defined(ENTRY_MAPPING_BOOT_SETUP)
|
||||
|
||||
/* 6. Setup KERNELBASE mapping in TLB1[0] */
|
||||
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
|
||||
mtspr SPRN_MAS0,r6
|
||||
lis r6,(MAS1_VALID|MAS1_IPROT)@h
|
||||
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
|
||||
mtspr SPRN_MAS1,r6
|
||||
lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
|
||||
ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
|
||||
mtspr SPRN_MAS2,r6
|
||||
mtspr SPRN_MAS3,r8
|
||||
tlbwe
|
||||
|
||||
/* 7. Jump to KERNELBASE mapping */
|
||||
lis r6,(KERNELBASE & ~0xfff)@h
|
||||
ori r6,r6,(KERNELBASE & ~0xfff)@l
|
||||
|
||||
#elif defined(ENTRY_MAPPING_KEXEC_SETUP)
|
||||
/*
|
||||
* 6. Setup a 1:1 mapping in TLB1. Esel 0 is unsued, 1 or 2 contains the tmp
|
||||
* mapping so we start at 3. We setup 8 mappings, each 256MiB in size. This
|
||||
* will cover the first 2GiB of memory.
|
||||
*/
|
||||
|
||||
lis r10, (MAS1_VALID|MAS1_IPROT)@h
|
||||
ori r10,r10, (MAS1_TSIZE(BOOK3E_PAGESZ_256M))@l
|
||||
li r11, 0
|
||||
li r0, 8
|
||||
mtctr r0
|
||||
|
||||
next_tlb_setup:
|
||||
addi r0, r11, 3
|
||||
rlwinm r0, r0, 16, 4, 15 // Compute esel
|
||||
rlwinm r9, r11, 28, 0, 3 // Compute [ER]PN
|
||||
oris r0, r0, (MAS0_TLBSEL(1))@h
|
||||
mtspr SPRN_MAS0,r0
|
||||
mtspr SPRN_MAS1,r10
|
||||
mtspr SPRN_MAS2,r9
|
||||
ori r9, r9, (MAS3_SX|MAS3_SW|MAS3_SR)
|
||||
mtspr SPRN_MAS3,r9
|
||||
tlbwe
|
||||
addi r11, r11, 1
|
||||
bdnz+ next_tlb_setup
|
||||
|
||||
/* 7. Jump to our 1:1 mapping */
|
||||
li r6, 0
|
||||
|
||||
#else
|
||||
#error You need to specify the mapping or not use this at all.
|
||||
#endif
|
||||
|
||||
lis r7,MSR_KERNEL@h
|
||||
ori r7,r7,MSR_KERNEL@l
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r9
|
||||
rlwimi r6,r9,0,20,31
|
||||
addi r6,r6,(2f - 1b)
|
||||
add r6, r6, r25
|
||||
mtspr SPRN_SRR0,r6
|
||||
mtspr SPRN_SRR1,r7
|
||||
rfi /* start execution out of TLB1[0] entry */
|
||||
|
||||
/* 8. Clear out the temp mapping */
|
||||
2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r8,SPRN_MAS1
|
||||
rlwinm r8,r8,0,2,0 /* clear IPROT */
|
||||
mtspr SPRN_MAS1,r8
|
||||
tlbwe
|
||||
/* Invalidate TLB1 */
|
||||
li r9,0x0c
|
||||
tlbivax 0,r9
|
||||
TLBSYNC
|
||||
@ -94,204 +94,10 @@ _ENTRY(_start);
|
||||
*/
|
||||
|
||||
_ENTRY(__early_start)
|
||||
/* 1. Find the index of the entry we're executing in */
|
||||
bl invstr /* Find our address */
|
||||
invstr: mflr r6 /* Make it accessible */
|
||||
mfmsr r7
|
||||
rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
|
||||
mfspr r7, SPRN_PID0
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
|
||||
mfspr r7,SPRN_MAS1
|
||||
andis. r7,r7,MAS1_VALID@h
|
||||
bne match_TLB
|
||||
|
||||
mfspr r7,SPRN_MMUCFG
|
||||
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
|
||||
cmpwi r7,3
|
||||
bne match_TLB /* skip if NPIDS != 3 */
|
||||
|
||||
mfspr r7,SPRN_PID1
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
|
||||
mfspr r7,SPRN_MAS1
|
||||
andis. r7,r7,MAS1_VALID@h
|
||||
bne match_TLB
|
||||
mfspr r7, SPRN_PID2
|
||||
slwi r7,r7,16
|
||||
or r7,r7,r4
|
||||
mtspr SPRN_MAS6,r7
|
||||
tlbsx 0,r6 /* Fall through, we had to match */
|
||||
|
||||
match_TLB:
|
||||
mfspr r7,SPRN_MAS0
|
||||
rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
|
||||
|
||||
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
|
||||
oris r7,r7,MAS1_IPROT@h
|
||||
mtspr SPRN_MAS1,r7
|
||||
tlbwe
|
||||
|
||||
/* 2. Invalidate all entries except the entry we're executing in */
|
||||
mfspr r9,SPRN_TLB1CFG
|
||||
andi. r9,r9,0xfff
|
||||
li r6,0 /* Set Entry counter to 0 */
|
||||
1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r7,SPRN_MAS1
|
||||
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
|
||||
cmpw r3,r6
|
||||
beq skpinv /* Dont update the current execution TLB */
|
||||
mtspr SPRN_MAS1,r7
|
||||
tlbwe
|
||||
isync
|
||||
skpinv: addi r6,r6,1 /* Increment */
|
||||
cmpw r6,r9 /* Are we done? */
|
||||
bne 1b /* If not, repeat */
|
||||
|
||||
/* Invalidate TLB0 */
|
||||
li r6,0x04
|
||||
tlbivax 0,r6
|
||||
TLBSYNC
|
||||
/* Invalidate TLB1 */
|
||||
li r6,0x0c
|
||||
tlbivax 0,r6
|
||||
TLBSYNC
|
||||
|
||||
/* 3. Setup a temp mapping and jump to it */
|
||||
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
|
||||
addi r5, r5, 0x1
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
|
||||
/* grab and fixup the RPN */
|
||||
mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
|
||||
rlwinm r6,r6,25,27,31
|
||||
li r8,-1
|
||||
addi r6,r6,10
|
||||
slw r6,r8,r6 /* convert to mask */
|
||||
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r7
|
||||
|
||||
mfspr r8,SPRN_MAS3
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
mfspr r23,SPRN_MAS7
|
||||
#endif
|
||||
and r8,r6,r8
|
||||
subfic r9,r6,-4096
|
||||
and r9,r9,r7
|
||||
|
||||
or r25,r8,r9
|
||||
ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
|
||||
|
||||
/* Just modify the entry ID and EPN for the temp mapping */
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
|
||||
slwi r6,r6,12
|
||||
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
|
||||
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
|
||||
mtspr SPRN_MAS1,r6
|
||||
mfspr r6,SPRN_MAS2
|
||||
li r7,0 /* temp EPN = 0 */
|
||||
rlwimi r7,r6,0,20,31
|
||||
mtspr SPRN_MAS2,r7
|
||||
mtspr SPRN_MAS3,r8
|
||||
tlbwe
|
||||
|
||||
xori r6,r4,1
|
||||
slwi r6,r6,5 /* setup new context with other address space */
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r9
|
||||
rlwimi r7,r9,0,20,31
|
||||
addi r7,r7,(2f - 1b)
|
||||
mtspr SPRN_SRR0,r7
|
||||
mtspr SPRN_SRR1,r6
|
||||
rfi
|
||||
2:
|
||||
/* 4. Clear out PIDs & Search info */
|
||||
li r6,0
|
||||
mtspr SPRN_MAS6,r6
|
||||
mtspr SPRN_PID0,r6
|
||||
|
||||
mfspr r7,SPRN_MMUCFG
|
||||
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
|
||||
cmpwi r7,3
|
||||
bne 2f /* skip if NPIDS != 3 */
|
||||
|
||||
mtspr SPRN_PID1,r6
|
||||
mtspr SPRN_PID2,r6
|
||||
|
||||
/* 5. Invalidate mapping we started in */
|
||||
2:
|
||||
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r6,SPRN_MAS1
|
||||
rlwinm r6,r6,0,2,0 /* clear IPROT */
|
||||
mtspr SPRN_MAS1,r6
|
||||
tlbwe
|
||||
/* Invalidate TLB1 */
|
||||
li r9,0x0c
|
||||
tlbivax 0,r9
|
||||
TLBSYNC
|
||||
|
||||
/* The mapping only needs to be cache-coherent on SMP */
|
||||
#ifdef CONFIG_SMP
|
||||
#define M_IF_SMP MAS2_M
|
||||
#else
|
||||
#define M_IF_SMP 0
|
||||
#endif
|
||||
|
||||
/* 6. Setup KERNELBASE mapping in TLB1[0] */
|
||||
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
|
||||
mtspr SPRN_MAS0,r6
|
||||
lis r6,(MAS1_VALID|MAS1_IPROT)@h
|
||||
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
|
||||
mtspr SPRN_MAS1,r6
|
||||
lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
|
||||
ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
|
||||
mtspr SPRN_MAS2,r6
|
||||
mtspr SPRN_MAS3,r8
|
||||
tlbwe
|
||||
|
||||
/* 7. Jump to KERNELBASE mapping */
|
||||
lis r6,(KERNELBASE & ~0xfff)@h
|
||||
ori r6,r6,(KERNELBASE & ~0xfff)@l
|
||||
lis r7,MSR_KERNEL@h
|
||||
ori r7,r7,MSR_KERNEL@l
|
||||
bl 1f /* Find our address */
|
||||
1: mflr r9
|
||||
rlwimi r6,r9,0,20,31
|
||||
addi r6,r6,(2f - 1b)
|
||||
mtspr SPRN_SRR0,r6
|
||||
mtspr SPRN_SRR1,r7
|
||||
rfi /* start execution out of TLB1[0] entry */
|
||||
|
||||
/* 8. Clear out the temp mapping */
|
||||
2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
|
||||
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
|
||||
mtspr SPRN_MAS0,r7
|
||||
tlbre
|
||||
mfspr r8,SPRN_MAS1
|
||||
rlwinm r8,r8,0,2,0 /* clear IPROT */
|
||||
mtspr SPRN_MAS1,r8
|
||||
tlbwe
|
||||
/* Invalidate TLB1 */
|
||||
li r9,0x0c
|
||||
tlbivax 0,r9
|
||||
TLBSYNC
|
||||
#define ENTRY_MAPPING_BOOT_SETUP
|
||||
#include "fsl_booke_entry_mapping.S"
|
||||
#undef ENTRY_MAPPING_BOOT_SETUP
|
||||
|
||||
/* Establish the interrupt vector offsets */
|
||||
SET_IVOR(0, CriticalInput);
|
||||
|
||||
@ -711,6 +711,22 @@ relocate_new_kernel:
|
||||
/* r4 = reboot_code_buffer */
|
||||
/* r5 = start_address */
|
||||
|
||||
#ifdef CONFIG_FSL_BOOKE
|
||||
|
||||
mr r29, r3
|
||||
mr r30, r4
|
||||
mr r31, r5
|
||||
|
||||
#define ENTRY_MAPPING_KEXEC_SETUP
|
||||
#include "fsl_booke_entry_mapping.S"
|
||||
#undef ENTRY_MAPPING_KEXEC_SETUP
|
||||
|
||||
mr r3, r29
|
||||
mr r4, r30
|
||||
mr r5, r31
|
||||
|
||||
li r0, 0
|
||||
#else
|
||||
li r0, 0
|
||||
|
||||
/*
|
||||
@ -727,6 +743,7 @@ relocate_new_kernel:
|
||||
rfi
|
||||
|
||||
1:
|
||||
#endif
|
||||
/* from this point address translation is turned off */
|
||||
/* and interrupts are disabled */
|
||||
|
||||
|
||||
@ -101,7 +101,7 @@ EXPORT_SYMBOL(pci_dram_offset);
|
||||
EXPORT_SYMBOL(start_thread);
|
||||
EXPORT_SYMBOL(kernel_thread);
|
||||
|
||||
#ifndef CONFIG_BOOKE
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
EXPORT_SYMBOL_GPL(cvt_df);
|
||||
EXPORT_SYMBOL_GPL(cvt_fd);
|
||||
#endif
|
||||
|
||||
193
arch/powerpc/kernel/swsusp_booke.S
Normal file
193
arch/powerpc/kernel/swsusp_booke.S
Normal file
@ -0,0 +1,193 @@
|
||||
/*
|
||||
* Based on swsusp_32.S, modified for FSL BookE by
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
* Copyright (c) 2009-2010 MontaVista Software, LLC.
|
||||
*/
|
||||
|
||||
#include <linux/threads.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* Structure for storing CPU registers on the save area.
|
||||
*/
|
||||
#define SL_SP 0
|
||||
#define SL_PC 4
|
||||
#define SL_MSR 8
|
||||
#define SL_TCR 0xc
|
||||
#define SL_SPRG0 0x10
|
||||
#define SL_SPRG1 0x14
|
||||
#define SL_SPRG2 0x18
|
||||
#define SL_SPRG3 0x1c
|
||||
#define SL_SPRG4 0x20
|
||||
#define SL_SPRG5 0x24
|
||||
#define SL_SPRG6 0x28
|
||||
#define SL_SPRG7 0x2c
|
||||
#define SL_TBU 0x30
|
||||
#define SL_TBL 0x34
|
||||
#define SL_R2 0x38
|
||||
#define SL_CR 0x3c
|
||||
#define SL_LR 0x40
|
||||
#define SL_R12 0x44 /* r12 to r31 */
|
||||
#define SL_SIZE (SL_R12 + 80)
|
||||
|
||||
.section .data
|
||||
.align 5
|
||||
|
||||
_GLOBAL(swsusp_save_area)
|
||||
.space SL_SIZE
|
||||
|
||||
|
||||
.section .text
|
||||
.align 5
|
||||
|
||||
_GLOBAL(swsusp_arch_suspend)
|
||||
lis r11,swsusp_save_area@h
|
||||
ori r11,r11,swsusp_save_area@l
|
||||
|
||||
mflr r0
|
||||
stw r0,SL_LR(r11)
|
||||
mfcr r0
|
||||
stw r0,SL_CR(r11)
|
||||
stw r1,SL_SP(r11)
|
||||
stw r2,SL_R2(r11)
|
||||
stmw r12,SL_R12(r11)
|
||||
|
||||
/* Save MSR & TCR */
|
||||
mfmsr r4
|
||||
stw r4,SL_MSR(r11)
|
||||
mfspr r4,SPRN_TCR
|
||||
stw r4,SL_TCR(r11)
|
||||
|
||||
/* Get a stable timebase and save it */
|
||||
1: mfspr r4,SPRN_TBRU
|
||||
stw r4,SL_TBU(r11)
|
||||
mfspr r5,SPRN_TBRL
|
||||
stw r5,SL_TBL(r11)
|
||||
mfspr r3,SPRN_TBRU
|
||||
cmpw r3,r4
|
||||
bne 1b
|
||||
|
||||
/* Save SPRGs */
|
||||
mfsprg r4,0
|
||||
stw r4,SL_SPRG0(r11)
|
||||
mfsprg r4,1
|
||||
stw r4,SL_SPRG1(r11)
|
||||
mfsprg r4,2
|
||||
stw r4,SL_SPRG2(r11)
|
||||
mfsprg r4,3
|
||||
stw r4,SL_SPRG3(r11)
|
||||
mfsprg r4,4
|
||||
stw r4,SL_SPRG4(r11)
|
||||
mfsprg r4,5
|
||||
stw r4,SL_SPRG5(r11)
|
||||
mfsprg r4,6
|
||||
stw r4,SL_SPRG6(r11)
|
||||
mfsprg r4,7
|
||||
stw r4,SL_SPRG7(r11)
|
||||
|
||||
/* Call the low level suspend stuff (we should probably have made
|
||||
* a stackframe...
|
||||
*/
|
||||
bl swsusp_save
|
||||
|
||||
/* Restore LR from the save area */
|
||||
lis r11,swsusp_save_area@h
|
||||
ori r11,r11,swsusp_save_area@l
|
||||
lwz r0,SL_LR(r11)
|
||||
mtlr r0
|
||||
|
||||
blr
|
||||
|
||||
_GLOBAL(swsusp_arch_resume)
|
||||
sync
|
||||
|
||||
/* Load ptr the list of pages to copy in r3 */
|
||||
lis r11,(restore_pblist)@h
|
||||
ori r11,r11,restore_pblist@l
|
||||
lwz r3,0(r11)
|
||||
|
||||
/* Copy the pages. This is a very basic implementation, to
|
||||
* be replaced by something more cache efficient */
|
||||
1:
|
||||
li r0,256
|
||||
mtctr r0
|
||||
lwz r5,pbe_address(r3) /* source */
|
||||
lwz r6,pbe_orig_address(r3) /* destination */
|
||||
2:
|
||||
lwz r8,0(r5)
|
||||
lwz r9,4(r5)
|
||||
lwz r10,8(r5)
|
||||
lwz r11,12(r5)
|
||||
addi r5,r5,16
|
||||
stw r8,0(r6)
|
||||
stw r9,4(r6)
|
||||
stw r10,8(r6)
|
||||
stw r11,12(r6)
|
||||
addi r6,r6,16
|
||||
bdnz 2b
|
||||
lwz r3,pbe_next(r3)
|
||||
cmpwi 0,r3,0
|
||||
bne 1b
|
||||
|
||||
bl flush_dcache_L1
|
||||
bl flush_instruction_cache
|
||||
|
||||
lis r11,swsusp_save_area@h
|
||||
ori r11,r11,swsusp_save_area@l
|
||||
|
||||
lwz r4,SL_SPRG0(r11)
|
||||
mtsprg 0,r4
|
||||
lwz r4,SL_SPRG1(r11)
|
||||
mtsprg 1,r4
|
||||
lwz r4,SL_SPRG2(r11)
|
||||
mtsprg 2,r4
|
||||
lwz r4,SL_SPRG3(r11)
|
||||
mtsprg 3,r4
|
||||
lwz r4,SL_SPRG4(r11)
|
||||
mtsprg 4,r4
|
||||
lwz r4,SL_SPRG5(r11)
|
||||
mtsprg 5,r4
|
||||
lwz r4,SL_SPRG6(r11)
|
||||
mtsprg 6,r4
|
||||
lwz r4,SL_SPRG7(r11)
|
||||
mtsprg 7,r4
|
||||
|
||||
/* restore the MSR */
|
||||
lwz r3,SL_MSR(r11)
|
||||
mtmsr r3
|
||||
|
||||
/* Restore TB */
|
||||
li r3,0
|
||||
mtspr SPRN_TBWL,r3
|
||||
lwz r3,SL_TBU(r11)
|
||||
lwz r4,SL_TBL(r11)
|
||||
mtspr SPRN_TBWU,r3
|
||||
mtspr SPRN_TBWL,r4
|
||||
|
||||
/* Restore TCR and clear any pending bits in TSR. */
|
||||
lwz r4,SL_TCR(r11)
|
||||
mtspr SPRN_TCR,r4
|
||||
lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
|
||||
mtspr SPRN_TSR,r4
|
||||
|
||||
/* Kick decrementer */
|
||||
li r0,1
|
||||
mtdec r0
|
||||
|
||||
/* Restore the callee-saved registers and return */
|
||||
lwz r0,SL_CR(r11)
|
||||
mtcr r0
|
||||
lwz r2,SL_R2(r11)
|
||||
lmw r12,SL_R12(r11)
|
||||
lwz r1,SL_SP(r11)
|
||||
lwz r0,SL_LR(r11)
|
||||
mtlr r0
|
||||
|
||||
li r3,0
|
||||
blr
|
||||
@ -1,5 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
||||
* Copyright 2007-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
@ -305,7 +306,7 @@ static inline int check_io_access(struct pt_regs *regs)
|
||||
#ifndef CONFIG_FSL_BOOKE
|
||||
#define get_mc_reason(regs) ((regs)->dsisr)
|
||||
#else
|
||||
#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK)
|
||||
#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
|
||||
#endif
|
||||
#define REASON_FP ESR_FP
|
||||
#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
|
||||
@ -421,6 +422,91 @@ int machine_check_47x(struct pt_regs *regs)
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_E500)
|
||||
int machine_check_e500mc(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long mcsr = mfspr(SPRN_MCSR);
|
||||
unsigned long reason = mcsr;
|
||||
int recoverable = 1;
|
||||
|
||||
printk("Machine check in kernel mode.\n");
|
||||
printk("Caused by (from MCSR=%lx): ", reason);
|
||||
|
||||
if (reason & MCSR_MCP)
|
||||
printk("Machine Check Signal\n");
|
||||
|
||||
if (reason & MCSR_ICPERR) {
|
||||
printk("Instruction Cache Parity Error\n");
|
||||
|
||||
/*
|
||||
* This is recoverable by invalidating the i-cache.
|
||||
*/
|
||||
mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
|
||||
while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
|
||||
;
|
||||
|
||||
/*
|
||||
* This will generally be accompanied by an instruction
|
||||
* fetch error report -- only treat MCSR_IF as fatal
|
||||
* if it wasn't due to an L1 parity error.
|
||||
*/
|
||||
reason &= ~MCSR_IF;
|
||||
}
|
||||
|
||||
if (reason & MCSR_DCPERR_MC) {
|
||||
printk("Data Cache Parity Error\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_L2MMU_MHIT) {
|
||||
printk("Hit on multiple TLB entries\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_NMI)
|
||||
printk("Non-maskable interrupt\n");
|
||||
|
||||
if (reason & MCSR_IF) {
|
||||
printk("Instruction Fetch Error Report\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_LD) {
|
||||
printk("Load Error Report\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_ST) {
|
||||
printk("Store Error Report\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_LDG) {
|
||||
printk("Guarded Load Error Report\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_TLBSYNC)
|
||||
printk("Simultaneous tlbsync operations\n");
|
||||
|
||||
if (reason & MCSR_BSL2_ERR) {
|
||||
printk("Level 2 Cache Error\n");
|
||||
recoverable = 0;
|
||||
}
|
||||
|
||||
if (reason & MCSR_MAV) {
|
||||
u64 addr;
|
||||
|
||||
addr = mfspr(SPRN_MCAR);
|
||||
addr |= (u64)mfspr(SPRN_MCARU) << 32;
|
||||
|
||||
printk("Machine Check %s Address: %#llx\n",
|
||||
reason & MCSR_MEA ? "Effective" : "Physical", addr);
|
||||
}
|
||||
|
||||
mtspr(SPRN_MCSR, mcsr);
|
||||
return mfspr(SPRN_MCSR) == 0 && recoverable;
|
||||
}
|
||||
|
||||
int machine_check_e500(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long reason = get_mc_reason(regs);
|
||||
|
||||
@ -223,19 +223,17 @@ SECTIONS
|
||||
#endif
|
||||
|
||||
/* The initial task and kernel stack */
|
||||
.data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
|
||||
INIT_TASK_DATA(THREAD_SIZE)
|
||||
}
|
||||
INIT_TASK_DATA_SECTION(THREAD_SIZE)
|
||||
|
||||
.data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) {
|
||||
.data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) {
|
||||
PAGE_ALIGNED_DATA(PAGE_SIZE)
|
||||
}
|
||||
|
||||
.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
|
||||
.data..cacheline_aligned : AT(ADDR(.data..cacheline_aligned) - LOAD_OFFSET) {
|
||||
CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
|
||||
}
|
||||
|
||||
.data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) {
|
||||
.data..read_mostly : AT(ADDR(.data..read_mostly) - LOAD_OFFSET) {
|
||||
READ_MOSTLY_DATA(L1_CACHE_BYTES)
|
||||
}
|
||||
|
||||
|
||||
@ -171,6 +171,17 @@ config ISS4xx
|
||||
help
|
||||
This option enables support for the IBM ISS simulation environment
|
||||
|
||||
config ICON
|
||||
bool "Icon"
|
||||
depends on 44x
|
||||
default n
|
||||
select PPC44x_SIMPLE
|
||||
select 440SPe
|
||||
select PCI
|
||||
select PPC4xx_PCI_EXPRESS
|
||||
help
|
||||
This option enables support for the AMCC PPC440SPe evaluation board.
|
||||
|
||||
#config LUAN
|
||||
# bool "Luan"
|
||||
# depends on 44x
|
||||
|
||||
@ -61,7 +61,8 @@ static char *board[] __initdata = {
|
||||
"amcc,redwood",
|
||||
"amcc,sequoia",
|
||||
"amcc,taishan",
|
||||
"amcc,yosemite"
|
||||
"amcc,yosemite",
|
||||
"mosaixtech,icon"
|
||||
};
|
||||
|
||||
static int __init ppc44x_probe(void)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
|
||||
* Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
|
||||
*
|
||||
* Author: Andy Fleming <afleming@freescale.com>
|
||||
*
|
||||
@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
|
||||
* Setup the architecture
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
extern void __init mpc85xx_smp_init(void);
|
||||
#endif
|
||||
|
||||
static void __init mpc85xx_mds_setup_arch(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc85xx_smp_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,qe");
|
||||
if (!np) {
|
||||
@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void)
|
||||
BCSR_UCC_RGMII, BCSR_UCC_RTBI);
|
||||
}
|
||||
|
||||
} else if (machine_is(p1021_mds)) {
|
||||
#define BCSR11_ENET_MICRST (0x1 << 5)
|
||||
/* Reset Micrel PHY */
|
||||
clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
|
||||
setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
|
||||
}
|
||||
|
||||
iounmap(bcsr_regs);
|
||||
}
|
||||
|
||||
if (machine_is(p1021_mds)) {
|
||||
#define MPC85xx_PMUXCR_OFFSET 0x60
|
||||
#define MPC85xx_PMUXCR_QE0 0x00008000
|
||||
#define MPC85xx_PMUXCR_QE3 0x00001000
|
||||
#define MPC85xx_PMUXCR_QE9 0x00000040
|
||||
#define MPC85xx_PMUXCR_QE12 0x00000008
|
||||
static __be32 __iomem *pmuxcr;
|
||||
|
||||
np = of_find_node_by_name(NULL, "global-utilities");
|
||||
|
||||
if (np) {
|
||||
pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
|
||||
|
||||
if (!pmuxcr)
|
||||
printk(KERN_EMERG "Error: Alternate function"
|
||||
" signal multiplex control register not"
|
||||
" mapped!\n");
|
||||
else
|
||||
/* P1021 has pins muxed for QE and other functions. To
|
||||
* enable QE UEC mode, we need to set bit QE0 for UCC1
|
||||
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
|
||||
* and QE12 for QE MII management singals in PMUXCR
|
||||
* register.
|
||||
*/
|
||||
setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
|
||||
MPC85xx_PMUXCR_QE3 |
|
||||
MPC85xx_PMUXCR_QE9 |
|
||||
MPC85xx_PMUXCR_QE12);
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static struct of_device_id p1021_ids[] = {
|
||||
{ .type = "soc", },
|
||||
{ .compatible = "soc", },
|
||||
{ .compatible = "simple-bus", },
|
||||
{ .type = "qe", },
|
||||
{ .compatible = "fsl,qe", },
|
||||
{ .compatible = "gianfar", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init mpc85xx_publish_devices(void)
|
||||
{
|
||||
if (machine_is(mpc8568_mds))
|
||||
@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init p1021_publish_devices(void)
|
||||
{
|
||||
/* Publish the QE devices */
|
||||
of_platform_bus_probe(NULL, p1021_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
|
||||
machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
|
||||
machine_device_initcall(p1021_mds, p1021_publish_devices);
|
||||
|
||||
machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
|
||||
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
|
||||
machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
|
||||
|
||||
static void __init mpc85xx_mds_pic_init(void)
|
||||
{
|
||||
@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void)
|
||||
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
|
||||
MPIC_BROKEN_FRR_NIRQS,
|
||||
MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
of_node_put(np);
|
||||
@ -380,7 +449,11 @@ static void __init mpc85xx_mds_pic_init(void)
|
||||
if (!np)
|
||||
return;
|
||||
}
|
||||
qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
|
||||
if (machine_is(p1021_mds))
|
||||
qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
|
||||
qe_ic_cascade_high_mpic);
|
||||
else
|
||||
qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
|
||||
of_node_put(np);
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
}
|
||||
@ -426,3 +499,26 @@ define_machine(mpc8569_mds) {
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init p1021_mds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
|
||||
|
||||
}
|
||||
|
||||
define_machine(p1021_mds) {
|
||||
.name = "P1021 MDS",
|
||||
.probe = p1021_mds_probe,
|
||||
.setup_arch = mpc85xx_mds_setup_arch,
|
||||
.init_IRQ = mpc85xx_mds_pic_init,
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
|
||||
* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Tony Li <tony.li@freescale.com>
|
||||
* Jason Jin <Jason.jin@freescale.com>
|
||||
@ -22,14 +22,20 @@
|
||||
#include <asm/prom.h>
|
||||
#include <asm/hw_irq.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
#include <asm/mpic.h>
|
||||
#include "fsl_msi.h"
|
||||
|
||||
LIST_HEAD(msi_head);
|
||||
|
||||
struct fsl_msi_feature {
|
||||
u32 fsl_pic_ip;
|
||||
u32 msiir_offset;
|
||||
};
|
||||
|
||||
static struct fsl_msi *fsl_msi;
|
||||
struct fsl_msi_cascade_data {
|
||||
struct fsl_msi *msi_data;
|
||||
int index;
|
||||
};
|
||||
|
||||
static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
|
||||
{
|
||||
@ -54,10 +60,12 @@ static struct irq_chip fsl_msi_chip = {
|
||||
static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct fsl_msi *msi_data = h->host_data;
|
||||
struct irq_chip *chip = &fsl_msi_chip;
|
||||
|
||||
irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
|
||||
|
||||
set_irq_chip_data(virq, msi_data);
|
||||
set_irq_chip_and_handler(virq, chip, handle_edge_irq);
|
||||
|
||||
return 0;
|
||||
@ -96,11 +104,12 @@ static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
|
||||
static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
|
||||
{
|
||||
struct msi_desc *entry;
|
||||
struct fsl_msi *msi_data = fsl_msi;
|
||||
struct fsl_msi *msi_data;
|
||||
|
||||
list_for_each_entry(entry, &pdev->msi_list, list) {
|
||||
if (entry->irq == NO_IRQ)
|
||||
continue;
|
||||
msi_data = get_irq_data(entry->irq);
|
||||
set_irq_msi(entry->irq, NULL);
|
||||
msi_bitmap_free_hwirqs(&msi_data->bitmap,
|
||||
virq_to_hw(entry->irq), 1);
|
||||
@ -111,9 +120,10 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
|
||||
}
|
||||
|
||||
static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
|
||||
struct msi_msg *msg)
|
||||
struct msi_msg *msg,
|
||||
struct fsl_msi *fsl_msi_data)
|
||||
{
|
||||
struct fsl_msi *msi_data = fsl_msi;
|
||||
struct fsl_msi *msi_data = fsl_msi_data;
|
||||
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
||||
u32 base = 0;
|
||||
|
||||
@ -130,14 +140,19 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
|
||||
|
||||
static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
||||
{
|
||||
int rc, hwirq;
|
||||
int rc, hwirq = -ENOMEM;
|
||||
unsigned int virq;
|
||||
struct msi_desc *entry;
|
||||
struct msi_msg msg;
|
||||
struct fsl_msi *msi_data = fsl_msi;
|
||||
struct fsl_msi *msi_data;
|
||||
|
||||
list_for_each_entry(entry, &pdev->msi_list, list) {
|
||||
hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
|
||||
list_for_each_entry(msi_data, &msi_head, list) {
|
||||
hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
|
||||
if (hwirq >= 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (hwirq < 0) {
|
||||
rc = hwirq;
|
||||
pr_debug("%s: fail allocating msi interrupt\n",
|
||||
@ -154,25 +169,31 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
||||
rc = -ENOSPC;
|
||||
goto out_free;
|
||||
}
|
||||
set_irq_data(virq, msi_data);
|
||||
set_irq_msi(virq, entry);
|
||||
|
||||
fsl_compose_msi_msg(pdev, hwirq, &msg);
|
||||
fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
|
||||
write_msi_msg(virq, &msg);
|
||||
}
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
/* free by the caller of this function */
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned int cascade_irq;
|
||||
struct fsl_msi *msi_data = fsl_msi;
|
||||
struct fsl_msi *msi_data;
|
||||
int msir_index = -1;
|
||||
u32 msir_value = 0;
|
||||
u32 intr_index;
|
||||
u32 have_shift = 0;
|
||||
struct fsl_msi_cascade_data *cascade_data;
|
||||
|
||||
cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
|
||||
msi_data = cascade_data->msi_data;
|
||||
|
||||
raw_spin_lock(&desc->lock);
|
||||
if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
|
||||
@ -187,13 +208,13 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
|
||||
if (unlikely(desc->status & IRQ_INPROGRESS))
|
||||
goto unlock;
|
||||
|
||||
msir_index = (int)desc->handler_data;
|
||||
msir_index = cascade_data->index;
|
||||
|
||||
if (msir_index >= NR_MSI_REG)
|
||||
cascade_irq = NO_IRQ;
|
||||
|
||||
desc->status |= IRQ_INPROGRESS;
|
||||
switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
|
||||
switch (msi_data->feature & FSL_PIC_IP_MASK) {
|
||||
case FSL_PIC_IP_MPIC:
|
||||
msir_value = fsl_msi_read(msi_data->msi_regs,
|
||||
msir_index * 0x10);
|
||||
@ -229,6 +250,30 @@ unlock:
|
||||
raw_spin_unlock(&desc->lock);
|
||||
}
|
||||
|
||||
static int fsl_of_msi_remove(struct of_device *ofdev)
|
||||
{
|
||||
struct fsl_msi *msi = ofdev->dev.platform_data;
|
||||
int virq, i;
|
||||
struct fsl_msi_cascade_data *cascade_data;
|
||||
|
||||
if (msi->list.prev != NULL)
|
||||
list_del(&msi->list);
|
||||
for (i = 0; i < NR_MSI_REG; i++) {
|
||||
virq = msi->msi_virqs[i];
|
||||
if (virq != NO_IRQ) {
|
||||
cascade_data = get_irq_data(virq);
|
||||
kfree(cascade_data);
|
||||
irq_dispose_mapping(virq);
|
||||
}
|
||||
}
|
||||
if (msi->bitmap.bitmap)
|
||||
msi_bitmap_free(&msi->bitmap);
|
||||
iounmap(msi->msi_regs);
|
||||
kfree(msi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit fsl_of_msi_probe(struct of_device *dev,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
@ -239,15 +284,18 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
|
||||
int virt_msir;
|
||||
const u32 *p;
|
||||
struct fsl_msi_feature *features = match->data;
|
||||
struct fsl_msi_cascade_data *cascade_data = NULL;
|
||||
int len;
|
||||
u32 offset;
|
||||
|
||||
printk(KERN_DEBUG "Setting up Freescale MSI support\n");
|
||||
|
||||
msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
|
||||
if (!msi) {
|
||||
dev_err(&dev->dev, "No memory for MSI structure\n");
|
||||
err = -ENOMEM;
|
||||
goto error_out;
|
||||
return -ENOMEM;
|
||||
}
|
||||
dev->dev.platform_data = msi;
|
||||
|
||||
msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
|
||||
NR_MSI_IRQS, &fsl_msi_host_ops, 0);
|
||||
@ -298,27 +346,47 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
|
||||
err = -EINVAL;
|
||||
goto error_out;
|
||||
}
|
||||
offset = 0;
|
||||
p = of_get_property(dev->node, "msi-available-ranges", &len);
|
||||
if (p)
|
||||
offset = *p / IRQS_PER_MSI_REG;
|
||||
|
||||
count /= sizeof(u32);
|
||||
for (i = 0; i < count / 2; i++) {
|
||||
if (i > NR_MSI_REG)
|
||||
break;
|
||||
for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
|
||||
virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
|
||||
if (virt_msir != NO_IRQ) {
|
||||
set_irq_data(virt_msir, (void *)i);
|
||||
cascade_data = kzalloc(
|
||||
sizeof(struct fsl_msi_cascade_data),
|
||||
GFP_KERNEL);
|
||||
if (!cascade_data) {
|
||||
dev_err(&dev->dev,
|
||||
"No memory for MSI cascade data\n");
|
||||
err = -ENOMEM;
|
||||
goto error_out;
|
||||
}
|
||||
msi->msi_virqs[i] = virt_msir;
|
||||
cascade_data->index = i + offset;
|
||||
cascade_data->msi_data = msi;
|
||||
set_irq_data(virt_msir, (void *)cascade_data);
|
||||
set_irq_chained_handler(virt_msir, fsl_msi_cascade);
|
||||
}
|
||||
}
|
||||
|
||||
fsl_msi = msi;
|
||||
list_add_tail(&msi->list, &msi_head);
|
||||
|
||||
WARN_ON(ppc_md.setup_msi_irqs);
|
||||
ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
|
||||
ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
|
||||
ppc_md.msi_check_device = fsl_msi_check_device;
|
||||
/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
|
||||
if (!ppc_md.setup_msi_irqs) {
|
||||
ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
|
||||
ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
|
||||
ppc_md.msi_check_device = fsl_msi_check_device;
|
||||
} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
|
||||
dev_err(&dev->dev, "Different MSI driver already installed!\n");
|
||||
err = -ENODEV;
|
||||
goto error_out;
|
||||
}
|
||||
return 0;
|
||||
error_out:
|
||||
kfree(msi);
|
||||
fsl_of_msi_remove(dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -351,6 +419,7 @@ static struct of_platform_driver fsl_of_msi_driver = {
|
||||
.of_match_table = fsl_of_msi_ids,
|
||||
},
|
||||
.probe = fsl_of_msi_probe,
|
||||
.remove = fsl_of_msi_remove,
|
||||
};
|
||||
|
||||
static __init int fsl_of_msi_init(void)
|
||||
|
||||
@ -32,8 +32,11 @@ struct fsl_msi {
|
||||
u32 msi_addr_hi;
|
||||
void __iomem *msi_regs;
|
||||
u32 feature;
|
||||
int msi_virqs[NR_MSI_REG];
|
||||
|
||||
struct msi_bitmap bitmap;
|
||||
|
||||
struct list_head list; /* support multiple MSI banks */
|
||||
};
|
||||
|
||||
#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
|
||||
|
||||
@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
|
||||
.setup_utl = ppc460ex_pciex_init_utl,
|
||||
};
|
||||
|
||||
static int __init ppc460sx_pciex_core_init(struct device_node *np)
|
||||
{
|
||||
/* HSS drive amplitude */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
|
||||
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
|
||||
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
|
||||
|
||||
/* HSS TX pre-emphasis */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
|
||||
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
|
||||
/* HSS TX calibration control */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
|
||||
|
||||
/* HSS TX slew control */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
|
||||
|
||||
udelay(100);
|
||||
|
||||
/* De-assert PLLRESET */
|
||||
dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
|
||||
|
||||
/* Reset DL, UTL, GPL before configuration */
|
||||
mtdcri(SDR0, PESDR0_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
mtdcri(SDR0, PESDR1_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
mtdcri(SDR0, PESDR2_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* If bifurcation is not enabled, u-boot would have disabled the
|
||||
* third PCIe port
|
||||
*/
|
||||
if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
|
||||
0x00000001)) {
|
||||
printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
|
||||
printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
|
||||
return 3;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
|
||||
return 2;
|
||||
}
|
||||
|
||||
static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
|
||||
if (port->endpoint)
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
|
||||
0x01000000, 0);
|
||||
else
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
|
||||
0, 0x01000000);
|
||||
|
||||
/*Gen-1*/
|
||||
mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
|
||||
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
|
||||
(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
|
||||
PESDRx_RCSSET_RSTPYN);
|
||||
|
||||
port->has_ibpre = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
/* Max 128 Bytes */
|
||||
out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
|
||||
.core_init = ppc460sx_pciex_core_init,
|
||||
.port_init_hw = ppc460sx_pciex_init_port_hw,
|
||||
.setup_utl = ppc460sx_pciex_init_utl,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_44x */
|
||||
|
||||
#ifdef CONFIG_40x
|
||||
@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
|
||||
}
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
|
||||
ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
|
||||
ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
|
||||
#endif /* CONFIG_44x */
|
||||
#ifdef CONFIG_40x
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
|
||||
|
||||
@ -323,6 +323,64 @@
|
||||
#define PESDR0_460EX_IHS1 0x036C
|
||||
#define PESDR0_460EX_IHS2 0x036D
|
||||
|
||||
/*
|
||||
* 460SX addtional DCRs
|
||||
*/
|
||||
#define PESDRn_460SX_RCEI 0x02
|
||||
|
||||
#define PESDR0_460SX_HSSL0DAMP 0x320
|
||||
#define PESDR0_460SX_HSSL1DAMP 0x321
|
||||
#define PESDR0_460SX_HSSL2DAMP 0x322
|
||||
#define PESDR0_460SX_HSSL3DAMP 0x323
|
||||
#define PESDR0_460SX_HSSL4DAMP 0x324
|
||||
#define PESDR0_460SX_HSSL5DAMP 0x325
|
||||
#define PESDR0_460SX_HSSL6DAMP 0x326
|
||||
#define PESDR0_460SX_HSSL7DAMP 0x327
|
||||
|
||||
#define PESDR1_460SX_HSSL0DAMP 0x354
|
||||
#define PESDR1_460SX_HSSL1DAMP 0x355
|
||||
#define PESDR1_460SX_HSSL2DAMP 0x356
|
||||
#define PESDR1_460SX_HSSL3DAMP 0x357
|
||||
|
||||
#define PESDR2_460SX_HSSL0DAMP 0x384
|
||||
#define PESDR2_460SX_HSSL1DAMP 0x385
|
||||
#define PESDR2_460SX_HSSL2DAMP 0x386
|
||||
#define PESDR2_460SX_HSSL3DAMP 0x387
|
||||
|
||||
#define PESDR0_460SX_HSSL0COEFA 0x328
|
||||
#define PESDR0_460SX_HSSL1COEFA 0x329
|
||||
#define PESDR0_460SX_HSSL2COEFA 0x32A
|
||||
#define PESDR0_460SX_HSSL3COEFA 0x32B
|
||||
#define PESDR0_460SX_HSSL4COEFA 0x32C
|
||||
#define PESDR0_460SX_HSSL5COEFA 0x32D
|
||||
#define PESDR0_460SX_HSSL6COEFA 0x32E
|
||||
#define PESDR0_460SX_HSSL7COEFA 0x32F
|
||||
|
||||
#define PESDR1_460SX_HSSL0COEFA 0x358
|
||||
#define PESDR1_460SX_HSSL1COEFA 0x359
|
||||
#define PESDR1_460SX_HSSL2COEFA 0x35A
|
||||
#define PESDR1_460SX_HSSL3COEFA 0x35B
|
||||
|
||||
#define PESDR2_460SX_HSSL0COEFA 0x388
|
||||
#define PESDR2_460SX_HSSL1COEFA 0x389
|
||||
#define PESDR2_460SX_HSSL2COEFA 0x38A
|
||||
#define PESDR2_460SX_HSSL3COEFA 0x38B
|
||||
|
||||
#define PESDR0_460SX_HSSL1CALDRV 0x339
|
||||
#define PESDR1_460SX_HSSL1CALDRV 0x361
|
||||
#define PESDR2_460SX_HSSL1CALDRV 0x391
|
||||
|
||||
#define PESDR0_460SX_HSSSLEW 0x338
|
||||
#define PESDR1_460SX_HSSSLEW 0x360
|
||||
#define PESDR2_460SX_HSSSLEW 0x390
|
||||
|
||||
#define PESDR0_460SX_HSSCTLSET 0x31E
|
||||
#define PESDR1_460SX_HSSCTLSET 0x352
|
||||
#define PESDR2_460SX_HSSCTLSET 0x382
|
||||
|
||||
#define PESDR0_460SX_RCSSET 0x304
|
||||
#define PESDR1_460SX_RCSSET 0x344
|
||||
#define PESDR2_460SX_RCSSET 0x374
|
||||
/*
|
||||
* Of the above, some are common offsets from the base
|
||||
*/
|
||||
|
||||
@ -14,6 +14,6 @@
|
||||
#define L1_CACHE_BYTES 256
|
||||
#define L1_CACHE_SHIFT 8
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#endif
|
||||
|
||||
@ -264,7 +264,7 @@ restore_registers:
|
||||
lghi %r2,0
|
||||
br %r14
|
||||
|
||||
.section .data.nosave,"aw",@progbits
|
||||
.section .data..nosave,"aw",@progbits
|
||||
.align 8
|
||||
.Ldisabled_wait_31:
|
||||
.long 0x000a0000,0x00000000
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
SECTIONS
|
||||
{
|
||||
.rodata.compressed : {
|
||||
.rodata..compressed : {
|
||||
input_len = .;
|
||||
LONG(input_data_end - input_data) input_data = .;
|
||||
*(.data)
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct cache_info {
|
||||
|
||||
@ -325,7 +325,7 @@ main1:
|
||||
(*rr)->next = NULL;
|
||||
}
|
||||
printf("! Generated by btfixupprep. Do not edit.\n\n");
|
||||
printf("\t.section\t\".data.init\",#alloc,#write\n\t.align\t4\n\n");
|
||||
printf("\t.section\t\".data..init\",#alloc,#write\n\t.align\t4\n\n");
|
||||
printf("\t.global\t___btfixup_start\n___btfixup_start:\n\n");
|
||||
for (i = 0; i < last; i++) {
|
||||
f = array + i;
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
|
||||
#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#ifdef CONFIG_SPARC32
|
||||
#include <asm/asi.h>
|
||||
|
||||
@ -94,7 +94,7 @@ SECTIONS
|
||||
.data : {
|
||||
INIT_TASK_DATA(KERNEL_STACK_SIZE)
|
||||
. = ALIGN(KERNEL_STACK_SIZE);
|
||||
*(.data.init_irqstack)
|
||||
*(.data..init_irqstack)
|
||||
DATA_DATA
|
||||
*(.data.* .gnu.linkonce.d.*)
|
||||
SORT(CONSTRUCTORS)
|
||||
|
||||
@ -34,5 +34,5 @@ union thread_union init_thread_union __init_task_data =
|
||||
{ INIT_THREAD_INFO(init_task) };
|
||||
|
||||
union thread_union cpu0_irqstack
|
||||
__attribute__((__section__(".data.init_irqstack"))) =
|
||||
__attribute__((__section__(".data..init_irqstack"))) =
|
||||
{ INIT_THREAD_INFO(init_task) };
|
||||
|
||||
@ -50,7 +50,7 @@ SECTIONS
|
||||
{
|
||||
INIT_TASK_DATA(KERNEL_STACK_SIZE)
|
||||
. = ALIGN(KERNEL_STACK_SIZE);
|
||||
*(.data.init_irqstack)
|
||||
*(.data..init_irqstack)
|
||||
DATA_DATA
|
||||
*(.gnu.linkonce.d*)
|
||||
CONSTRUCTORS
|
||||
|
||||
3
arch/x86/.gitignore
vendored
Normal file
3
arch/x86/.gitignore
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
boot/compressed/vmlinux
|
||||
tools/test_get_len
|
||||
|
||||
@ -77,7 +77,7 @@ int main(int argc, char *argv[])
|
||||
offs += 32*1024 + 18; /* Add 32K + 18 bytes slack */
|
||||
offs = (offs+4095) & ~4095; /* Round to a 4K boundary */
|
||||
|
||||
printf(".section \".rodata.compressed\",\"a\",@progbits\n");
|
||||
printf(".section \".rodata..compressed\",\"a\",@progbits\n");
|
||||
printf(".globl z_input_len\n");
|
||||
printf("z_input_len = %lu\n", ilen);
|
||||
printf(".globl z_output_len\n");
|
||||
|
||||
@ -26,8 +26,8 @@ SECTIONS
|
||||
HEAD_TEXT
|
||||
_ehead = . ;
|
||||
}
|
||||
.rodata.compressed : {
|
||||
*(.rodata.compressed)
|
||||
.rodata..compressed : {
|
||||
*(.rodata..compressed)
|
||||
}
|
||||
.text : {
|
||||
_text = .; /* Text */
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#define INTERNODE_CACHE_SHIFT CONFIG_X86_INTERNODE_CACHE_SHIFT
|
||||
#define INTERNODE_CACHE_BYTES (1 << INTERNODE_CACHE_SHIFT)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user