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usb: dwc2: gadget: Fix GUSBCFG.USBTRDTIM value
USBTrdTim must be programmed to 0x5 when phy has a UTMI+ 16-bit wide interface or 0x9 when it has a 8-bit wide interface. GUSBCFG reset value (Value After Reset: 0x1400) sets USBTrdTim to 0x5. In case of 8-bit UTMI+, without clearing GUSBCFG.USBTRDTIM mask, USBTrdTim results in 0xD (0x5 | 0x9). That's why we need to clear GUSBCFG.USBTRDTIM mask before setting USBTrdTim value, to ensure USBTrdTim is correctly set in case of 8-bit UTMI+. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -3169,7 +3169,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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/* keep other bits untouched (so e.g. forced modes are not lost) */
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usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
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GUSBCFG_HNPCAP);
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GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
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if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
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(hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
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@ -4123,7 +4123,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
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/* keep other bits untouched (so e.g. forced modes are not lost) */
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usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
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GUSBCFG_HNPCAP);
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GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
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/* set the PLL on, remove the HNP/SRP and set the PHY */
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trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
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