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drm/radeon/kms/evergreen: add initial CS parser
Advanced validation is not implemented yet. The mesa code that uses this will be released soon. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
36d1701c50
commit
cb5fcbd540
@ -33,6 +33,9 @@ $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
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$(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable
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$(call if_changed,mkregtable)
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$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable
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$(call if_changed,mkregtable)
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$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
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$(obj)/r200.o: $(obj)/r200_reg_safe.h
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@ -47,6 +50,8 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
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$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
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$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
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radeon_irq.o r300_cmdbuf.o r600_cp.o
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# add KMS driver
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@ -60,7 +65,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
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r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
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r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o
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evergreen.o evergreen_cs.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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1356
drivers/gpu/drm/radeon/evergreen_cs.c
Normal file
1356
drivers/gpu/drm/radeon/evergreen_cs.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -151,6 +151,9 @@
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#define EVERGREEN_DATA_FORMAT 0x6b00
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# define EVERGREEN_INTERLEAVE_EN (1 << 0)
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#define EVERGREEN_DESKTOP_HEIGHT 0x6b04
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#define EVERGREEN_VLINE_START_END 0x6b08
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#define EVERGREEN_VLINE_STATUS 0x6bb8
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# define EVERGREEN_VLINE_STAT (1 << 12)
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#define EVERGREEN_VIEWPORT_START 0x6d70
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#define EVERGREEN_VIEWPORT_SIZE 0x6d74
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@ -218,6 +218,8 @@
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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#define PA_SC_AA_CONFIG 0x28C04
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#define MSAA_NUM_SAMPLES_SHIFT 0
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#define MSAA_NUM_SAMPLES_MASK 0x3
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#define PA_SC_CLIPRECT_RULE 0x2820C
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#define PA_SC_EDGERULE 0x28230
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#define PA_SC_FIFO_SIZE 0x8BCC
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@ -553,4 +555,466 @@
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# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
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# define DC_HPDx_EN (1 << 28)
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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#define PACKET2_PAD_SHIFT 0
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#define PACKET2_PAD_MASK (0x3fffffff << 0)
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDIRECT_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_INDIRECT_BUFFER_END 0x17
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_DRAW_INDEX_OFFSET 0x29
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDEX 0x2B
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_DRAW_INDEX_IMMD 0x2E
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
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#define PACKET3_MEM_SEMAPHORE 0x39
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#define PACKET3_MPEG_INDEX 0x3A
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_INDIRECT_BUFFER 0x32
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
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# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
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# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
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# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
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# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
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# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
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# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
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# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
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# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
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# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
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# define PACKET3_CB11_DEST_BASE_ENA (1 << 17)
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# define PACKET3_FULL_CACHE_ENA (1 << 20)
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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# define PACKET3_VC_ACTION_ENA (1 << 24)
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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# define PACKET3_DB_ACTION_ENA (1 << 26)
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# define PACKET3_SH_ACTION_ENA (1 << 27)
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# define PACKET3_SMX_ACTION_ENA (1 << 28)
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#define PACKET3_ME_INITIALIZE 0x44
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#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
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#define PACKET3_COND_WRITE 0x45
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#define PACKET3_EVENT_WRITE 0x46
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_PREAMBLE_CNTL 0x4A
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#define PACKET3_RB_OFFSET 0x4B
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#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
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#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
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#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
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#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
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#define PACKET3_ONE_REG_WRITE 0x57
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#define PACKET3_SET_CONFIG_REG 0x68
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#define PACKET3_SET_CONFIG_REG_START 0x00008000
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#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
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#define PACKET3_SET_CONTEXT_REG 0x69
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#define PACKET3_SET_CONTEXT_REG_START 0x00028000
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#define PACKET3_SET_CONTEXT_REG_END 0x00029000
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#define PACKET3_SET_ALU_CONST 0x6A
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/* alu const buffers only; no reg file */
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#define PACKET3_SET_BOOL_CONST 0x6B
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#define PACKET3_SET_BOOL_CONST_START 0x0003a500
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#define PACKET3_SET_BOOL_CONST_END 0x0003a518
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#define PACKET3_SET_LOOP_CONST 0x6C
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#define PACKET3_SET_LOOP_CONST_START 0x0003a200
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#define PACKET3_SET_LOOP_CONST_END 0x0003a500
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#define PACKET3_SET_RESOURCE 0x6D
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#define PACKET3_SET_RESOURCE_START 0x00030000
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#define PACKET3_SET_RESOURCE_END 0x00038000
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#define PACKET3_SET_SAMPLER 0x6E
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#define PACKET3_SET_SAMPLER_START 0x0003c000
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#define PACKET3_SET_SAMPLER_END 0x0003c600
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#define PACKET3_SET_CTL_CONST 0x6F
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#define PACKET3_SET_CTL_CONST_START 0x0003cff0
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#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
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#define PACKET3_SET_RESOURCE_OFFSET 0x70
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#define PACKET3_SET_ALU_CONST_VS 0x71
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#define PACKET3_SET_ALU_CONST_DI 0x72
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#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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#define PACKET3_SET_RESOURCE_INDIRECT 0x74
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#define PACKET3_SET_APPEND_CNT 0x75
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#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
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#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
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#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
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#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
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#define SQ_TEX_VTX_INVALID_BUFFER 0x1
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#define SQ_TEX_VTX_VALID_TEXTURE 0x2
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#define SQ_TEX_VTX_VALID_BUFFER 0x3
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#define SQ_CONST_MEM_BASE 0x8df8
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#define SQ_ESGS_RING_SIZE 0x8c44
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#define SQ_GSVS_RING_SIZE 0x8c4c
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#define SQ_ESTMP_RING_SIZE 0x8c54
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#define SQ_GSTMP_RING_SIZE 0x8c5c
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#define SQ_VSTMP_RING_SIZE 0x8c64
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#define SQ_PSTMP_RING_SIZE 0x8c6c
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#define SQ_LSTMP_RING_SIZE 0x8e14
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#define SQ_HSTMP_RING_SIZE 0x8e1c
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#define VGT_TF_RING_SIZE 0x8988
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#define SQ_ESGS_RING_ITEMSIZE 0x28900
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#define SQ_GSVS_RING_ITEMSIZE 0x28904
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#define SQ_ESTMP_RING_ITEMSIZE 0x28908
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#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
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#define SQ_VSTMP_RING_ITEMSIZE 0x28910
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#define SQ_PSTMP_RING_ITEMSIZE 0x28914
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#define SQ_LSTMP_RING_ITEMSIZE 0x28830
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#define SQ_HSTMP_RING_ITEMSIZE 0x28834
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#define SQ_GS_VERT_ITEMSIZE 0x2891c
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#define SQ_GS_VERT_ITEMSIZE_1 0x28920
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#define SQ_GS_VERT_ITEMSIZE_2 0x28924
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#define SQ_GS_VERT_ITEMSIZE_3 0x28928
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#define SQ_GSVS_RING_OFFSET_1 0x2892c
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#define SQ_GSVS_RING_OFFSET_2 0x28930
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#define SQ_GSVS_RING_OFFSET_3 0x28934
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#define SQ_ALU_CONST_CACHE_PS_0 0x28940
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#define SQ_ALU_CONST_CACHE_PS_1 0x28944
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#define SQ_ALU_CONST_CACHE_PS_2 0x28948
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#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
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#define SQ_ALU_CONST_CACHE_PS_4 0x28950
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#define SQ_ALU_CONST_CACHE_PS_5 0x28954
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#define SQ_ALU_CONST_CACHE_PS_6 0x28958
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#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
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#define SQ_ALU_CONST_CACHE_PS_8 0x28960
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#define SQ_ALU_CONST_CACHE_PS_9 0x28964
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#define SQ_ALU_CONST_CACHE_PS_10 0x28968
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#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
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#define SQ_ALU_CONST_CACHE_PS_12 0x28970
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#define SQ_ALU_CONST_CACHE_PS_13 0x28974
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#define SQ_ALU_CONST_CACHE_PS_14 0x28978
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#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
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#define SQ_ALU_CONST_CACHE_VS_0 0x28980
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#define SQ_ALU_CONST_CACHE_VS_1 0x28984
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#define SQ_ALU_CONST_CACHE_VS_2 0x28988
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#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
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#define SQ_ALU_CONST_CACHE_VS_4 0x28990
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#define SQ_ALU_CONST_CACHE_VS_5 0x28994
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#define SQ_ALU_CONST_CACHE_VS_6 0x28998
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#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
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#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
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#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
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#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
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#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
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#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
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#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
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#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
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#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
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#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
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#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
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#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
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#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
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#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
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#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
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#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
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#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
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#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
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#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
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#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
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#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
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#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
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#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
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#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
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#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
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#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
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#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
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#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
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#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
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#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
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#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
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#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
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#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
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#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
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#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
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#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
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#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
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#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
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#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
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#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
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#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
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#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
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#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
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#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
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#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
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#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
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#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
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#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
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#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
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#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
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#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
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#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
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#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
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#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
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#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
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#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
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#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
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#define DB_DEPTH_CONTROL 0x28800
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#define DB_DEPTH_VIEW 0x28008
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#define DB_HTILE_DATA_BASE 0x28014
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#define DB_Z_INFO 0x28040
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# define Z_ARRAY_MODE(x) ((x) << 4)
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#define DB_STENCIL_INFO 0x28044
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#define DB_Z_READ_BASE 0x28048
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#define DB_STENCIL_READ_BASE 0x2804c
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#define DB_Z_WRITE_BASE 0x28050
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#define DB_STENCIL_WRITE_BASE 0x28054
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#define DB_DEPTH_SIZE 0x28058
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#define SQ_PGM_START_PS 0x28840
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#define SQ_PGM_START_VS 0x2885c
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#define SQ_PGM_START_GS 0x28874
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#define SQ_PGM_START_ES 0x2888c
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#define SQ_PGM_START_FS 0x288a4
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#define SQ_PGM_START_HS 0x288b8
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#define SQ_PGM_START_LS 0x288d0
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#define VGT_STRMOUT_CONFIG 0x28b94
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||||
#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
|
||||
|
||||
#define CB_TARGET_MASK 0x28238
|
||||
#define CB_SHADER_MASK 0x2823c
|
||||
|
||||
#define GDS_ADDR_BASE 0x28720
|
||||
|
||||
#define CB_IMMED0_BASE 0x28b9c
|
||||
#define CB_IMMED1_BASE 0x28ba0
|
||||
#define CB_IMMED2_BASE 0x28ba4
|
||||
#define CB_IMMED3_BASE 0x28ba8
|
||||
#define CB_IMMED4_BASE 0x28bac
|
||||
#define CB_IMMED5_BASE 0x28bb0
|
||||
#define CB_IMMED6_BASE 0x28bb4
|
||||
#define CB_IMMED7_BASE 0x28bb8
|
||||
#define CB_IMMED8_BASE 0x28bbc
|
||||
#define CB_IMMED9_BASE 0x28bc0
|
||||
#define CB_IMMED10_BASE 0x28bc4
|
||||
#define CB_IMMED11_BASE 0x28bc8
|
||||
|
||||
/* all 12 CB blocks have these regs */
|
||||
#define CB_COLOR0_BASE 0x28c60
|
||||
#define CB_COLOR0_PITCH 0x28c64
|
||||
#define CB_COLOR0_SLICE 0x28c68
|
||||
#define CB_COLOR0_VIEW 0x28c6c
|
||||
#define CB_COLOR0_INFO 0x28c70
|
||||
# define CB_ARRAY_MODE(x) ((x) << 8)
|
||||
# define ARRAY_LINEAR_GENERAL 0
|
||||
# define ARRAY_LINEAR_ALIGNED 1
|
||||
# define ARRAY_1D_TILED_THIN1 2
|
||||
# define ARRAY_2D_TILED_THIN1 4
|
||||
#define CB_COLOR0_ATTRIB 0x28c74
|
||||
#define CB_COLOR0_DIM 0x28c78
|
||||
/* only CB0-7 blocks have these regs */
|
||||
#define CB_COLOR0_CMASK 0x28c7c
|
||||
#define CB_COLOR0_CMASK_SLICE 0x28c80
|
||||
#define CB_COLOR0_FMASK 0x28c84
|
||||
#define CB_COLOR0_FMASK_SLICE 0x28c88
|
||||
#define CB_COLOR0_CLEAR_WORD0 0x28c8c
|
||||
#define CB_COLOR0_CLEAR_WORD1 0x28c90
|
||||
#define CB_COLOR0_CLEAR_WORD2 0x28c94
|
||||
#define CB_COLOR0_CLEAR_WORD3 0x28c98
|
||||
|
||||
#define CB_COLOR1_BASE 0x28c9c
|
||||
#define CB_COLOR2_BASE 0x28cd8
|
||||
#define CB_COLOR3_BASE 0x28d14
|
||||
#define CB_COLOR4_BASE 0x28d50
|
||||
#define CB_COLOR5_BASE 0x28d8c
|
||||
#define CB_COLOR6_BASE 0x28dc8
|
||||
#define CB_COLOR7_BASE 0x28e04
|
||||
#define CB_COLOR8_BASE 0x28e40
|
||||
#define CB_COLOR9_BASE 0x28e5c
|
||||
#define CB_COLOR10_BASE 0x28e78
|
||||
#define CB_COLOR11_BASE 0x28e94
|
||||
|
||||
#define CB_COLOR1_PITCH 0x28ca0
|
||||
#define CB_COLOR2_PITCH 0x28cdc
|
||||
#define CB_COLOR3_PITCH 0x28d18
|
||||
#define CB_COLOR4_PITCH 0x28d54
|
||||
#define CB_COLOR5_PITCH 0x28d90
|
||||
#define CB_COLOR6_PITCH 0x28dcc
|
||||
#define CB_COLOR7_PITCH 0x28e08
|
||||
#define CB_COLOR8_PITCH 0x28e44
|
||||
#define CB_COLOR9_PITCH 0x28e60
|
||||
#define CB_COLOR10_PITCH 0x28e7c
|
||||
#define CB_COLOR11_PITCH 0x28e98
|
||||
|
||||
#define CB_COLOR1_SLICE 0x28ca4
|
||||
#define CB_COLOR2_SLICE 0x28ce0
|
||||
#define CB_COLOR3_SLICE 0x28d1c
|
||||
#define CB_COLOR4_SLICE 0x28d58
|
||||
#define CB_COLOR5_SLICE 0x28d94
|
||||
#define CB_COLOR6_SLICE 0x28dd0
|
||||
#define CB_COLOR7_SLICE 0x28e0c
|
||||
#define CB_COLOR8_SLICE 0x28e48
|
||||
#define CB_COLOR9_SLICE 0x28e64
|
||||
#define CB_COLOR10_SLICE 0x28e80
|
||||
#define CB_COLOR11_SLICE 0x28e9c
|
||||
|
||||
#define CB_COLOR1_VIEW 0x28ca8
|
||||
#define CB_COLOR2_VIEW 0x28ce4
|
||||
#define CB_COLOR3_VIEW 0x28d20
|
||||
#define CB_COLOR4_VIEW 0x28d5c
|
||||
#define CB_COLOR5_VIEW 0x28d98
|
||||
#define CB_COLOR6_VIEW 0x28dd4
|
||||
#define CB_COLOR7_VIEW 0x28e10
|
||||
#define CB_COLOR8_VIEW 0x28e4c
|
||||
#define CB_COLOR9_VIEW 0x28e68
|
||||
#define CB_COLOR10_VIEW 0x28e84
|
||||
#define CB_COLOR11_VIEW 0x28ea0
|
||||
|
||||
#define CB_COLOR1_INFO 0x28cac
|
||||
#define CB_COLOR2_INFO 0x28ce8
|
||||
#define CB_COLOR3_INFO 0x28d24
|
||||
#define CB_COLOR4_INFO 0x28d60
|
||||
#define CB_COLOR5_INFO 0x28d9c
|
||||
#define CB_COLOR6_INFO 0x28dd8
|
||||
#define CB_COLOR7_INFO 0x28e14
|
||||
#define CB_COLOR8_INFO 0x28e50
|
||||
#define CB_COLOR9_INFO 0x28e6c
|
||||
#define CB_COLOR10_INFO 0x28e88
|
||||
#define CB_COLOR11_INFO 0x28ea4
|
||||
|
||||
#define CB_COLOR1_ATTRIB 0x28cb0
|
||||
#define CB_COLOR2_ATTRIB 0x28cec
|
||||
#define CB_COLOR3_ATTRIB 0x28d28
|
||||
#define CB_COLOR4_ATTRIB 0x28d64
|
||||
#define CB_COLOR5_ATTRIB 0x28da0
|
||||
#define CB_COLOR6_ATTRIB 0x28ddc
|
||||
#define CB_COLOR7_ATTRIB 0x28e18
|
||||
#define CB_COLOR8_ATTRIB 0x28e54
|
||||
#define CB_COLOR9_ATTRIB 0x28e70
|
||||
#define CB_COLOR10_ATTRIB 0x28e8c
|
||||
#define CB_COLOR11_ATTRIB 0x28ea8
|
||||
|
||||
#define CB_COLOR1_DIM 0x28cb4
|
||||
#define CB_COLOR2_DIM 0x28cf0
|
||||
#define CB_COLOR3_DIM 0x28d2c
|
||||
#define CB_COLOR4_DIM 0x28d68
|
||||
#define CB_COLOR5_DIM 0x28da4
|
||||
#define CB_COLOR6_DIM 0x28de0
|
||||
#define CB_COLOR7_DIM 0x28e1c
|
||||
#define CB_COLOR8_DIM 0x28e58
|
||||
#define CB_COLOR9_DIM 0x28e74
|
||||
#define CB_COLOR10_DIM 0x28e90
|
||||
#define CB_COLOR11_DIM 0x28eac
|
||||
|
||||
#define CB_COLOR1_CMASK 0x28cb8
|
||||
#define CB_COLOR2_CMASK 0x28cf4
|
||||
#define CB_COLOR3_CMASK 0x28d30
|
||||
#define CB_COLOR4_CMASK 0x28d6c
|
||||
#define CB_COLOR5_CMASK 0x28da8
|
||||
#define CB_COLOR6_CMASK 0x28de4
|
||||
#define CB_COLOR7_CMASK 0x28e20
|
||||
|
||||
#define CB_COLOR1_CMASK_SLICE 0x28cbc
|
||||
#define CB_COLOR2_CMASK_SLICE 0x28cf8
|
||||
#define CB_COLOR3_CMASK_SLICE 0x28d34
|
||||
#define CB_COLOR4_CMASK_SLICE 0x28d70
|
||||
#define CB_COLOR5_CMASK_SLICE 0x28dac
|
||||
#define CB_COLOR6_CMASK_SLICE 0x28de8
|
||||
#define CB_COLOR7_CMASK_SLICE 0x28e24
|
||||
|
||||
#define CB_COLOR1_FMASK 0x28cc0
|
||||
#define CB_COLOR2_FMASK 0x28cfc
|
||||
#define CB_COLOR3_FMASK 0x28d38
|
||||
#define CB_COLOR4_FMASK 0x28d74
|
||||
#define CB_COLOR5_FMASK 0x28db0
|
||||
#define CB_COLOR6_FMASK 0x28dec
|
||||
#define CB_COLOR7_FMASK 0x28e28
|
||||
|
||||
#define CB_COLOR1_FMASK_SLICE 0x28cc4
|
||||
#define CB_COLOR2_FMASK_SLICE 0x28d00
|
||||
#define CB_COLOR3_FMASK_SLICE 0x28d3c
|
||||
#define CB_COLOR4_FMASK_SLICE 0x28d78
|
||||
#define CB_COLOR5_FMASK_SLICE 0x28db4
|
||||
#define CB_COLOR6_FMASK_SLICE 0x28df0
|
||||
#define CB_COLOR7_FMASK_SLICE 0x28e2c
|
||||
|
||||
#define CB_COLOR1_CLEAR_WORD0 0x28cc8
|
||||
#define CB_COLOR2_CLEAR_WORD0 0x28d04
|
||||
#define CB_COLOR3_CLEAR_WORD0 0x28d40
|
||||
#define CB_COLOR4_CLEAR_WORD0 0x28d7c
|
||||
#define CB_COLOR5_CLEAR_WORD0 0x28db8
|
||||
#define CB_COLOR6_CLEAR_WORD0 0x28df4
|
||||
#define CB_COLOR7_CLEAR_WORD0 0x28e30
|
||||
|
||||
#define CB_COLOR1_CLEAR_WORD1 0x28ccc
|
||||
#define CB_COLOR2_CLEAR_WORD1 0x28d08
|
||||
#define CB_COLOR3_CLEAR_WORD1 0x28d44
|
||||
#define CB_COLOR4_CLEAR_WORD1 0x28d80
|
||||
#define CB_COLOR5_CLEAR_WORD1 0x28dbc
|
||||
#define CB_COLOR6_CLEAR_WORD1 0x28df8
|
||||
#define CB_COLOR7_CLEAR_WORD1 0x28e34
|
||||
|
||||
#define CB_COLOR1_CLEAR_WORD2 0x28cd0
|
||||
#define CB_COLOR2_CLEAR_WORD2 0x28d0c
|
||||
#define CB_COLOR3_CLEAR_WORD2 0x28d48
|
||||
#define CB_COLOR4_CLEAR_WORD2 0x28d84
|
||||
#define CB_COLOR5_CLEAR_WORD2 0x28dc0
|
||||
#define CB_COLOR6_CLEAR_WORD2 0x28dfc
|
||||
#define CB_COLOR7_CLEAR_WORD2 0x28e38
|
||||
|
||||
#define CB_COLOR1_CLEAR_WORD3 0x28cd4
|
||||
#define CB_COLOR2_CLEAR_WORD3 0x28d10
|
||||
#define CB_COLOR3_CLEAR_WORD3 0x28d4c
|
||||
#define CB_COLOR4_CLEAR_WORD3 0x28d88
|
||||
#define CB_COLOR5_CLEAR_WORD3 0x28dc4
|
||||
#define CB_COLOR6_CLEAR_WORD3 0x28e00
|
||||
#define CB_COLOR7_CLEAR_WORD3 0x28e3c
|
||||
|
||||
#define SQ_TEX_RESOURCE_WORD0_0 0x30000
|
||||
#define SQ_TEX_RESOURCE_WORD1_0 0x30004
|
||||
# define TEX_ARRAY_MODE(x) ((x) << 28)
|
||||
#define SQ_TEX_RESOURCE_WORD2_0 0x30008
|
||||
#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
|
||||
#define SQ_TEX_RESOURCE_WORD4_0 0x30010
|
||||
#define SQ_TEX_RESOURCE_WORD5_0 0x30014
|
||||
#define SQ_TEX_RESOURCE_WORD6_0 0x30018
|
||||
#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -724,8 +724,8 @@ static struct radeon_asic evergreen_asic = {
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
.fence_ring_emit = NULL,
|
||||
.cs_parse = NULL,
|
||||
.fence_ring_emit = &r600_fence_ring_emit,
|
||||
.cs_parse = &evergreen_cs_parse,
|
||||
.copy_blit = NULL,
|
||||
.copy_dma = NULL,
|
||||
.copy = NULL,
|
||||
|
||||
@ -314,6 +314,7 @@ void evergreen_hpd_set_polarity(struct radeon_device *rdev,
|
||||
u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
|
||||
int evergreen_irq_set(struct radeon_device *rdev);
|
||||
int evergreen_irq_process(struct radeon_device *rdev);
|
||||
extern int evergreen_cs_parse(struct radeon_cs_parser *p);
|
||||
extern void evergreen_pm_misc(struct radeon_device *rdev);
|
||||
extern void evergreen_pm_prepare(struct radeon_device *rdev);
|
||||
extern void evergreen_pm_finish(struct radeon_device *rdev);
|
||||
|
||||
611
drivers/gpu/drm/radeon/reg_srcs/evergreen
Normal file
611
drivers/gpu/drm/radeon/reg_srcs/evergreen
Normal file
@ -0,0 +1,611 @@
|
||||
evergreen 0x9400
|
||||
0x00008040 WAIT_UNTIL
|
||||
0x00008044 WAIT_UNTIL_POLL_CNTL
|
||||
0x00008048 WAIT_UNTIL_POLL_MASK
|
||||
0x0000804c WAIT_UNTIL_POLL_REFDATA
|
||||
0x000088B0 VGT_VTX_VECT_EJECT_REG
|
||||
0x000088C4 VGT_CACHE_INVALIDATION
|
||||
0x000088D4 VGT_GS_VERTEX_REUSE
|
||||
0x00008958 VGT_PRIMITIVE_TYPE
|
||||
0x0000895C VGT_INDEX_TYPE
|
||||
0x00008970 VGT_NUM_INDICES
|
||||
0x00008974 VGT_NUM_INSTANCES
|
||||
0x00008990 VGT_COMPUTE_DIM_X
|
||||
0x00008994 VGT_COMPUTE_DIM_Y
|
||||
0x00008998 VGT_COMPUTE_DIM_Z
|
||||
0x0000899C VGT_COMPUTE_START_X
|
||||
0x000089A0 VGT_COMPUTE_START_Y
|
||||
0x000089A4 VGT_COMPUTE_START_Z
|
||||
0x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE
|
||||
0x00008A14 PA_CL_ENHANCE
|
||||
0x00008A60 PA_SC_LINE_STIPPLE_VALUE
|
||||
0x00008B10 PA_SC_LINE_STIPPLE_STATE
|
||||
0x00008BF0 PA_SC_ENHANCE
|
||||
0x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
|
||||
0x00008C00 SQ_CONFIG
|
||||
0x00008C04 SQ_GPR_RESOURCE_MGMT_1
|
||||
0x00008C08 SQ_GPR_RESOURCE_MGMT_2
|
||||
0x00008C0C SQ_GPR_RESOURCE_MGMT_3
|
||||
0x00008C10 SQ_GLOBAL_GPR_RESOURCE_MGMT_1
|
||||
0x00008C14 SQ_GLOBAL_GPR_RESOURCE_MGMT_2
|
||||
0x00008C18 SQ_THREAD_RESOURCE_MGMT
|
||||
0x00008C1C SQ_THREAD_RESOURCE_MGMT_2
|
||||
0x00008C20 SQ_STACK_RESOURCE_MGMT_1
|
||||
0x00008C24 SQ_STACK_RESOURCE_MGMT_2
|
||||
0x00008C28 SQ_STACK_RESOURCE_MGMT_3
|
||||
0x00008DF8 SQ_CONST_MEM_BASE
|
||||
0x00008E48 SQ_EX_ALLOC_TABLE_SLOTS
|
||||
0x00009100 SPI_CONFIG_CNTL
|
||||
0x0000913C SPI_CONFIG_CNTL_1
|
||||
0x00009700 VC_CNTL
|
||||
0x00009714 VC_ENHANCE
|
||||
0x00009830 DB_DEBUG
|
||||
0x00009834 DB_DEBUG2
|
||||
0x00009838 DB_DEBUG3
|
||||
0x0000983C DB_DEBUG4
|
||||
0x00009854 DB_WATERMARKS
|
||||
0x0000A400 TD_PS_BORDER_COLOR_INDEX
|
||||
0x0000A404 TD_PS_BORDER_COLOR_RED
|
||||
0x0000A408 TD_PS_BORDER_COLOR_GREEN
|
||||
0x0000A40C TD_PS_BORDER_COLOR_BLUE
|
||||
0x0000A410 TD_PS_BORDER_COLOR_ALPHA
|
||||
0x0000A414 TD_VS_BORDER_COLOR_INDEX
|
||||
0x0000A418 TD_VS_BORDER_COLOR_RED
|
||||
0x0000A41C TD_VS_BORDER_COLOR_GREEN
|
||||
0x0000A420 TD_VS_BORDER_COLOR_BLUE
|
||||
0x0000A424 TD_VS_BORDER_COLOR_ALPHA
|
||||
0x0000A428 TD_GS_BORDER_COLOR_INDEX
|
||||
0x0000A42C TD_GS_BORDER_COLOR_RED
|
||||
0x0000A430 TD_GS_BORDER_COLOR_GREEN
|
||||
0x0000A434 TD_GS_BORDER_COLOR_BLUE
|
||||
0x0000A438 TD_GS_BORDER_COLOR_ALPHA
|
||||
0x0000A43C TD_HS_BORDER_COLOR_INDEX
|
||||
0x0000A440 TD_HS_BORDER_COLOR_RED
|
||||
0x0000A444 TD_HS_BORDER_COLOR_GREEN
|
||||
0x0000A448 TD_HS_BORDER_COLOR_BLUE
|
||||
0x0000A44C TD_HS_BORDER_COLOR_ALPHA
|
||||
0x0000A450 TD_LS_BORDER_COLOR_INDEX
|
||||
0x0000A454 TD_LS_BORDER_COLOR_RED
|
||||
0x0000A458 TD_LS_BORDER_COLOR_GREEN
|
||||
0x0000A45C TD_LS_BORDER_COLOR_BLUE
|
||||
0x0000A460 TD_LS_BORDER_COLOR_ALPHA
|
||||
0x0000A464 TD_CS_BORDER_COLOR_INDEX
|
||||
0x0000A468 TD_CS_BORDER_COLOR_RED
|
||||
0x0000A46C TD_CS_BORDER_COLOR_GREEN
|
||||
0x0000A470 TD_CS_BORDER_COLOR_BLUE
|
||||
0x0000A474 TD_CS_BORDER_COLOR_ALPHA
|
||||
0x00028000 DB_RENDER_CONTROL
|
||||
0x00028004 DB_COUNT_CONTROL
|
||||
0x0002800C DB_RENDER_OVERRIDE
|
||||
0x00028010 DB_RENDER_OVERRIDE2
|
||||
0x00028028 DB_STENCIL_CLEAR
|
||||
0x0002802C DB_DEPTH_CLEAR
|
||||
0x00028034 PA_SC_SCREEN_SCISSOR_BR
|
||||
0x00028030 PA_SC_SCREEN_SCISSOR_TL
|
||||
0x0002805C DB_DEPTH_SLICE
|
||||
0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
|
||||
0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
|
||||
0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
|
||||
0x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3
|
||||
0x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4
|
||||
0x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5
|
||||
0x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6
|
||||
0x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7
|
||||
0x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8
|
||||
0x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9
|
||||
0x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10
|
||||
0x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11
|
||||
0x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12
|
||||
0x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13
|
||||
0x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14
|
||||
0x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15
|
||||
0x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0
|
||||
0x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1
|
||||
0x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2
|
||||
0x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3
|
||||
0x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4
|
||||
0x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5
|
||||
0x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6
|
||||
0x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7
|
||||
0x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8
|
||||
0x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9
|
||||
0x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10
|
||||
0x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11
|
||||
0x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12
|
||||
0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
|
||||
0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
|
||||
0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
|
||||
0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
|
||||
0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
|
||||
0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
|
||||
0x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3
|
||||
0x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4
|
||||
0x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5
|
||||
0x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6
|
||||
0x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7
|
||||
0x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8
|
||||
0x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9
|
||||
0x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10
|
||||
0x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11
|
||||
0x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12
|
||||
0x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13
|
||||
0x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14
|
||||
0x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15
|
||||
0x00028200 PA_SC_WINDOW_OFFSET
|
||||
0x00028204 PA_SC_WINDOW_SCISSOR_TL
|
||||
0x00028208 PA_SC_WINDOW_SCISSOR_BR
|
||||
0x0002820C PA_SC_CLIPRECT_RULE
|
||||
0x00028210 PA_SC_CLIPRECT_0_TL
|
||||
0x00028214 PA_SC_CLIPRECT_0_BR
|
||||
0x00028218 PA_SC_CLIPRECT_1_TL
|
||||
0x0002821C PA_SC_CLIPRECT_1_BR
|
||||
0x00028220 PA_SC_CLIPRECT_2_TL
|
||||
0x00028224 PA_SC_CLIPRECT_2_BR
|
||||
0x00028228 PA_SC_CLIPRECT_3_TL
|
||||
0x0002822C PA_SC_CLIPRECT_3_BR
|
||||
0x00028230 PA_SC_EDGERULE
|
||||
0x00028234 PA_SU_HARDWARE_SCREEN_OFFSET
|
||||
0x00028240 PA_SC_GENERIC_SCISSOR_TL
|
||||
0x00028244 PA_SC_GENERIC_SCISSOR_BR
|
||||
0x00028250 PA_SC_VPORT_SCISSOR_0_TL
|
||||
0x00028254 PA_SC_VPORT_SCISSOR_0_BR
|
||||
0x00028258 PA_SC_VPORT_SCISSOR_1_TL
|
||||
0x0002825C PA_SC_VPORT_SCISSOR_1_BR
|
||||
0x00028260 PA_SC_VPORT_SCISSOR_2_TL
|
||||
0x00028264 PA_SC_VPORT_SCISSOR_2_BR
|
||||
0x00028268 PA_SC_VPORT_SCISSOR_3_TL
|
||||
0x0002826C PA_SC_VPORT_SCISSOR_3_BR
|
||||
0x00028270 PA_SC_VPORT_SCISSOR_4_TL
|
||||
0x00028274 PA_SC_VPORT_SCISSOR_4_BR
|
||||
0x00028278 PA_SC_VPORT_SCISSOR_5_TL
|
||||
0x0002827C PA_SC_VPORT_SCISSOR_5_BR
|
||||
0x00028280 PA_SC_VPORT_SCISSOR_6_TL
|
||||
0x00028284 PA_SC_VPORT_SCISSOR_6_BR
|
||||
0x00028288 PA_SC_VPORT_SCISSOR_7_TL
|
||||
0x0002828C PA_SC_VPORT_SCISSOR_7_BR
|
||||
0x00028290 PA_SC_VPORT_SCISSOR_8_TL
|
||||
0x00028294 PA_SC_VPORT_SCISSOR_8_BR
|
||||
0x00028298 PA_SC_VPORT_SCISSOR_9_TL
|
||||
0x0002829C PA_SC_VPORT_SCISSOR_9_BR
|
||||
0x000282A0 PA_SC_VPORT_SCISSOR_10_TL
|
||||
0x000282A4 PA_SC_VPORT_SCISSOR_10_BR
|
||||
0x000282A8 PA_SC_VPORT_SCISSOR_11_TL
|
||||
0x000282AC PA_SC_VPORT_SCISSOR_11_BR
|
||||
0x000282B0 PA_SC_VPORT_SCISSOR_12_TL
|
||||
0x000282B4 PA_SC_VPORT_SCISSOR_12_BR
|
||||
0x000282B8 PA_SC_VPORT_SCISSOR_13_TL
|
||||
0x000282BC PA_SC_VPORT_SCISSOR_13_BR
|
||||
0x000282C0 PA_SC_VPORT_SCISSOR_14_TL
|
||||
0x000282C4 PA_SC_VPORT_SCISSOR_14_BR
|
||||
0x000282C8 PA_SC_VPORT_SCISSOR_15_TL
|
||||
0x000282CC PA_SC_VPORT_SCISSOR_15_BR
|
||||
0x000282D0 PA_SC_VPORT_ZMIN_0
|
||||
0x000282D4 PA_SC_VPORT_ZMAX_0
|
||||
0x000282D8 PA_SC_VPORT_ZMIN_1
|
||||
0x000282DC PA_SC_VPORT_ZMAX_1
|
||||
0x000282E0 PA_SC_VPORT_ZMIN_2
|
||||
0x000282E4 PA_SC_VPORT_ZMAX_2
|
||||
0x000282E8 PA_SC_VPORT_ZMIN_3
|
||||
0x000282EC PA_SC_VPORT_ZMAX_3
|
||||
0x000282F0 PA_SC_VPORT_ZMIN_4
|
||||
0x000282F4 PA_SC_VPORT_ZMAX_4
|
||||
0x000282F8 PA_SC_VPORT_ZMIN_5
|
||||
0x000282FC PA_SC_VPORT_ZMAX_5
|
||||
0x00028300 PA_SC_VPORT_ZMIN_6
|
||||
0x00028304 PA_SC_VPORT_ZMAX_6
|
||||
0x00028308 PA_SC_VPORT_ZMIN_7
|
||||
0x0002830C PA_SC_VPORT_ZMAX_7
|
||||
0x00028310 PA_SC_VPORT_ZMIN_8
|
||||
0x00028314 PA_SC_VPORT_ZMAX_8
|
||||
0x00028318 PA_SC_VPORT_ZMIN_9
|
||||
0x0002831C PA_SC_VPORT_ZMAX_9
|
||||
0x00028320 PA_SC_VPORT_ZMIN_10
|
||||
0x00028324 PA_SC_VPORT_ZMAX_10
|
||||
0x00028328 PA_SC_VPORT_ZMIN_11
|
||||
0x0002832C PA_SC_VPORT_ZMAX_11
|
||||
0x00028330 PA_SC_VPORT_ZMIN_12
|
||||
0x00028334 PA_SC_VPORT_ZMAX_12
|
||||
0x00028338 PA_SC_VPORT_ZMIN_13
|
||||
0x0002833C PA_SC_VPORT_ZMAX_13
|
||||
0x00028340 PA_SC_VPORT_ZMIN_14
|
||||
0x00028344 PA_SC_VPORT_ZMAX_14
|
||||
0x00028348 PA_SC_VPORT_ZMIN_15
|
||||
0x0002834C PA_SC_VPORT_ZMAX_15
|
||||
0x00028350 SX_MISC
|
||||
0x00028380 SQ_VTX_SEMANTIC_0
|
||||
0x00028384 SQ_VTX_SEMANTIC_1
|
||||
0x00028388 SQ_VTX_SEMANTIC_2
|
||||
0x0002838C SQ_VTX_SEMANTIC_3
|
||||
0x00028390 SQ_VTX_SEMANTIC_4
|
||||
0x00028394 SQ_VTX_SEMANTIC_5
|
||||
0x00028398 SQ_VTX_SEMANTIC_6
|
||||
0x0002839C SQ_VTX_SEMANTIC_7
|
||||
0x000283A0 SQ_VTX_SEMANTIC_8
|
||||
0x000283A4 SQ_VTX_SEMANTIC_9
|
||||
0x000283A8 SQ_VTX_SEMANTIC_10
|
||||
0x000283AC SQ_VTX_SEMANTIC_11
|
||||
0x000283B0 SQ_VTX_SEMANTIC_12
|
||||
0x000283B4 SQ_VTX_SEMANTIC_13
|
||||
0x000283B8 SQ_VTX_SEMANTIC_14
|
||||
0x000283BC SQ_VTX_SEMANTIC_15
|
||||
0x000283C0 SQ_VTX_SEMANTIC_16
|
||||
0x000283C4 SQ_VTX_SEMANTIC_17
|
||||
0x000283C8 SQ_VTX_SEMANTIC_18
|
||||
0x000283CC SQ_VTX_SEMANTIC_19
|
||||
0x000283D0 SQ_VTX_SEMANTIC_20
|
||||
0x000283D4 SQ_VTX_SEMANTIC_21
|
||||
0x000283D8 SQ_VTX_SEMANTIC_22
|
||||
0x000283DC SQ_VTX_SEMANTIC_23
|
||||
0x000283E0 SQ_VTX_SEMANTIC_24
|
||||
0x000283E4 SQ_VTX_SEMANTIC_25
|
||||
0x000283E8 SQ_VTX_SEMANTIC_26
|
||||
0x000283EC SQ_VTX_SEMANTIC_27
|
||||
0x000283F0 SQ_VTX_SEMANTIC_28
|
||||
0x000283F4 SQ_VTX_SEMANTIC_29
|
||||
0x000283F8 SQ_VTX_SEMANTIC_30
|
||||
0x000283FC SQ_VTX_SEMANTIC_31
|
||||
0x00028400 VGT_MAX_VTX_INDX
|
||||
0x00028404 VGT_MIN_VTX_INDX
|
||||
0x00028408 VGT_INDX_OFFSET
|
||||
0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
|
||||
0x00028410 SX_ALPHA_TEST_CONTROL
|
||||
0x00028414 CB_BLEND_RED
|
||||
0x00028418 CB_BLEND_GREEN
|
||||
0x0002841C CB_BLEND_BLUE
|
||||
0x00028420 CB_BLEND_ALPHA
|
||||
0x00028430 DB_STENCILREFMASK
|
||||
0x00028434 DB_STENCILREFMASK_BF
|
||||
0x00028438 SX_ALPHA_REF
|
||||
0x0002843C PA_CL_VPORT_XSCALE_0
|
||||
0x00028440 PA_CL_VPORT_XOFFSET_0
|
||||
0x00028444 PA_CL_VPORT_YSCALE_0
|
||||
0x00028448 PA_CL_VPORT_YOFFSET_0
|
||||
0x0002844C PA_CL_VPORT_ZSCALE_0
|
||||
0x00028450 PA_CL_VPORT_ZOFFSET_0
|
||||
0x00028454 PA_CL_VPORT_XSCALE_1
|
||||
0x00028458 PA_CL_VPORT_XOFFSET_1
|
||||
0x0002845C PA_CL_VPORT_YSCALE_1
|
||||
0x00028460 PA_CL_VPORT_YOFFSET_1
|
||||
0x00028464 PA_CL_VPORT_ZSCALE_1
|
||||
0x00028468 PA_CL_VPORT_ZOFFSET_1
|
||||
0x0002846C PA_CL_VPORT_XSCALE_2
|
||||
0x00028470 PA_CL_VPORT_XOFFSET_2
|
||||
0x00028474 PA_CL_VPORT_YSCALE_2
|
||||
0x00028478 PA_CL_VPORT_YOFFSET_2
|
||||
0x0002847C PA_CL_VPORT_ZSCALE_2
|
||||
0x00028480 PA_CL_VPORT_ZOFFSET_2
|
||||
0x00028484 PA_CL_VPORT_XSCALE_3
|
||||
0x00028488 PA_CL_VPORT_XOFFSET_3
|
||||
0x0002848C PA_CL_VPORT_YSCALE_3
|
||||
0x00028490 PA_CL_VPORT_YOFFSET_3
|
||||
0x00028494 PA_CL_VPORT_ZSCALE_3
|
||||
0x00028498 PA_CL_VPORT_ZOFFSET_3
|
||||
0x0002849C PA_CL_VPORT_XSCALE_4
|
||||
0x000284A0 PA_CL_VPORT_XOFFSET_4
|
||||
0x000284A4 PA_CL_VPORT_YSCALE_4
|
||||
0x000284A8 PA_CL_VPORT_YOFFSET_4
|
||||
0x000284AC PA_CL_VPORT_ZSCALE_4
|
||||
0x000284B0 PA_CL_VPORT_ZOFFSET_4
|
||||
0x000284B4 PA_CL_VPORT_XSCALE_5
|
||||
0x000284B8 PA_CL_VPORT_XOFFSET_5
|
||||
0x000284BC PA_CL_VPORT_YSCALE_5
|
||||
0x000284C0 PA_CL_VPORT_YOFFSET_5
|
||||
0x000284C4 PA_CL_VPORT_ZSCALE_5
|
||||
0x000284C8 PA_CL_VPORT_ZOFFSET_5
|
||||
0x000284CC PA_CL_VPORT_XSCALE_6
|
||||
0x000284D0 PA_CL_VPORT_XOFFSET_6
|
||||
0x000284D4 PA_CL_VPORT_YSCALE_6
|
||||
0x000284D8 PA_CL_VPORT_YOFFSET_6
|
||||
0x000284DC PA_CL_VPORT_ZSCALE_6
|
||||
0x000284E0 PA_CL_VPORT_ZOFFSET_6
|
||||
0x000284E4 PA_CL_VPORT_XSCALE_7
|
||||
0x000284E8 PA_CL_VPORT_XOFFSET_7
|
||||
0x000284EC PA_CL_VPORT_YSCALE_7
|
||||
0x000284F0 PA_CL_VPORT_YOFFSET_7
|
||||
0x000284F4 PA_CL_VPORT_ZSCALE_7
|
||||
0x000284F8 PA_CL_VPORT_ZOFFSET_7
|
||||
0x000284FC PA_CL_VPORT_XSCALE_8
|
||||
0x00028500 PA_CL_VPORT_XOFFSET_8
|
||||
0x00028504 PA_CL_VPORT_YSCALE_8
|
||||
0x00028508 PA_CL_VPORT_YOFFSET_8
|
||||
0x0002850C PA_CL_VPORT_ZSCALE_8
|
||||
0x00028510 PA_CL_VPORT_ZOFFSET_8
|
||||
0x00028514 PA_CL_VPORT_XSCALE_9
|
||||
0x00028518 PA_CL_VPORT_XOFFSET_9
|
||||
0x0002851C PA_CL_VPORT_YSCALE_9
|
||||
0x00028520 PA_CL_VPORT_YOFFSET_9
|
||||
0x00028524 PA_CL_VPORT_ZSCALE_9
|
||||
0x00028528 PA_CL_VPORT_ZOFFSET_9
|
||||
0x0002852C PA_CL_VPORT_XSCALE_10
|
||||
0x00028530 PA_CL_VPORT_XOFFSET_10
|
||||
0x00028534 PA_CL_VPORT_YSCALE_10
|
||||
0x00028538 PA_CL_VPORT_YOFFSET_10
|
||||
0x0002853C PA_CL_VPORT_ZSCALE_10
|
||||
0x00028540 PA_CL_VPORT_ZOFFSET_10
|
||||
0x00028544 PA_CL_VPORT_XSCALE_11
|
||||
0x00028548 PA_CL_VPORT_XOFFSET_11
|
||||
0x0002854C PA_CL_VPORT_YSCALE_11
|
||||
0x00028550 PA_CL_VPORT_YOFFSET_11
|
||||
0x00028554 PA_CL_VPORT_ZSCALE_11
|
||||
0x00028558 PA_CL_VPORT_ZOFFSET_11
|
||||
0x0002855C PA_CL_VPORT_XSCALE_12
|
||||
0x00028560 PA_CL_VPORT_XOFFSET_12
|
||||
0x00028564 PA_CL_VPORT_YSCALE_12
|
||||
0x00028568 PA_CL_VPORT_YOFFSET_12
|
||||
0x0002856C PA_CL_VPORT_ZSCALE_12
|
||||
0x00028570 PA_CL_VPORT_ZOFFSET_12
|
||||
0x00028574 PA_CL_VPORT_XSCALE_13
|
||||
0x00028578 PA_CL_VPORT_XOFFSET_13
|
||||
0x0002857C PA_CL_VPORT_YSCALE_13
|
||||
0x00028580 PA_CL_VPORT_YOFFSET_13
|
||||
0x00028584 PA_CL_VPORT_ZSCALE_13
|
||||
0x00028588 PA_CL_VPORT_ZOFFSET_13
|
||||
0x0002858C PA_CL_VPORT_XSCALE_14
|
||||
0x00028590 PA_CL_VPORT_XOFFSET_14
|
||||
0x00028594 PA_CL_VPORT_YSCALE_14
|
||||
0x00028598 PA_CL_VPORT_YOFFSET_14
|
||||
0x0002859C PA_CL_VPORT_ZSCALE_14
|
||||
0x000285A0 PA_CL_VPORT_ZOFFSET_14
|
||||
0x000285A4 PA_CL_VPORT_XSCALE_15
|
||||
0x000285A8 PA_CL_VPORT_XOFFSET_15
|
||||
0x000285AC PA_CL_VPORT_YSCALE_15
|
||||
0x000285B0 PA_CL_VPORT_YOFFSET_15
|
||||
0x000285B4 PA_CL_VPORT_ZSCALE_15
|
||||
0x000285B8 PA_CL_VPORT_ZOFFSET_15
|
||||
0x000285BC PA_CL_UCP_0_X
|
||||
0x000285C0 PA_CL_UCP_0_Y
|
||||
0x000285C4 PA_CL_UCP_0_Z
|
||||
0x000285C8 PA_CL_UCP_0_W
|
||||
0x000285CC PA_CL_UCP_1_X
|
||||
0x000285D0 PA_CL_UCP_1_Y
|
||||
0x000285D4 PA_CL_UCP_1_Z
|
||||
0x000285D8 PA_CL_UCP_1_W
|
||||
0x000285DC PA_CL_UCP_2_X
|
||||
0x000285E0 PA_CL_UCP_2_Y
|
||||
0x000285E4 PA_CL_UCP_2_Z
|
||||
0x000285E8 PA_CL_UCP_2_W
|
||||
0x000285EC PA_CL_UCP_3_X
|
||||
0x000285F0 PA_CL_UCP_3_Y
|
||||
0x000285F4 PA_CL_UCP_3_Z
|
||||
0x000285F8 PA_CL_UCP_3_W
|
||||
0x000285FC PA_CL_UCP_4_X
|
||||
0x00028600 PA_CL_UCP_4_Y
|
||||
0x00028604 PA_CL_UCP_4_Z
|
||||
0x00028608 PA_CL_UCP_4_W
|
||||
0x0002860C PA_CL_UCP_5_X
|
||||
0x00028610 PA_CL_UCP_5_Y
|
||||
0x00028614 PA_CL_UCP_5_Z
|
||||
0x00028618 PA_CL_UCP_5_W
|
||||
0x0002861C SPI_VS_OUT_ID_0
|
||||
0x00028620 SPI_VS_OUT_ID_1
|
||||
0x00028624 SPI_VS_OUT_ID_2
|
||||
0x00028628 SPI_VS_OUT_ID_3
|
||||
0x0002862C SPI_VS_OUT_ID_4
|
||||
0x00028630 SPI_VS_OUT_ID_5
|
||||
0x00028634 SPI_VS_OUT_ID_6
|
||||
0x00028638 SPI_VS_OUT_ID_7
|
||||
0x0002863C SPI_VS_OUT_ID_8
|
||||
0x00028640 SPI_VS_OUT_ID_9
|
||||
0x00028644 SPI_PS_INPUT_CNTL_0
|
||||
0x00028648 SPI_PS_INPUT_CNTL_1
|
||||
0x0002864C SPI_PS_INPUT_CNTL_2
|
||||
0x00028650 SPI_PS_INPUT_CNTL_3
|
||||
0x00028654 SPI_PS_INPUT_CNTL_4
|
||||
0x00028658 SPI_PS_INPUT_CNTL_5
|
||||
0x0002865C SPI_PS_INPUT_CNTL_6
|
||||
0x00028660 SPI_PS_INPUT_CNTL_7
|
||||
0x00028664 SPI_PS_INPUT_CNTL_8
|
||||
0x00028668 SPI_PS_INPUT_CNTL_9
|
||||
0x0002866C SPI_PS_INPUT_CNTL_10
|
||||
0x00028670 SPI_PS_INPUT_CNTL_11
|
||||
0x00028674 SPI_PS_INPUT_CNTL_12
|
||||
0x00028678 SPI_PS_INPUT_CNTL_13
|
||||
0x0002867C SPI_PS_INPUT_CNTL_14
|
||||
0x00028680 SPI_PS_INPUT_CNTL_15
|
||||
0x00028684 SPI_PS_INPUT_CNTL_16
|
||||
0x00028688 SPI_PS_INPUT_CNTL_17
|
||||
0x0002868C SPI_PS_INPUT_CNTL_18
|
||||
0x00028690 SPI_PS_INPUT_CNTL_19
|
||||
0x00028694 SPI_PS_INPUT_CNTL_20
|
||||
0x00028698 SPI_PS_INPUT_CNTL_21
|
||||
0x0002869C SPI_PS_INPUT_CNTL_22
|
||||
0x000286A0 SPI_PS_INPUT_CNTL_23
|
||||
0x000286A4 SPI_PS_INPUT_CNTL_24
|
||||
0x000286A8 SPI_PS_INPUT_CNTL_25
|
||||
0x000286AC SPI_PS_INPUT_CNTL_26
|
||||
0x000286B0 SPI_PS_INPUT_CNTL_27
|
||||
0x000286B4 SPI_PS_INPUT_CNTL_28
|
||||
0x000286B8 SPI_PS_INPUT_CNTL_29
|
||||
0x000286BC SPI_PS_INPUT_CNTL_30
|
||||
0x000286C0 SPI_PS_INPUT_CNTL_31
|
||||
0x000286C4 SPI_VS_OUT_CONFIG
|
||||
0x000286C8 SPI_THREAD_GROUPING
|
||||
0x000286CC SPI_PS_IN_CONTROL_0
|
||||
0x000286D0 SPI_PS_IN_CONTROL_1
|
||||
0x000286D4 SPI_INTERP_CONTROL_0
|
||||
0x000286D8 SPI_INPUT_Z
|
||||
0x000286DC SPI_FOG_CNTL
|
||||
0x000286E0 SPI_BARYC_CNTL
|
||||
0x000286E4 SPI_PS_IN_CONTROL_2
|
||||
0x000286E8 SPI_COMPUTE_INPUT_CNTL
|
||||
0x000286EC SPI_COMPUTE_NUM_THREAD_X
|
||||
0x000286F0 SPI_COMPUTE_NUM_THREAD_Y
|
||||
0x000286F4 SPI_COMPUTE_NUM_THREAD_Z
|
||||
0x000286F8 GDS_ADDR_SIZE
|
||||
0x00028780 CB_BLEND0_CONTROL
|
||||
0x00028784 CB_BLEND1_CONTROL
|
||||
0x00028788 CB_BLEND2_CONTROL
|
||||
0x0002878C CB_BLEND3_CONTROL
|
||||
0x00028790 CB_BLEND4_CONTROL
|
||||
0x00028794 CB_BLEND5_CONTROL
|
||||
0x00028798 CB_BLEND6_CONTROL
|
||||
0x0002879C CB_BLEND7_CONTROL
|
||||
0x000287CC CS_COPY_STATE
|
||||
0x000287D0 GFX_COPY_STATE
|
||||
0x000287D4 PA_CL_POINT_X_RAD
|
||||
0x000287D8 PA_CL_POINT_Y_RAD
|
||||
0x000287DC PA_CL_POINT_SIZE
|
||||
0x000287E0 PA_CL_POINT_CULL_RAD
|
||||
0x00028808 CB_COLOR_CONTROL
|
||||
0x0002880C DB_SHADER_CONTROL
|
||||
0x00028810 PA_CL_CLIP_CNTL
|
||||
0x00028814 PA_SU_SC_MODE_CNTL
|
||||
0x00028818 PA_CL_VTE_CNTL
|
||||
0x0002881C PA_CL_VS_OUT_CNTL
|
||||
0x00028820 PA_CL_NANINF_CNTL
|
||||
0x00028824 PA_SU_LINE_STIPPLE_CNTL
|
||||
0x00028828 PA_SU_LINE_STIPPLE_SCALE
|
||||
0x0002882C PA_SU_PRIM_FILTER_CNTL
|
||||
0x00028838 SQ_DYN_GPR_RESOURCE_LIMIT_1
|
||||
0x00028844 SQ_PGM_RESOURCES_PS
|
||||
0x00028848 SQ_PGM_RESOURCES_2_PS
|
||||
0x0002884C SQ_PGM_EXPORTS_PS
|
||||
0x0002885C SQ_PGM_RESOURCES_VS
|
||||
0x00028860 SQ_PGM_RESOURCES_2_VS
|
||||
0x00028878 SQ_PGM_RESOURCES_GS
|
||||
0x0002887C SQ_PGM_RESOURCES_2_GS
|
||||
0x00028890 SQ_PGM_RESOURCES_ES
|
||||
0x00028894 SQ_PGM_RESOURCES_2_ES
|
||||
0x000288A8 SQ_PGM_RESOURCES_FS
|
||||
0x000288BC SQ_PGM_RESOURCES_HS
|
||||
0x000288C0 SQ_PGM_RESOURCES_2_HS
|
||||
0x000288D0 SQ_PGM_RESOURCES_LS
|
||||
0x000288D4 SQ_PGM_RESOURCES_2_LS
|
||||
0x000288E8 SQ_LDS_ALLOC
|
||||
0x000288EC SQ_LDS_ALLOC_PS
|
||||
0x000288F0 SQ_VTX_SEMANTIC_CLEAR
|
||||
0x00028A00 PA_SU_POINT_SIZE
|
||||
0x00028A04 PA_SU_POINT_MINMAX
|
||||
0x00028A08 PA_SU_LINE_CNTL
|
||||
0x00028A0C PA_SC_LINE_STIPPLE
|
||||
0x00028A10 VGT_OUTPUT_PATH_CNTL
|
||||
0x00028A14 VGT_HOS_CNTL
|
||||
0x00028A18 VGT_HOS_MAX_TESS_LEVEL
|
||||
0x00028A1C VGT_HOS_MIN_TESS_LEVEL
|
||||
0x00028A20 VGT_HOS_REUSE_DEPTH
|
||||
0x00028A24 VGT_GROUP_PRIM_TYPE
|
||||
0x00028A28 VGT_GROUP_FIRST_DECR
|
||||
0x00028A2C VGT_GROUP_DECR
|
||||
0x00028A30 VGT_GROUP_VECT_0_CNTL
|
||||
0x00028A34 VGT_GROUP_VECT_1_CNTL
|
||||
0x00028A38 VGT_GROUP_VECT_0_FMT_CNTL
|
||||
0x00028A3C VGT_GROUP_VECT_1_FMT_CNTL
|
||||
0x00028A40 VGT_GS_MODE
|
||||
0x00028A48 PA_SC_MODE_CNTL_0
|
||||
0x00028A4C PA_SC_MODE_CNTL_1
|
||||
0x00028A50 VGT_ENHANCE
|
||||
0x00028A54 VGT_GS_PER_ES
|
||||
0x00028A58 VGT_ES_PER_GS
|
||||
0x00028A5C VGT_GS_PER_VS
|
||||
0x00028A6C VGT_GS_OUT_PRIM_TYPE
|
||||
0x00028A84 VGT_PRIMITIVEID_EN
|
||||
0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
|
||||
0x00028AA0 VGT_INSTANCE_STEP_RATE_0
|
||||
0x00028AA4 VGT_INSTANCE_STEP_RATE_1
|
||||
0x00028AB4 VGT_REUSE_OFF
|
||||
0x00028AB8 VGT_VTX_CNT_EN
|
||||
0x00028ABC DB_HTILE_SURFACE
|
||||
0x00028AC0 DB_SRESULTS_COMPARE_STATE0
|
||||
0x00028AC4 DB_SRESULTS_COMPARE_STATE1
|
||||
0x00028AC8 DB_PRELOAD_CONTROL
|
||||
0x00028B38 VGT_GS_MAX_VERT_OUT
|
||||
0x00028B54 VGT_SHADER_STAGES_EN
|
||||
0x00028B58 VGT_LS_HS_CONFIG
|
||||
0x00028B5C VGT_LS_SIZE
|
||||
0x00028B60 VGT_HS_SIZE
|
||||
0x00028B64 VGT_LS_HS_ALLOC
|
||||
0x00028B68 VGT_HS_PATCH_CONST
|
||||
0x00028B6C VGT_TF_PARAM
|
||||
0x00028B70 DB_ALPHA_TO_MASK
|
||||
0x00028B74 VGT_DISPATCH_INITIATOR
|
||||
0x00028B78 PA_SU_POLY_OFFSET_DB_FMT_CNTL
|
||||
0x00028B7C PA_SU_POLY_OFFSET_CLAMP
|
||||
0x00028B80 PA_SU_POLY_OFFSET_FRONT_SCALE
|
||||
0x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET
|
||||
0x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE
|
||||
0x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET
|
||||
0x00028B74 VGT_GS_INSTANCE_CNT
|
||||
0x00028C00 PA_SC_LINE_CNTL
|
||||
0x00028C08 PA_SU_VTX_CNTL
|
||||
0x00028C0C PA_CL_GB_VERT_CLIP_ADJ
|
||||
0x00028C10 PA_CL_GB_VERT_DISC_ADJ
|
||||
0x00028C14 PA_CL_GB_HORZ_CLIP_ADJ
|
||||
0x00028C18 PA_CL_GB_HORZ_DISC_ADJ
|
||||
0x00028C1C PA_SC_AA_SAMPLE_LOCS_0
|
||||
0x00028C20 PA_SC_AA_SAMPLE_LOCS_1
|
||||
0x00028C24 PA_SC_AA_SAMPLE_LOCS_2
|
||||
0x00028C28 PA_SC_AA_SAMPLE_LOCS_3
|
||||
0x00028C2C PA_SC_AA_SAMPLE_LOCS_4
|
||||
0x00028C30 PA_SC_AA_SAMPLE_LOCS_5
|
||||
0x00028C34 PA_SC_AA_SAMPLE_LOCS_6
|
||||
0x00028C38 PA_SC_AA_SAMPLE_LOCS_7
|
||||
0x00028C3C PA_SC_AA_MASK
|
||||
0x00028C8C CB_COLOR0_CLEAR_WORD0
|
||||
0x00028C90 CB_COLOR0_CLEAR_WORD1
|
||||
0x00028C94 CB_COLOR0_CLEAR_WORD2
|
||||
0x00028C98 CB_COLOR0_CLEAR_WORD3
|
||||
0x00028CC8 CB_COLOR1_CLEAR_WORD0
|
||||
0x00028CCC CB_COLOR1_CLEAR_WORD1
|
||||
0x00028CD0 CB_COLOR1_CLEAR_WORD2
|
||||
0x00028CD4 CB_COLOR1_CLEAR_WORD3
|
||||
0x00028D04 CB_COLOR2_CLEAR_WORD0
|
||||
0x00028D08 CB_COLOR2_CLEAR_WORD1
|
||||
0x00028D0C CB_COLOR2_CLEAR_WORD2
|
||||
0x00028D10 CB_COLOR2_CLEAR_WORD3
|
||||
0x00028D40 CB_COLOR3_CLEAR_WORD0
|
||||
0x00028D44 CB_COLOR3_CLEAR_WORD1
|
||||
0x00028D48 CB_COLOR3_CLEAR_WORD2
|
||||
0x00028D4C CB_COLOR3_CLEAR_WORD3
|
||||
0x00028D7C CB_COLOR4_CLEAR_WORD0
|
||||
0x00028D80 CB_COLOR4_CLEAR_WORD1
|
||||
0x00028D84 CB_COLOR4_CLEAR_WORD2
|
||||
0x00028D88 CB_COLOR4_CLEAR_WORD3
|
||||
0x00028DB8 CB_COLOR5_CLEAR_WORD0
|
||||
0x00028DBC CB_COLOR5_CLEAR_WORD1
|
||||
0x00028DC0 CB_COLOR5_CLEAR_WORD2
|
||||
0x00028DC4 CB_COLOR5_CLEAR_WORD3
|
||||
0x00028DF4 CB_COLOR6_CLEAR_WORD0
|
||||
0x00028DF8 CB_COLOR6_CLEAR_WORD1
|
||||
0x00028DFC CB_COLOR6_CLEAR_WORD2
|
||||
0x00028E00 CB_COLOR6_CLEAR_WORD3
|
||||
0x00028E30 CB_COLOR7_CLEAR_WORD0
|
||||
0x00028E34 CB_COLOR7_CLEAR_WORD1
|
||||
0x00028E38 CB_COLOR7_CLEAR_WORD2
|
||||
0x00028E3C CB_COLOR7_CLEAR_WORD3
|
||||
0x00028F80 SQ_ALU_CONST_BUFFER_SIZE_HS_0
|
||||
0x00028F84 SQ_ALU_CONST_BUFFER_SIZE_HS_1
|
||||
0x00028F88 SQ_ALU_CONST_BUFFER_SIZE_HS_2
|
||||
0x00028F8C SQ_ALU_CONST_BUFFER_SIZE_HS_3
|
||||
0x00028F90 SQ_ALU_CONST_BUFFER_SIZE_HS_4
|
||||
0x00028F94 SQ_ALU_CONST_BUFFER_SIZE_HS_5
|
||||
0x00028F98 SQ_ALU_CONST_BUFFER_SIZE_HS_6
|
||||
0x00028F9C SQ_ALU_CONST_BUFFER_SIZE_HS_7
|
||||
0x00028FA0 SQ_ALU_CONST_BUFFER_SIZE_HS_8
|
||||
0x00028FA4 SQ_ALU_CONST_BUFFER_SIZE_HS_9
|
||||
0x00028FA8 SQ_ALU_CONST_BUFFER_SIZE_HS_10
|
||||
0x00028FAC SQ_ALU_CONST_BUFFER_SIZE_HS_11
|
||||
0x00028FB0 SQ_ALU_CONST_BUFFER_SIZE_HS_12
|
||||
0x00028FB4 SQ_ALU_CONST_BUFFER_SIZE_HS_13
|
||||
0x00028FB8 SQ_ALU_CONST_BUFFER_SIZE_HS_14
|
||||
0x00028FBC SQ_ALU_CONST_BUFFER_SIZE_HS_15
|
||||
0x00028FC0 SQ_ALU_CONST_BUFFER_SIZE_LS_0
|
||||
0x00028FC4 SQ_ALU_CONST_BUFFER_SIZE_LS_1
|
||||
0x00028FC8 SQ_ALU_CONST_BUFFER_SIZE_LS_2
|
||||
0x00028FCC SQ_ALU_CONST_BUFFER_SIZE_LS_3
|
||||
0x00028FD0 SQ_ALU_CONST_BUFFER_SIZE_LS_4
|
||||
0x00028FD4 SQ_ALU_CONST_BUFFER_SIZE_LS_5
|
||||
0x00028FD8 SQ_ALU_CONST_BUFFER_SIZE_LS_6
|
||||
0x00028FDC SQ_ALU_CONST_BUFFER_SIZE_LS_7
|
||||
0x00028FE0 SQ_ALU_CONST_BUFFER_SIZE_LS_8
|
||||
0x00028FE4 SQ_ALU_CONST_BUFFER_SIZE_LS_9
|
||||
0x00028FE8 SQ_ALU_CONST_BUFFER_SIZE_LS_10
|
||||
0x00028FEC SQ_ALU_CONST_BUFFER_SIZE_LS_11
|
||||
0x00028FF0 SQ_ALU_CONST_BUFFER_SIZE_LS_12
|
||||
0x00028FF4 SQ_ALU_CONST_BUFFER_SIZE_LS_13
|
||||
0x00028FF8 SQ_ALU_CONST_BUFFER_SIZE_LS_14
|
||||
0x00028FFC SQ_ALU_CONST_BUFFER_SIZE_LS_15
|
||||
0x0003CFF0 SQ_VTX_BASE_VTX_LOC
|
||||
0x0003CFF4 SQ_VTX_START_INST_LOC
|
||||
0x0003FF00 SQ_TEX_SAMPLER_CLEAR
|
||||
0x0003FF04 SQ_TEX_RESOURCE_CLEAR
|
||||
0x0003FF08 SQ_LOOP_BOOL_CLEAR
|
||||
Loading…
Reference in New Issue
Block a user