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https://github.com/FEX-Emu/linux.git
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igb: remove unused defines
This patch removes all of the unused defines from the .h files contained in igb. For some defines there was a use and so I plugged them into the correct locations. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck
David S. Miller
parent
bc1cbd3493
commit
cbd347adfe
@ -58,9 +58,6 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
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E1000_EICR_RX_QUEUE2 | \
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E1000_EICR_RX_QUEUE3)
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#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
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#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
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/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
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/* Receive Descriptor - Advanced */
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@ -95,12 +92,6 @@ union e1000_adv_rx_desc {
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#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
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#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
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/* RSS Hash results */
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/* RSS Packet Types as indicated in the receive descriptor */
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#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
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#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
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/* Transmit Descriptor - Advanced */
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union e1000_adv_tx_desc {
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struct {
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@ -150,11 +141,8 @@ struct e1000_adv_tx_context_desc {
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#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/* Direct Cache Access (DCA) definitions */
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#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
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#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
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#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
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#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
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#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
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#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
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#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
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#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
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@ -42,33 +42,9 @@
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#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
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#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
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#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
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#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
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#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
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#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
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#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
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#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
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#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
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/* Wake Up Status */
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/* Wake Up Packet Length */
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/* Four Flexible Filters are supported */
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#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
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/* Each Flexible Filter is at most 128 (0x80) bytes in length */
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#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
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/* Extended Device Control */
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#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
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#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
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#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
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#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
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#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
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#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
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#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
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#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
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@ -103,14 +79,7 @@
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#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
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#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
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#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
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#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
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#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
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#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
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#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
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#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
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#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
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#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
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#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
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#define E1000_RXDEXT_STATERR_CE 0x01000000
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#define E1000_RXDEXT_STATERR_SE 0x02000000
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@ -120,14 +89,6 @@
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#define E1000_RXDEXT_STATERR_IPE 0x40000000
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#define E1000_RXDEXT_STATERR_RXE 0x80000000
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/* mask to determine if packets should be dropped due to frame errors */
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#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
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E1000_RXD_ERR_CE | \
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E1000_RXD_ERR_SE | \
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E1000_RXD_ERR_SEQ | \
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E1000_RXD_ERR_CXE | \
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E1000_RXD_ERR_RXE)
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/* Same mask, but for extended and packet split descriptors */
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#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
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E1000_RXDEXT_STATERR_CE | \
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@ -146,16 +107,11 @@
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/* Management Control */
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#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
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#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
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#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
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/* Enable Neighbor Discovery Filtering */
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#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
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/* Enable MAC address filtering */
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#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
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/* Enable MNG packets to host memory */
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#define E1000_MANC_EN_MNG2HOST 0x00200000
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/* Enable IP address filtering */
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/* Receive Control */
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#define E1000_RCTL_EN 0x00000002 /* enable */
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@ -163,14 +119,11 @@
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#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
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#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
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#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
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#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
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#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
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#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
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#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
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#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
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#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
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#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
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#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
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#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
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#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
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@ -227,11 +180,7 @@
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/* enable link status from external LINK_0 and LINK_1 pins */
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#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
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#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
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#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
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#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
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#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
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#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
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#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
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#define E1000_CTRL_RST 0x04000000 /* Global reset */
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#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
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#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
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@ -309,9 +258,7 @@
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#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
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/* LED Control */
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#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
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#define E1000_LEDCTL_LED0_MODE_SHIFT 0
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#define E1000_LEDCTL_LED0_IVRT 0x00000040
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#define E1000_LEDCTL_LED0_BLINK 0x00000080
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#define E1000_LEDCTL_MODE_LED_ON 0xE
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@ -358,12 +305,7 @@
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#define MAX_JUMBO_FRAME_SIZE 0x3F00
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/* Extended Configuration Control and Size */
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#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
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/* PBA constants */
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#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
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#define E1000_PBA_24K 0x0018
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#define E1000_PBA_34K 0x0022
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#define E1000_PBA_64K 0x0040 /* 64KB */
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@ -379,41 +321,13 @@
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/* Interrupt Cause Read */
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#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
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#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
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#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
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#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
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#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
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#define E1000_ICR_RXO 0x00000040 /* rx overrun */
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#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
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#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
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#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
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#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
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#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
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#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
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#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
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#define E1000_ICR_TXD_LOW 0x00008000
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#define E1000_ICR_SRPD 0x00010000
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#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
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#define E1000_ICR_MNG 0x00040000 /* Manageability event */
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#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
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/* If this bit asserted, the driver should claim the interrupt */
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#define E1000_ICR_INT_ASSERTED 0x80000000
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/* queue 0 Rx descriptor FIFO parity error */
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#define E1000_ICR_RXD_FIFO_PAR0 0x00100000
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/* queue 0 Tx descriptor FIFO parity error */
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#define E1000_ICR_TXD_FIFO_PAR0 0x00200000
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/* host arb read buffer parity error */
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#define E1000_ICR_HOST_ARB_PAR 0x00400000
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#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
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/* queue 1 Rx descriptor FIFO parity error */
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#define E1000_ICR_RXD_FIFO_PAR1 0x01000000
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/* queue 1 Tx descriptor FIFO parity error */
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#define E1000_ICR_TXD_FIFO_PAR1 0x02000000
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/* FW changed the status of DISSW bit in the FWSM */
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#define E1000_ICR_DSW 0x00000020
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/* LAN connected device generates an interrupt */
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#define E1000_ICR_PHYINT 0x00001000
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#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
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#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
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/* Extended Interrupt Cause Read */
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@ -425,7 +339,6 @@
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#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
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#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
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#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
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#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
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#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
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/* TCP Timer */
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@ -455,13 +368,11 @@
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#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
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/* Extended Interrupt Mask Set */
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#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
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#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
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/* Interrupt Cause Set */
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#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
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#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
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#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
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/* Extended Interrupt Cause Set */
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@ -497,7 +408,6 @@
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#define E1000_ERR_MAC_INIT 5
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#define E1000_ERR_RESET 9
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#define E1000_ERR_MASTER_REQUESTS_PENDING 10
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#define E1000_ERR_HOST_INTERFACE_COMMAND 11
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#define E1000_BLK_PHY_RESET 12
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#define E1000_ERR_SWFW_SYNC 13
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#define E1000_NOT_IMPLEMENTED 14
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@ -517,30 +427,9 @@
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/* Flow Control */
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#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
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/* Transmit Configuration Word */
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#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
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/* Receive Configuration Word */
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/* PCI Express Control */
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#define E1000_GCR_RXD_NO_SNOOP 0x00000001
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#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
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#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
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#define E1000_GCR_TXD_NO_SNOOP 0x00000008
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#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
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#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
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#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
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E1000_GCR_RXDSCW_NO_SNOOP | \
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E1000_GCR_RXDSCR_NO_SNOOP | \
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E1000_GCR_TXD_NO_SNOOP | \
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E1000_GCR_TXDSCW_NO_SNOOP | \
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E1000_GCR_TXDSCR_NO_SNOOP)
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/* PHY Control Register */
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#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
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#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
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#define MII_CR_POWER_DOWN 0x0800 /* Power down */
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#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
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#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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@ -670,10 +559,8 @@
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#define IGP_LED3_MODE 0x07000000
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/* PCI/PCI-X/PCI-EX Config space */
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#define PCI_HEADER_TYPE_REGISTER 0x0E
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#define PCIE_LINK_STATUS 0x12
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#define PCI_HEADER_TYPE_MULTIFUNC 0x80
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#define PCIE_LINK_WIDTH_MASK 0x3F0
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#define PCIE_LINK_WIDTH_SHIFT 4
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@ -82,13 +82,8 @@ enum e1000_mng_mode {
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#define E1000_FWSM_MODE_MASK 0xE
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#define E1000_FWSM_MODE_SHIFT 1
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#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
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#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
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#define E1000_HICR_EN 0x01 /* Enable bit - RO */
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/* Driver sets this bit when done to put command in RAM */
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#define E1000_HICR_C 0x02
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extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
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extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
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@ -39,9 +39,6 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw);
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/* Cable length tables */
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static const u16 e1000_m88_cable_length_table[] =
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{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
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#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
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(sizeof(e1000_m88_cable_length_table) / \
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sizeof(e1000_m88_cable_length_table[0]))
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static const u16 e1000_igp_2_cable_length_table[] =
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{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
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@ -73,7 +73,6 @@
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#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
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#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
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#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
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#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
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#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
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/* IEEE 1588 TIMESYNCH */
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@ -178,7 +177,6 @@ enum {
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: (0x0E018 + ((_n) * 0x40)))
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#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
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: (0x0E028 + ((_n) * 0x40)))
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#define E1000_TARC(_n) (0x03840 + (_n << 8))
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#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
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#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
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#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
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@ -301,9 +299,7 @@ enum {
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#define E1000_MANC 0x05820 /* Management Control - RW */
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#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
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#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
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#define E1000_HOST_IF 0x08800 /* Host Interface */
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#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
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#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
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#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
|
||||
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
|
||||
@ -311,9 +307,7 @@ enum {
|
||||
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
|
||||
#define E1000_SWSM 0x05B50 /* SW Semaphore */
|
||||
#define E1000_FWSM 0x05B54 /* FW Semaphore */
|
||||
#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
|
||||
#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
|
||||
#define E1000_HICR 0x08F00 /* Host Inteface Control */
|
||||
|
||||
/* RSS registers */
|
||||
#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
|
||||
@ -322,14 +316,6 @@ enum {
|
||||
#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
|
||||
/* MSI-X Allocation Register (_i) - RW */
|
||||
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
|
||||
/* MSI-X Table entry addr low reg 0 - RW */
|
||||
#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry addr upper reg 0 - RW */
|
||||
#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry message reg 0 - RW */
|
||||
#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
|
||||
/* MSI-X Table entry vector ctrl reg 0 - RW */
|
||||
#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
|
||||
/* Redirection Table - RW Array */
|
||||
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
|
||||
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
|
||||
|
||||
@ -40,17 +40,9 @@
|
||||
|
||||
struct igb_adapter;
|
||||
|
||||
/* Interrupt defines */
|
||||
#define IGB_MIN_DYN_ITR 3000
|
||||
#define IGB_MAX_DYN_ITR 96000
|
||||
|
||||
/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
|
||||
#define IGB_START_ITR 648
|
||||
|
||||
#define IGB_DYN_ITR_PACKET_THRESHOLD 2
|
||||
#define IGB_DYN_ITR_LENGTH_LOW 200
|
||||
#define IGB_DYN_ITR_LENGTH_HIGH 1000
|
||||
|
||||
/* TX/RX descriptor defines */
|
||||
#define IGB_DEFAULT_TXD 256
|
||||
#define IGB_MIN_TXD 80
|
||||
@ -92,8 +84,6 @@ struct igb_adapter;
|
||||
#define IGB_RXBUFFER_512 512
|
||||
#define IGB_RXBUFFER_1024 1024
|
||||
#define IGB_RXBUFFER_2048 2048
|
||||
#define IGB_RXBUFFER_4096 4096
|
||||
#define IGB_RXBUFFER_8192 8192
|
||||
#define IGB_RXBUFFER_16384 16384
|
||||
|
||||
/* Packet Buffer allocations */
|
||||
@ -286,10 +276,9 @@ struct igb_adapter {
|
||||
};
|
||||
|
||||
#define IGB_FLAG_HAS_MSI (1 << 0)
|
||||
#define IGB_FLAG_MSI_ENABLE (1 << 1)
|
||||
#define IGB_FLAG_DCA_ENABLED (1 << 2)
|
||||
#define IGB_FLAG_QUAD_PORT_A (1 << 3)
|
||||
#define IGB_FLAG_NEED_CTX_IDX (1 << 4)
|
||||
#define IGB_FLAG_DCA_ENABLED (1 << 1)
|
||||
#define IGB_FLAG_QUAD_PORT_A (1 << 2)
|
||||
#define IGB_FLAG_NEED_CTX_IDX (1 << 3)
|
||||
|
||||
enum e1000_state_t {
|
||||
__IGB_TESTING,
|
||||
|
||||
@ -1366,8 +1366,7 @@ static int igb_setup_desc_rings(struct igb_adapter *adapter)
|
||||
wr32(E1000_RDH(0), 0);
|
||||
wr32(E1000_RDT(0), 0);
|
||||
rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
|
||||
rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
|
||||
E1000_RCTL_RDMTS_HALF |
|
||||
rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
|
||||
(adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
|
||||
wr32(E1000_RCTL, rctl);
|
||||
wr32(E1000_SRRCTL(0), 0);
|
||||
@ -1855,9 +1854,6 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* toggle LED 4 times per second = 2 "blinks" per second */
|
||||
#define IGB_ID_INTERVAL (HZ/4)
|
||||
|
||||
/* bit defines for adapter->led_status */
|
||||
#define IGB_LED_ON 0
|
||||
|
||||
|
||||
@ -1305,7 +1305,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
|
||||
hw->fc.original_type = e1000_fc_default;
|
||||
hw->fc.type = e1000_fc_default;
|
||||
|
||||
adapter->itr_setting = 3;
|
||||
adapter->itr_setting = IGB_DEFAULT_ITR;
|
||||
adapter->itr = IGB_START_ITR;
|
||||
|
||||
igb_validate_mdi_setting(hw);
|
||||
@ -1366,7 +1366,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
|
||||
dev_info(&pdev->dev, "DCA enabled\n");
|
||||
/* Always use CB2 mode, difference is masked
|
||||
* in the CB driver. */
|
||||
wr32(E1000_DCA_CTRL, 2);
|
||||
wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
|
||||
igb_setup_dca(adapter);
|
||||
}
|
||||
#endif
|
||||
@ -1498,7 +1498,7 @@ static void __devexit igb_remove(struct pci_dev *pdev)
|
||||
dev_info(&pdev->dev, "DCA disabled\n");
|
||||
dca_remove_requester(&pdev->dev);
|
||||
adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
|
||||
wr32(E1000_DCA_CTRL, 1);
|
||||
wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -3058,8 +3058,6 @@ static int igb_maybe_stop_tx(struct net_device *netdev,
|
||||
return __igb_maybe_stop_tx(netdev, tx_ring, size);
|
||||
}
|
||||
|
||||
#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
|
||||
|
||||
static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
|
||||
struct net_device *netdev,
|
||||
struct igb_ring *tx_ring)
|
||||
@ -3586,7 +3584,7 @@ static int __igb_notify_dca(struct device *dev, void *data)
|
||||
break;
|
||||
/* Always use CB2 mode, difference is masked
|
||||
* in the CB driver. */
|
||||
wr32(E1000_DCA_CTRL, 2);
|
||||
wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
|
||||
if (dca_add_requester(dev) == 0) {
|
||||
adapter->flags |= IGB_FLAG_DCA_ENABLED;
|
||||
dev_info(&adapter->pdev->dev, "DCA enabled\n");
|
||||
@ -3601,7 +3599,7 @@ static int __igb_notify_dca(struct device *dev, void *data)
|
||||
dca_remove_requester(dev);
|
||||
dev_info(&adapter->pdev->dev, "DCA disabled\n");
|
||||
adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
|
||||
wr32(E1000_DCA_CTRL, 1);
|
||||
wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user