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KVM: PPC: Book3S HV: Don't wake thread with no vcpu on guest IPI

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When running a multi-threaded guest and vcpu 0 in a virtual core
is not running in the guest (i.e. it is busy elsewhere in the host),
thread 0 of the physical core will switch the MMU to the guest and
then go to nap mode in the code at kvm_do_nap.  If the guest sends
an IPI to thread 0 using the msgsndp instruction, that will wake
up thread 0 and cause all the threads in the guest to exit to the
host unnecessarily.  To avoid the unnecessary exit, this arranges
for the PECEDP bit to be cleared in this situation.  When napping
due to a H_CEDE from the guest, we still set PECEDP so that the
thread will wake up on an IPI sent using msgsndp.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Paul Mackerras 2015-03-28 14:21:07 +11:00 committed by Alexander Graf
parent 5d5b99cd68
commit ccc07772c9
1 changed files with 7 additions and 3 deletions
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10
arch/powerpc/kvm/book3s_hv_rmhandlers.S
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@ -191,6 +191,7 @@ kvmppc_primary_no_guest:
li r3, NAPPING_NOVCPU li r3, NAPPING_NOVCPU
stb r3, HSTATE_NAPPING(r13) stb r3, HSTATE_NAPPING(r13)
li r3, 0 /* Don't wake on privileged (OS) doorbell */
b kvm_do_nap b kvm_do_nap
kvm_novcpu_wakeup: kvm_novcpu_wakeup:
@ -2129,10 +2130,13 @@ _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
bl kvmhv_accumulate_time bl kvmhv_accumulate_time
#endif #endif
lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
/* /*
* Take a nap until a decrementer or external or doobell interrupt * Take a nap until a decrementer or external or doobell interrupt
* occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the * occurs, with PECE1 and PECE0 set in LPCR.
* runlatch bit before napping. * On POWER8, if we are ceding, also set PECEDP.
* Also clear the runlatch bit before napping.
*/ */
kvm_do_nap: kvm_do_nap:
mfspr r0, SPRN_CTRLF mfspr r0, SPRN_CTRLF
@ -2144,7 +2148,7 @@ kvm_do_nap:
mfspr r5,SPRN_LPCR mfspr r5,SPRN_LPCR
ori r5,r5,LPCR_PECE0 | LPCR_PECE1 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
oris r5,r5,LPCR_PECEDP@h rlwimi r5, r3, 0, LPCR_PECEDP
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
mtspr SPRN_LPCR,r5 mtspr SPRN_LPCR,r5
isync isync