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mmc: omap_hsmmc: Enable HSPE bit for high speed cards
HSMMC IP on AM33xx need a special setting to handle High-speed cards. Other platforms like TI81xx, OMAP4 may need this as-well. This depends on the HSMMC IP timing closure done for the high speed cards. From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation): The MMC/SD/SDIO output signals can be driven on either falling edge or rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows to reach better timing performance, and thus to increase data transfer frequency. There are few pre-requisites for enabling the HSPE bit - Controller should support High-Speed-Enable Bit and - Controller should not be using DDR Mode and - Controller should advertise that it supports High Speed in capabilities register and - MMC/SD clock coming out of controller > 25MHz Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com> Signed-off-by: Venkatraman S <svenkatr@ti.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -19,6 +19,7 @@ ti,dual-volt: boolean, supports dual voltage cards
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"supply-name" examples are "vmmc", "vmmc_aux" etc
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ti,non-removable: non-removable slot (like eMMC)
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ti,needs-special-reset: Requires a special softreset sequence
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ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
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Example:
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mmc1: mmc@0x4809c000 {
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@ -126,6 +126,7 @@ struct omap_mmc_platform_data {
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/* we can put the features above into this variable */
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#define HSMMC_HAS_PBIAS (1 << 0)
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#define HSMMC_HAS_UPDATED_RESET (1 << 1)
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#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
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unsigned features;
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int switch_pin; /* gpio (card detect) */
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@ -63,6 +63,7 @@
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#define VS18 (1 << 26)
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#define VS30 (1 << 25)
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#define HSS (1 << 21)
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#define SDVS18 (0x5 << 9)
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#define SDVS30 (0x6 << 9)
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#define SDVS33 (0x7 << 9)
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@ -90,6 +91,7 @@
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#define MSBS (1 << 5)
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#define BCE (1 << 1)
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#define FOUR_BIT (1 << 1)
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#define HSPE (1 << 2)
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#define DDR (1 << 19)
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#define DW8 (1 << 5)
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#define CC 0x1
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@ -495,6 +497,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
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struct mmc_ios *ios = &host->mmc->ios;
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unsigned long regval;
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unsigned long timeout;
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unsigned long clkdiv;
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dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
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@ -502,7 +505,8 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
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regval = OMAP_HSMMC_READ(host->base, SYSCTL);
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regval = regval & ~(CLKD_MASK | DTO_MASK);
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regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
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clkdiv = calc_divisor(host, ios);
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regval = regval | (clkdiv << 6) | (DTO << 16);
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OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
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OMAP_HSMMC_WRITE(host->base, SYSCTL,
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OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
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@ -513,6 +517,27 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
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&& time_before(jiffies, timeout))
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cpu_relax();
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/*
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* Enable High-Speed Support
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* Pre-Requisites
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* - Controller should support High-Speed-Enable Bit
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* - Controller should not be using DDR Mode
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* - Controller should advertise that it supports High Speed
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* in capabilities register
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* - MMC/SD clock coming out of controller > 25MHz
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*/
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if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
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(ios->timing != MMC_TIMING_UHS_DDR50) &&
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((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
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regval = OMAP_HSMMC_READ(host->base, HCTL);
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if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
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regval |= HSPE;
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else
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regval &= ~HSPE;
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OMAP_HSMMC_WRITE(host->base, HCTL, regval);
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}
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omap_hsmmc_start_clock(host);
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}
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@ -1715,6 +1740,9 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
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if (!of_property_read_u32(np, "max-frequency", &max_freq))
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pdata->max_freq = max_freq;
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if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
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pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
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return pdata;
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}
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#else
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