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i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
All the I2C controllers on Intel BayTrail LPSS subsystem able to support 10-bit addressing mode functionality. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -64,12 +64,19 @@ struct dw_pci_controller {
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u32 tx_fifo_depth;
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u32 tx_fifo_depth;
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u32 rx_fifo_depth;
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u32 rx_fifo_depth;
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u32 clk_khz;
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u32 clk_khz;
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u32 functionality;
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};
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};
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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DW_IC_CON_SLAVE_DISABLE | \
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DW_IC_CON_SLAVE_DISABLE | \
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DW_IC_CON_RESTART_EN)
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DW_IC_CON_RESTART_EN)
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#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK)
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static struct dw_pci_controller dw_pci_controllers[] = {
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static struct dw_pci_controller dw_pci_controllers[] = {
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[moorestown_0] = {
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[moorestown_0] = {
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.bus_num = 0,
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.bus_num = 0,
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@ -140,6 +147,7 @@ static struct dw_pci_controller dw_pci_controllers[] = {
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.tx_fifo_depth = 32,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 100000,
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.clk_khz = 100000,
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.functionality = I2C_FUNC_10BIT_ADDR,
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},
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},
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};
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};
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static struct i2c_algorithm i2c_dw_algo = {
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static struct i2c_algorithm i2c_dw_algo = {
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@ -212,12 +220,9 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
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dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
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dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
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dev->base = pcim_iomap_table(pdev)[0];
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dev->base = pcim_iomap_table(pdev)[0];
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dev->dev = &pdev->dev;
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dev->dev = &pdev->dev;
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dev->functionality =
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dev->functionality = controller->functionality |
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I2C_FUNC_I2C |
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DW_DEFAULT_FUNCTIONALITY;
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I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA |
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I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_I2C_BLOCK;
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dev->master_cfg = controller->bus_cfg;
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dev->master_cfg = controller->bus_cfg;
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pci_set_drvdata(pdev, dev);
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pci_set_drvdata(pdev, dev);
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