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crypto: caam - Modify the interface layers to use JR API's
- Earlier interface layers - caamalg, caamhash, caamrng were directly using the Controller driver private structure to access the Job ring. - Changed the above to use alloc/free API's provided by Job Ring Drive Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Garg Vakul-B16394 <vakul@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ruchika Gupta
Herbert Xu
parent
07defbfb0f
commit
cfc6f11b76
@ -86,6 +86,7 @@
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#else
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#define debug(format, arg...)
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#endif
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static struct list_head alg_list;
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/* Set DK bit in class 1 operation if shared */
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static inline void append_dec_op1(u32 *desc, u32 type)
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@ -2057,7 +2058,6 @@ static struct caam_alg_template driver_algs[] = {
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struct caam_crypto_alg {
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struct list_head entry;
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struct device *ctrldev;
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int class1_alg_type;
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int class2_alg_type;
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int alg_op;
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@ -2070,16 +2070,12 @@ static int caam_cra_init(struct crypto_tfm *tfm)
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struct caam_crypto_alg *caam_alg =
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container_of(alg, struct caam_crypto_alg, crypto_alg);
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struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
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struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
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struct platform_device *pdev;
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int tgt_jr = atomic_inc_return(&priv->tfm_count);
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/*
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* distribute tfms across job rings to ensure in-order
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* crypto request processing per tfm
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*/
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pdev = priv->jrpdev[(tgt_jr / 2) % priv->total_jobrs];
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ctx->jrdev = &pdev->dev;
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ctx->jrdev = caam_jr_alloc();
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if (IS_ERR(ctx->jrdev)) {
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pr_err("Job Ring Device allocation for transform failed\n");
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return PTR_ERR(ctx->jrdev);
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}
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/* copy descriptor header template value */
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ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
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@ -2106,44 +2102,26 @@ static void caam_cra_exit(struct crypto_tfm *tfm)
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dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
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desc_bytes(ctx->sh_desc_givenc),
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DMA_TO_DEVICE);
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caam_jr_free(ctx->jrdev);
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}
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static void __exit caam_algapi_exit(void)
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{
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struct device_node *dev_node;
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struct platform_device *pdev;
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struct device *ctrldev;
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struct caam_drv_private *priv;
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struct caam_crypto_alg *t_alg, *n;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
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if (!dev_node)
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return;
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}
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pdev = of_find_device_by_node(dev_node);
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if (!pdev)
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if (!alg_list.next)
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return;
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ctrldev = &pdev->dev;
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of_node_put(dev_node);
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priv = dev_get_drvdata(ctrldev);
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if (!priv->alg_list.next)
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return;
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list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
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list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
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crypto_unregister_alg(&t_alg->crypto_alg);
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list_del(&t_alg->entry);
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kfree(t_alg);
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}
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}
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static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
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struct caam_alg_template
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static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
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*template)
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{
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struct caam_crypto_alg *t_alg;
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@ -2151,7 +2129,7 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
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t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
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if (!t_alg) {
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dev_err(ctrldev, "failed to allocate t_alg\n");
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pr_err("failed to allocate t_alg\n");
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return ERR_PTR(-ENOMEM);
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}
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@ -2183,69 +2161,39 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
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t_alg->class1_alg_type = template->class1_alg_type;
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t_alg->class2_alg_type = template->class2_alg_type;
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t_alg->alg_op = template->alg_op;
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t_alg->ctrldev = ctrldev;
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return t_alg;
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}
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static int __init caam_algapi_init(void)
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{
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struct device_node *dev_node;
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struct platform_device *pdev;
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struct device *ctrldev;
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struct caam_drv_private *priv;
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int i = 0, err = 0;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
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if (!dev_node)
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return -ENODEV;
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}
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pdev = of_find_device_by_node(dev_node);
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if (!pdev)
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return -ENODEV;
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ctrldev = &pdev->dev;
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priv = dev_get_drvdata(ctrldev);
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of_node_put(dev_node);
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/*
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* If priv is NULL, it's probably because the caam driver wasn't
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* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
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*/
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if (!priv)
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return -ENODEV;
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INIT_LIST_HEAD(&priv->alg_list);
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atomic_set(&priv->tfm_count, -1);
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INIT_LIST_HEAD(&alg_list);
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/* register crypto algorithms the device supports */
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for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
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/* TODO: check if h/w supports alg */
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struct caam_crypto_alg *t_alg;
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t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]);
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t_alg = caam_alg_alloc(&driver_algs[i]);
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if (IS_ERR(t_alg)) {
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err = PTR_ERR(t_alg);
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dev_warn(ctrldev, "%s alg allocation failed\n",
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driver_algs[i].driver_name);
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pr_warn("%s alg allocation failed\n",
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driver_algs[i].driver_name);
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continue;
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}
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err = crypto_register_alg(&t_alg->crypto_alg);
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if (err) {
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dev_warn(ctrldev, "%s alg registration failed\n",
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pr_warn("%s alg registration failed\n",
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t_alg->crypto_alg.cra_driver_name);
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kfree(t_alg);
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} else
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list_add_tail(&t_alg->entry, &priv->alg_list);
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list_add_tail(&t_alg->entry, &alg_list);
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}
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if (!list_empty(&priv->alg_list))
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dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n",
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(char *)of_get_property(dev_node, "compatible", NULL));
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if (!list_empty(&alg_list))
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pr_info("caam algorithms registered in /proc/crypto\n");
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return err;
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}
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@ -94,6 +94,9 @@
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#define debug(format, arg...)
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#endif
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static struct list_head hash_list;
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/* ahash per-session context */
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struct caam_hash_ctx {
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struct device *jrdev;
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@ -1653,7 +1656,6 @@ static struct caam_hash_template driver_hash[] = {
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struct caam_hash_alg {
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struct list_head entry;
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struct device *ctrldev;
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int alg_type;
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int alg_op;
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struct ahash_alg ahash_alg;
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@ -1670,7 +1672,6 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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struct caam_hash_alg *caam_hash =
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container_of(alg, struct caam_hash_alg, ahash_alg);
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struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
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struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev);
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/* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
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static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
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HASH_MSG_LEN + SHA1_DIGEST_SIZE,
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@ -1678,17 +1679,17 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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HASH_MSG_LEN + SHA256_DIGEST_SIZE,
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HASH_MSG_LEN + 64,
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HASH_MSG_LEN + SHA512_DIGEST_SIZE };
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int tgt_jr = atomic_inc_return(&priv->tfm_count);
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int ret = 0;
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struct platform_device *pdev;
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/*
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* distribute tfms across job rings to ensure in-order
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* Get a Job ring from Job Ring driver to ensure in-order
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* crypto request processing per tfm
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*/
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pdev = priv->jrpdev[tgt_jr % priv->total_jobrs];
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ctx->jrdev = &pdev->dev;
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ctx->jrdev = caam_jr_alloc();
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if (IS_ERR(ctx->jrdev)) {
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pr_err("Job Ring Device allocation for transform failed\n");
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return PTR_ERR(ctx->jrdev);
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}
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/* copy descriptor header template value */
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ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
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ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
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@ -1731,35 +1732,18 @@ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
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!dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
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dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
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desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
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caam_jr_free(ctx->jrdev);
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}
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static void __exit caam_algapi_hash_exit(void)
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{
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struct device_node *dev_node;
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struct platform_device *pdev;
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struct device *ctrldev;
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struct caam_drv_private *priv;
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struct caam_hash_alg *t_alg, *n;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
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if (!dev_node)
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return;
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}
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pdev = of_find_device_by_node(dev_node);
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if (!pdev)
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if (!hash_list.next)
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return;
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ctrldev = &pdev->dev;
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of_node_put(dev_node);
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priv = dev_get_drvdata(ctrldev);
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if (!priv->hash_list.next)
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return;
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list_for_each_entry_safe(t_alg, n, &priv->hash_list, entry) {
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list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
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crypto_unregister_ahash(&t_alg->ahash_alg);
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list_del(&t_alg->entry);
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kfree(t_alg);
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@ -1767,7 +1751,7 @@ static void __exit caam_algapi_hash_exit(void)
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}
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static struct caam_hash_alg *
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caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
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caam_hash_alloc(struct caam_hash_template *template,
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bool keyed)
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{
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struct caam_hash_alg *t_alg;
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@ -1776,7 +1760,7 @@ caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
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t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL);
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if (!t_alg) {
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dev_err(ctrldev, "failed to allocate t_alg\n");
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pr_err("failed to allocate t_alg\n");
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return ERR_PTR(-ENOMEM);
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}
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@ -1807,44 +1791,15 @@ caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
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t_alg->alg_type = template->alg_type;
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t_alg->alg_op = template->alg_op;
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t_alg->ctrldev = ctrldev;
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return t_alg;
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}
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static int __init caam_algapi_hash_init(void)
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{
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struct device_node *dev_node;
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struct platform_device *pdev;
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struct device *ctrldev;
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struct caam_drv_private *priv;
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int i = 0, err = 0;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
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if (!dev_node)
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return -ENODEV;
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}
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pdev = of_find_device_by_node(dev_node);
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if (!pdev)
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return -ENODEV;
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ctrldev = &pdev->dev;
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priv = dev_get_drvdata(ctrldev);
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of_node_put(dev_node);
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/*
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* If priv is NULL, it's probably because the caam driver wasn't
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* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
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*/
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if (!priv)
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return -ENODEV;
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INIT_LIST_HEAD(&priv->hash_list);
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atomic_set(&priv->tfm_count, -1);
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INIT_LIST_HEAD(&hash_list);
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/* register crypto algorithms the device supports */
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for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
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@ -1852,38 +1807,38 @@ static int __init caam_algapi_hash_init(void)
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struct caam_hash_alg *t_alg;
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/* register hmac version */
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t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], true);
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t_alg = caam_hash_alloc(&driver_hash[i], true);
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if (IS_ERR(t_alg)) {
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err = PTR_ERR(t_alg);
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dev_warn(ctrldev, "%s alg allocation failed\n",
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driver_hash[i].driver_name);
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pr_warn("%s alg allocation failed\n",
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driver_hash[i].driver_name);
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continue;
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}
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err = crypto_register_ahash(&t_alg->ahash_alg);
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if (err) {
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dev_warn(ctrldev, "%s alg registration failed\n",
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pr_warn("%s alg registration failed\n",
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t_alg->ahash_alg.halg.base.cra_driver_name);
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kfree(t_alg);
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} else
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list_add_tail(&t_alg->entry, &priv->hash_list);
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list_add_tail(&t_alg->entry, &hash_list);
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/* register unkeyed version */
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t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], false);
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t_alg = caam_hash_alloc(&driver_hash[i], false);
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if (IS_ERR(t_alg)) {
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err = PTR_ERR(t_alg);
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dev_warn(ctrldev, "%s alg allocation failed\n",
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driver_hash[i].driver_name);
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pr_warn("%s alg allocation failed\n",
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driver_hash[i].driver_name);
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continue;
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}
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err = crypto_register_ahash(&t_alg->ahash_alg);
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if (err) {
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dev_warn(ctrldev, "%s alg registration failed\n",
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pr_warn("%s alg registration failed\n",
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t_alg->ahash_alg.halg.base.cra_driver_name);
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kfree(t_alg);
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} else
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list_add_tail(&t_alg->entry, &priv->hash_list);
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list_add_tail(&t_alg->entry, &hash_list);
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}
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return err;
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@ -273,42 +273,23 @@ static struct hwrng caam_rng = {
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static void __exit caam_rng_exit(void)
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{
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caam_jr_free(rng_ctx.jrdev);
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hwrng_unregister(&caam_rng);
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}
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static int __init caam_rng_init(void)
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{
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struct device_node *dev_node;
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struct platform_device *pdev, *jrpdev;
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struct device *ctrldev;
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struct caam_drv_private *priv;
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struct device *dev;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
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if (!dev_node)
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return -ENODEV;
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dev = caam_jr_alloc();
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if (IS_ERR(dev)) {
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pr_err("Job Ring Device allocation for transform failed\n");
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return PTR_ERR(dev);
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}
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pdev = of_find_device_by_node(dev_node);
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if (!pdev)
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return -ENODEV;
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caam_init_rng(&rng_ctx, dev);
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ctrldev = &pdev->dev;
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priv = dev_get_drvdata(ctrldev);
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of_node_put(dev_node);
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/*
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* If priv is NULL, it's probably because the caam driver wasn't
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* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
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*/
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if (!priv)
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return -ENODEV;
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jrpdev = priv->jrpdev[0];
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caam_init_rng(&rng_ctx, &jrpdev->dev);
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dev_info(&jrpdev->dev, "registering rng-caam\n");
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dev_info(dev, "registering rng-caam\n");
|
||||
return hwrng_register(&caam_rng);
|
||||
}
|
||||
|
||||
|
||||
@ -83,13 +83,6 @@ struct caam_drv_private {
|
||||
u8 qi_present; /* Nonzero if QI present in device */
|
||||
int secvio_irq; /* Security violation interrupt number */
|
||||
|
||||
/* which jr allocated to scatterlist crypto */
|
||||
atomic_t tfm_count ____cacheline_aligned;
|
||||
/* list of registered crypto algorithms (mk generic context handle?) */
|
||||
struct list_head alg_list;
|
||||
/* list of registered hash algorithms (mk generic context handle?) */
|
||||
struct list_head hash_list;
|
||||
|
||||
#define RNG4_MAX_HANDLES 2
|
||||
/* RNG4 block */
|
||||
u32 rng4_sh_init; /* This bitmap shows which of the State
|
||||
|
||||
Loading…
Reference in New Issue
Block a user