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drm/amdgpu: refine uvd pg code in kv_dpm.c
1. no need to set cg as use hw dynamic cg. 2. when uvd idle, stop uvd. encode, start uvd. 3. if pg feature enabled, power on/down uvd by smu. 4. drm/amdgpu: dpm do not set uvd pg status. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1688,38 +1688,25 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
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struct kv_power_info *pi = kv_get_pi(adev);
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int ret;
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if (pi->uvd_power_gated == gate)
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return;
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pi->uvd_power_gated = gate;
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if (gate) {
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if (pi->caps_uvd_pg) {
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/* disable clockgating so we can properly shut down the block */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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/* shutdown the UVD block */
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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/* XXX: check for errors */
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}
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/* stop the UVD block */
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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kv_update_uvd_dpm(adev, gate);
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if (pi->caps_uvd_pg)
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/* power off the UVD block */
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
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} else {
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if (pi->caps_uvd_pg) {
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if (pi->caps_uvd_pg)
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/* power on the UVD block */
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
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/* re-init the UVD block */
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_GATE);
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/* XXX: check for errors */
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}
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kv_update_uvd_dpm(adev, gate);
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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}
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}
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@ -3010,7 +2997,7 @@ static int kv_dpm_late_init(void *handle)
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kv_dpm_powergate_acp(adev, true);
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kv_dpm_powergate_samu(adev, true);
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kv_dpm_powergate_vce(adev, true);
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kv_dpm_powergate_uvd(adev, true);
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return 0;
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}
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