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DMA: AT91: Get transfer width
In one dma transfer, the data transfer width can be configured and it is limited by source or destination peripheral width, tx_width will save the transfer width, but for memcpy, either source or destination transfer width is taken as tx_width. Signed-off-by: Elen Song <elen.song@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -615,6 +615,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = len;
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first->tx_width = src_width;
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/* set end-of-link to the last link descriptor of list*/
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set_desc_eol(desc);
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@ -761,6 +762,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = total_len;
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first->tx_width = reg_width;
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/* first link descriptor of list is responsible of flags */
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first->txd.flags = flags; /* client is in control of this ack */
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@ -919,6 +921,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = buf_len;
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first->tx_width = reg_width;
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return &first->txd;
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@ -182,6 +182,7 @@ struct at_lli {
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* @txd: support for the async_tx api
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* @desc_node: node on the channed descriptors list
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* @len: total transaction bytecount
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* @tx_width: transfer width
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*/
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struct at_desc {
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/* FIRST values the hardware uses */
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@ -192,6 +193,7 @@ struct at_desc {
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struct dma_async_tx_descriptor txd;
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struct list_head desc_node;
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size_t len;
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u32 tx_width;
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};
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static inline struct at_desc *
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