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drm/i915: Only insert the mb() before updating the fence parameter
With a fence, we only need to insert a memory barrier around the actual fence alteration for CPU accesses through the GTT. Performing the barrier in flush-fence was inserting unnecessary and expensive barriers for never fenced objects. Note removing the barriers from flush-fence, which was effectively a barrier before every direct access through the GTT, revealed that we where missing a barrier before the first access through the GTT. Lack of that barrier was sufficient to cause GPU hangs. v2: Add a couple more comments to explain the new barriers Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2611,9 +2611,22 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
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POSTING_READ(FENCE_REG_830_0 + reg * 4);
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}
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inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
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{
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return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
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}
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static void i915_gem_write_fence(struct drm_device *dev, int reg,
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struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* Ensure that all CPU reads are completed before installing a fence
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* and all writes before removing the fence.
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*/
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if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
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mb();
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switch (INTEL_INFO(dev)->gen) {
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case 7:
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case 6:
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@ -2623,6 +2636,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
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case 2: i830_write_fence_reg(dev, reg, obj); break;
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default: BUG();
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}
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/* And similarly be paranoid that no direct access to this region
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* is reordered to before the fence is installed.
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*/
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if (i915_gem_object_needs_mb(obj))
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mb();
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}
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static inline int fence_number(struct drm_i915_private *dev_priv,
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@ -2652,7 +2671,7 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
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}
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static int
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i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
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i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
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{
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if (obj->last_fenced_seqno) {
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int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
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@ -2662,12 +2681,6 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
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obj->last_fenced_seqno = 0;
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}
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/* Ensure that all CPU reads are completed before installing a fence
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* and all writes before removing the fence.
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*/
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if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
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mb();
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obj->fenced_gpu_access = false;
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return 0;
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}
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@ -2678,7 +2691,7 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
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struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
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int ret;
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ret = i915_gem_object_flush_fence(obj);
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ret = i915_gem_object_wait_fence(obj);
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if (ret)
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return ret;
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@ -2752,7 +2765,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
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* will need to serialise the write to the associated fence register?
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*/
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if (obj->fence_dirty) {
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ret = i915_gem_object_flush_fence(obj);
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ret = i915_gem_object_wait_fence(obj);
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if (ret)
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return ret;
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}
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@ -2773,7 +2786,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
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if (reg->obj) {
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struct drm_i915_gem_object *old = reg->obj;
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ret = i915_gem_object_flush_fence(old);
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ret = i915_gem_object_wait_fence(old);
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if (ret)
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return ret;
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@ -3068,6 +3081,13 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
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i915_gem_object_flush_cpu_write_domain(obj);
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/* Serialise direct access to this object with the barriers for
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* coherent writes from the GPU, by effectively invalidating the
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* GTT domain upon first access.
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*/
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if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
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mb();
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old_write_domain = obj->base.write_domain;
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old_read_domains = obj->base.read_domains;
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