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PCI: faraday: Add clock bindings

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The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.  Add
bindings for these two clocks so we can assign them in the device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Linus Walleij 2017-05-15 19:23:12 +02:00 committed by Bjorn Helgaas
parent 769b461fc0
commit d1ef28900d
1 changed files with 7 additions and 0 deletions
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7
Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
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@ -30,6 +30,13 @@ Mandatory properties:
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
pre-fetchable.
Optional properties:
- clocks: when present, this should contain the peripheral clock (PCLK) and the
PCI clock (PCICLK). If these are not present, they are assumed to be
hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
- clock-names: when present, this should contain "PCLK" for the peripheral
clock and "PCICLK" for the PCI-side clock.
Mandatory subnodes:
- For "faraday,ftpci100" a node representing the interrupt-controller inside the
host bridge is mandatory. It has the following mandatory properties: