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powerpc/4xx: Convert Sam440ep DTS to dts-v1
This makes the sam440ep.dts dts-v1 compliant. Signed-off-by: Giuseppe Coviello <gicoviello@gmail.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Giuseppe Coviello
Josh Boyer
parent
b6014e15bc
commit
d2146cb274
@ -13,12 +13,13 @@
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "acube,sam440ep";
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compatible = "acube,sam440ep";
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dcr-parent = <&/cpus/cpu@0>;
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aliases {
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ethernet0 = &EMAC0;
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@ -39,10 +40,10 @@
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reg = <0>;
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clock-frequency = <0>; /* Filled in by zImage */
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timebase-frequency = <0>; /* Filled in by zImage */
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i-cache-line-size = <20>;
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d-cache-line-size = <20>;
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i-cache-size = <8000>;
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d-cache-size = <8000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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};
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@ -57,7 +58,7 @@
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compatible = "ibm,uic-440ep","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0c0 009>;
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dcr-reg = <0x0c0 9>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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@ -67,22 +68,22 @@
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compatible = "ibm,uic-440ep","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0d0 009>;
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dcr-reg = <0x0d0 9>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1e 4 1f 4>; /* cascade */
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interrupts = <0x1e 4 0x1f 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-440ep";
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dcr-reg = <00e 002>;
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dcr-reg = <0x00e 2>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-440ep";
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dcr-reg = <00c 002>;
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dcr-reg = <0x00c 2>;
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};
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plb {
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@ -94,17 +95,17 @@
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SDRAM0: sdram {
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compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
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dcr-reg = <010 2>;
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dcr-reg = <0x010 2>;
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};
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DMA0: dma {
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compatible = "ibm,dma-440ep", "ibm,dma-440gp";
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dcr-reg = <100 027>;
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dcr-reg = <0x100 0x027>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
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dcr-reg = <180 62>;
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <4>;
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num-rx-chans = <2>;
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interrupt-parent = <&MAL0>;
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@ -112,8 +113,8 @@
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
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/*RXEOB*/ 1 &UIC0 b 4
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interrupt-map = </*TXEOB*/ 0 &UIC0 10 4
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/*RXEOB*/ 1 &UIC0 11 4
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/*SERR*/ 2 &UIC1 0 4
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/*TXDE*/ 3 &UIC1 1 4
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/*RXDE*/ 4 &UIC1 2 4>;
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@ -126,15 +127,15 @@
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/* Bamboo is oddball in the 44x world and doesn't use the ERPN
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* bits.
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*/
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ranges = <00000000 0 00000000 80000000
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80000000 0 80000000 80000000>;
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ranges = <0x00000000 0 0x00000000 0x80000000
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0x80000000 0 0x80000000 0x80000000>;
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interrupt-parent = <&UIC1>;
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interrupts = <7 4>;
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clock-frequency = <0>; /* Filled in by zImage */
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EBC0: ebc {
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compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
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dcr-reg = <012 2>;
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dcr-reg = <0x012 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by zImage */
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@ -145,10 +146,10 @@
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600300 8>;
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virtual-reg = <ef600300>;
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reg = <0xef600300 8>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <1c200>;
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current-speed = <0x1c200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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@ -156,8 +157,8 @@
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UART1: serial@ef600400 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600400 8>;
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virtual-reg = <ef600400>;
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reg = <0xef600400 8>;
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virtual-reg = <0xef600400>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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@ -167,8 +168,8 @@
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UART2: serial@ef600500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600500 8>;
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virtual-reg = <ef600500>;
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reg = <0xef600500 8>;
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virtual-reg = <0xef600500>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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@ -178,8 +179,8 @@
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UART3: serial@ef600600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600600 8>;
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virtual-reg = <ef600600>;
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reg = <0xef600600 8>;
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virtual-reg = <0xef600600>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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@ -191,26 +192,26 @@
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#size-cells = <0>;
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compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
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index = <0>;
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reg = <ef600700 14>;
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reg = <0xef600700 0x14>;
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interrupt-parent = <&UIC0>;
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interrupts = <2 4>;
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rtc@68 {
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compatible = "stm,m41t80";
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reg = <68>;
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reg = <0x68>;
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};
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};
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IIC1: i2c@ef600800 {
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compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
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index = <5>;
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reg = <ef600800 14>;
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reg = <0xef600800 0x14>;
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interrupt-parent = <&UIC0>;
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interrupts = <7 4>;
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};
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ZMII0: emac-zmii@ef600d00 {
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compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
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reg = <ef600d00 c>;
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reg = <0xef600d00 0xc>;
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};
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EMAC0: ethernet@ef600e00 {
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@ -218,16 +219,16 @@
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device_type = "network";
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compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
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interrupt-parent = <&UIC1>;
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interrupts = <1c 4 1d 4>;
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reg = <ef600e00 70>;
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interrupts = <0x1c 4 0x1d 4>;
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reg = <0xef600e00 0x70>;
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local-mac-address = [000000000000];
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mal-device = <&MAL0>;
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mal-tx-channel = <0 1>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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max-frame-size = <0x5dc>;
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rx-fifo-size = <0x1000>;
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tx-fifo-size = <0x800>;
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phy-mode = "rmii";
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phy-map = <00000000>;
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zmii-device = <&ZMII0>;
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@ -239,16 +240,16 @@
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device_type = "network";
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compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
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interrupt-parent = <&UIC1>;
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interrupts = <1e 4 1f 4>;
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reg = <ef600f00 70>;
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interrupts = <0x1e 4 0x1f 4>;
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reg = <0xef600f00 0x70>;
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local-mac-address = [000000000000];
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mal-device = <&MAL0>;
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mal-tx-channel = <2 3>;
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mal-rx-channel = <1>;
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cell-index = <1>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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max-frame-size = <0x5dc>;
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rx-fifo-size = <0x1000>;
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tx-fifo-size = <0x800>;
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phy-mode = "rmii";
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phy-map = <00000000>;
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zmii-device = <&ZMII0>;
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@ -256,9 +257,9 @@
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};
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usb@ef601000 {
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compatible = "ohci-be";
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reg = <ef601000 80>;
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reg = <0xef601000 0x80>;
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interrupts = <8 4 9 4>;
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interrupt-parent = < &UIC1 >;
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interrupt-parent = <&UIC1>;
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};
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};
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@ -269,20 +270,20 @@
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#address-cells = <3>;
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compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
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primary;
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reg = <0 eec00000 8 /* Config space access */
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0 eed00000 4 /* IACK */
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0 eed00000 4 /* Special cycle */
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0 ef400000 40>; /* Internal registers */
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reg = <0 0xeec00000 8 /* Config space access */
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0 0xeed00000 4 /* IACK */
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0 0xeed00000 4 /* Special cycle */
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0 0xef400000 0x40>; /* Internal registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed. Chip supports a second
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* IO range but we don't use it for now
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*/
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ranges = <02000000 0 a0000000 0 a0000000 0 20000000
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01000000 0 00000000 0 e8000000 0 00010000>;
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ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
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0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>;
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};
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};
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