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drm/radeon: add a check to wait_reg_mem command
WAIT_REG_MEM on register does not allow the use of PFP. Enforce this restriction when checking packets sent from userland. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2101,6 +2101,9 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
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ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
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ib[idx+2] = upper_32_bits(offset) & 0xff;
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} else if (idx_value & 0x100) {
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DRM_ERROR("cannot use PFP on REG wait\n");
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return -EINVAL;
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}
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break;
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case PACKET3_CP_DMA:
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@ -949,6 +949,11 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
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DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
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return -EINVAL;
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}
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/* bit 8 is me (0) or pfp (1) */
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if (wait_reg_mem_info & 0x100) {
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DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
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return -EINVAL;
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}
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/* waiting for value to be equal */
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if ((wait_reg_mem_info & 0x7) != 0x3) {
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DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
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@ -1847,6 +1852,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
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ib[idx+2] = upper_32_bits(offset) & 0xff;
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} else if (idx_value & 0x100) {
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DRM_ERROR("cannot use PFP on REG wait\n");
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return -EINVAL;
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}
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break;
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case PACKET3_CP_DMA:
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