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clk: ux500: Add armss clk and fixup smp_twd clk for u8500
The new armss clk is a prcmu_scalable_rate clk which represents the ARMSS clk. This then makes it possible to convert the smp_twd clk to a fixed factor clock type, using a fixed divider of 2 and with the armss clk as parent. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -206,16 +206,18 @@ void u8500_clk_init(void)
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clk_register_clkdev(clk, "dsilp2", "dsilink.2");
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clk_register_clkdev(clk, "dsilp2", "mcde");
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clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
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CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
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CLK_IGNORE_UNUSED);
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clk = clk_reg_prcmu_scalable_rate("armss", NULL,
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PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "armss", NULL);
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clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
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CLK_IGNORE_UNUSED, 1, 2);
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clk_register_clkdev(clk, NULL, "smp_twd");
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/*
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* FIXME: Add special handled PRCMU clocks here:
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* 1. clk_arm, use PRCMU_ARMCLK.
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* 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
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* 3. ab9540_clkout1yuv, see clkout0yuv
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* 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
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* 2. ab9540_clkout1yuv, see clkout0yuv
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*/
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/* PRCC P-clocks */
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