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https://github.com/FEX-Emu/linux.git
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Samsung clock patches for 3.17
1) non-critical fixes (without need to push to stable): d5e136a clk: samsung: Register clk provider only after registering its all clocks 305cfab clk: samsung: Make of_device_id array const e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend f65d518 clk: samsung: trivial: Correct typo in author's name 2) Exynos CLKOUT driver: 800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy 01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy 1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data 3) Clock hierarchy extensions: 17d3f1d clk: exynos4: Add PPMU IP block source clocks. ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data 4) ARM CLKDOWN functionality enablement for Exynos4 and 3250: 42773b2 clk: samsung: exynos4: Enable ARMCLK down feature 45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJT2kn8AAoJEIv3Hb8G/Xru1OMP/j6lh7aMyNm6E0mHFJd0Pfjy foe5N9RdQeRfoLySkItqJbBmgujkjjxstSpENCMp8VINlxxHfxi4Nl0bk34efy5f xYMVrmyZoB5dO4W/QmamGIiysD6aRhJ+kbwN+fai05/y+XUt8nUSTH7VdBabq9d3 2O1kRjOMhcdnGQgs/V2XK3SvX2+iUycNAi3JKv1ai1OtB8JiykCeN4FOJr2xPFkv CS5kZj+ofor3SZ6NnmJq52Uuto+ck9NLpp6ohCNlvf6PC52oGa/l1KU693r534Rf nbbNeCOEeByqXPMuL/SxAQzZOqbMRADef42X6tVTK6qpTx58Iep9LRybolYCrMor s4p92u9gsLsURQ85f02mYecnqLMEoeZb5p7sOmjZ0QuHWXm5PVkhIzOYweXEzFtE MeEcVIEiaSpqrm94s7iPYNXleTfLHvoi7jSRjfJayqffNuUeBMfKG6gkmYogU/Ou 9RrGsB+m8dyz/vqvqtRkZznOBaFblwqhSdeY2F+x9Onk/Bin3wzh/9NIge8HJk2P H62R1EUQePLCS9cZJS95jBmSAWRXPD6yaq4xIj2LTuN0uFhCO2FRxWW2eFu9OqE4 DfDIDA1S77aqMzIYjSUUis1yhf4RnSnqy2il5iFMsbiA0/19rYgLiyNrpym8AS+T +ErdKOkHjkwEUZbzobH6 =wCSD -----END PGP SIGNATURE----- Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung Samsung clock patches for 3.17 1) non-critical fixes (without need to push to stable): d5e136a clk: samsung: Register clk provider only after registering its all clocks 305cfab clk: samsung: Make of_device_id array const e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend f65d518 clk: samsung: trivial: Correct typo in author's name 2) Exynos CLKOUT driver: 800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy 01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy 1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data 3) Clock hierarchy extensions: 17d3f1d clk: exynos4: Add PPMU IP block source clocks. ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data 4) ARM CLKDOWN functionality enablement for Exynos4 and 3250: 42773b2 clk: samsung: exynos4: Enable ARMCLK down feature 45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
This commit is contained in:
Mike Turquette
commit
d7d3d26fa5
@ -12,8 +12,38 @@ Properties:
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- reg : offset and length of the register set.
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- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
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The single specifier cell is used as index to list of clocks
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provided by PMU, which is currently:
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0 : SoC clock output (CLKOUT pin)
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- clock-names : list of clock names for particular CLKOUT mux inputs in
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following format:
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"clkoutN", where N is a decimal number corresponding to
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CLKOUT mux control bits value for given input, e.g.
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"clkout0", "clkout7", "clkout15".
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- clocks : list of phandles and specifiers to all input clocks listed in
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clock-names property.
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Example :
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5250-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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#clock-cells = <1>;
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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};
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Example of clock consumer :
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usb3503: usb3503@08 {
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/* ... */
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clock-names = "refclk";
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clocks = <&pmu_system_controller 0>;
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/* ... */
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};
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@ -31,6 +31,16 @@
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pinctrl2 = &pinctrl_2;
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};
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pmu_system_controller: system-controller@10020000 {
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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#clock-cells = <1>;
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x20000>;
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@ -139,6 +139,13 @@
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pmu_system_controller: system-controller@10020000 {
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compatible = "samsung,exynos4212-pmu", "syscon";
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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#clock-cells = <1>;
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};
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g2d@10800000 {
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@ -191,6 +191,9 @@
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5250-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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clock-names = "clkout16";
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clocks = <&clock CLK_FIN_PLL>;
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#clock-cells = <1>;
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};
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sysreg_system_controller: syscon@10050000 {
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@ -724,6 +724,9 @@
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5420-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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clock-names = "clkout16";
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clocks = <&clock CLK_FIN_PLL>;
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#clock-cells = <1>;
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};
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sysreg_system_controller: syscon@10050000 {
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@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
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obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
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153
drivers/clk/samsung/clk-exynos-clkout.c
Normal file
153
drivers/clk/samsung/clk-exynos-clkout.c
Normal file
@ -0,0 +1,153 @@
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Tomasz Figa <t.figa@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Clock driver for Exynos clock output
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#define EXYNOS_CLKOUT_NR_CLKS 1
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#define EXYNOS_CLKOUT_PARENTS 32
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#define EXYNOS_PMU_DEBUG_REG 0xa00
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#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
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#define EXYNOS_CLKOUT_MUX_SHIFT 8
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#define EXYNOS4_CLKOUT_MUX_MASK 0xf
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#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
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struct exynos_clkout {
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struct clk_gate gate;
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struct clk_mux mux;
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spinlock_t slock;
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struct clk_onecell_data data;
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struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
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void __iomem *reg;
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u32 pmu_debug_save;
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};
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static struct exynos_clkout *clkout;
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static int exynos_clkout_suspend(void)
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{
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clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
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return 0;
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}
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static void exynos_clkout_resume(void)
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{
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writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
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}
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static struct syscore_ops exynos_clkout_syscore_ops = {
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.suspend = exynos_clkout_suspend,
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.resume = exynos_clkout_resume,
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};
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static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
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{
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const char *parent_names[EXYNOS_CLKOUT_PARENTS];
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struct clk *parents[EXYNOS_CLKOUT_PARENTS];
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int parent_count;
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int ret;
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int i;
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clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
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if (!clkout)
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return;
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spin_lock_init(&clkout->slock);
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parent_count = 0;
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for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
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char name[] = "clkoutXX";
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snprintf(name, sizeof(name), "clkout%d", i);
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parents[i] = of_clk_get_by_name(node, name);
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if (IS_ERR(parents[i])) {
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parent_names[i] = "none";
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continue;
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}
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parent_names[i] = __clk_get_name(parents[i]);
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parent_count = i + 1;
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}
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if (!parent_count)
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goto free_clkout;
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clkout->reg = of_iomap(node, 0);
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if (!clkout->reg)
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goto clks_put;
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clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
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clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
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clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
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clkout->gate.lock = &clkout->slock;
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clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
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clkout->mux.mask = mux_mask;
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clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
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clkout->mux.lock = &clkout->slock;
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clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
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parent_names, parent_count, &clkout->mux.hw,
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&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
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&clk_gate_ops, CLK_SET_RATE_PARENT
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| CLK_SET_RATE_NO_REPARENT);
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if (IS_ERR(clkout->clk_table[0]))
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goto err_unmap;
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clkout->data.clks = clkout->clk_table;
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clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
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ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
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if (ret)
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goto err_clk_unreg;
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register_syscore_ops(&exynos_clkout_syscore_ops);
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return;
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err_clk_unreg:
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clk_unregister(clkout->clk_table[0]);
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err_unmap:
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iounmap(clkout->reg);
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clks_put:
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for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
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if (!IS_ERR(parents[i]))
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clk_put(parents[i]);
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free_clkout:
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kfree(clkout);
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pr_err("%s: failed to register clkout clock\n", __func__);
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}
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static void __init exynos4_clkout_init(struct device_node *node)
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{
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exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
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}
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CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu",
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exynos4_clkout_init);
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CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
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exynos4_clkout_init);
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CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
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exynos4_clkout_init);
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static void __init exynos5_clkout_init(struct device_node *node)
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{
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exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
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}
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CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
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exynos5_clkout_init);
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CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
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exynos5_clkout_init);
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@ -87,6 +87,22 @@
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#define SRC_CPU 0x14200
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#define DIV_CPU0 0x14500
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#define DIV_CPU1 0x14504
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#define PWR_CTRL1 0x15020
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#define PWR_CTRL2 0x15024
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/* Below definitions are used for PWR_CTRL settings */
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#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
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#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
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#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
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#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
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#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
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#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
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#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
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#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
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#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
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#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
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#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
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#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
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/* list of PLLs to be registered */
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enum exynos3250_plls {
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@ -168,6 +184,8 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
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SRC_CPU,
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DIV_CPU0,
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DIV_CPU1,
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PWR_CTRL1,
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PWR_CTRL2,
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};
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static int exynos3250_clk_suspend(void)
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@ -748,6 +766,27 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
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UPLL_LOCK, UPLL_CON0, NULL),
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};
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static void __init exynos3_core_down_clock(void)
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{
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unsigned int tmp;
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/*
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* Enable arm clock down (in idle) and set arm divider
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* ratios in WFI/WFE state.
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*/
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tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
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PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
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PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
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PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
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__raw_writel(tmp, reg_base + PWR_CTRL1);
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/*
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* Disable the clock up feature on Exynos4x12, in case it was
|
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* enabled by bootloader.
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*/
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__raw_writel(0x0, reg_base + PWR_CTRL2);
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}
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static void __init exynos3250_cmu_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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@ -775,6 +814,10 @@ static void __init exynos3250_cmu_init(struct device_node *np)
|
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samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
|
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samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
|
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|
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exynos3_core_down_clock();
|
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|
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exynos3250_clk_sleep_init();
|
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|
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samsung_clk_of_add_provider(np, ctx);
|
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}
|
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CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
|
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|
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@ -25,10 +25,12 @@
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#define DIV_LEFTBUS 0x4500
|
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#define GATE_IP_LEFTBUS 0x4800
|
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#define E4X12_GATE_IP_IMAGE 0x4930
|
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#define CLKOUT_CMU_LEFTBUS 0x4a00
|
||||
#define SRC_RIGHTBUS 0x8200
|
||||
#define DIV_RIGHTBUS 0x8500
|
||||
#define GATE_IP_RIGHTBUS 0x8800
|
||||
#define E4X12_GATE_IP_PERIR 0x8960
|
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#define CLKOUT_CMU_RIGHTBUS 0x8a00
|
||||
#define EPLL_LOCK 0xc010
|
||||
#define VPLL_LOCK 0xc020
|
||||
#define EPLL_CON0 0xc110
|
||||
@ -98,6 +100,7 @@
|
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#define GATE_IP_PERIL 0xc950
|
||||
#define E4210_GATE_IP_PERIR 0xc960
|
||||
#define GATE_BLOCK 0xc970
|
||||
#define CLKOUT_CMU_TOP 0xca00
|
||||
#define E4X12_MPLL_LOCK 0x10008
|
||||
#define E4X12_MPLL_CON0 0x10108
|
||||
#define SRC_DMC 0x10200
|
||||
@ -105,6 +108,7 @@
|
||||
#define DIV_DMC0 0x10500
|
||||
#define DIV_DMC1 0x10504
|
||||
#define GATE_IP_DMC 0x10900
|
||||
#define CLKOUT_CMU_DMC 0x10a00
|
||||
#define APLL_LOCK 0x14000
|
||||
#define E4210_MPLL_LOCK 0x14008
|
||||
#define APLL_CON0 0x14100
|
||||
@ -114,11 +118,28 @@
|
||||
#define DIV_CPU1 0x14504
|
||||
#define GATE_SCLK_CPU 0x14800
|
||||
#define GATE_IP_CPU 0x14900
|
||||
#define CLKOUT_CMU_CPU 0x14a00
|
||||
#define PWR_CTRL1 0x15020
|
||||
#define E4X12_PWR_CTRL2 0x15024
|
||||
#define E4X12_DIV_ISP0 0x18300
|
||||
#define E4X12_DIV_ISP1 0x18304
|
||||
#define E4X12_GATE_ISP0 0x18800
|
||||
#define E4X12_GATE_ISP1 0x18804
|
||||
|
||||
/* Below definitions are used for PWR_CTRL settings */
|
||||
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
|
||||
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
|
||||
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
|
||||
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
|
||||
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
|
||||
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
|
||||
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
|
||||
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
|
||||
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
|
||||
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
/* the exynos4 soc type */
|
||||
enum exynos4_soc {
|
||||
EXYNOS4210,
|
||||
@ -155,6 +176,7 @@ static unsigned long exynos4210_clk_save[] __initdata = {
|
||||
E4210_GATE_IP_LCD1,
|
||||
E4210_GATE_IP_PERIR,
|
||||
E4210_MPLL_CON0,
|
||||
PWR_CTRL1,
|
||||
};
|
||||
|
||||
static unsigned long exynos4x12_clk_save[] __initdata = {
|
||||
@ -164,6 +186,8 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
|
||||
E4X12_DIV_ISP,
|
||||
E4X12_DIV_CAM1,
|
||||
E4X12_MPLL_CON0,
|
||||
PWR_CTRL1,
|
||||
E4X12_PWR_CTRL2,
|
||||
};
|
||||
|
||||
static unsigned long exynos4_clk_pll_regs[] __initdata = {
|
||||
@ -242,6 +266,11 @@ static unsigned long exynos4_clk_regs[] __initdata = {
|
||||
DIV_CPU1,
|
||||
GATE_SCLK_CPU,
|
||||
GATE_IP_CPU,
|
||||
CLKOUT_CMU_LEFTBUS,
|
||||
CLKOUT_CMU_RIGHTBUS,
|
||||
CLKOUT_CMU_TOP,
|
||||
CLKOUT_CMU_DMC,
|
||||
CLKOUT_CMU_CPU,
|
||||
};
|
||||
|
||||
static const struct samsung_clk_reg_dump src_mask_suspend[] = {
|
||||
@ -397,10 +426,32 @@ PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
|
||||
"sclk_epll", "sclk_vpll", };
|
||||
PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
|
||||
PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
|
||||
PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
|
||||
"sclk_usbphy1", "sclk_hdmiphy", "none",
|
||||
"sclk_epll", "sclk_vpll" };
|
||||
PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
|
||||
"div_gdl", "div_gpl" };
|
||||
PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
|
||||
"div_gdr", "div_gpr" };
|
||||
PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
|
||||
"sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
|
||||
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
|
||||
"aclk160", "aclk133", "aclk200", "aclk100",
|
||||
"sclk_mfc", "sclk_g3d", "sclk_g2d",
|
||||
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
|
||||
"s_rxbyteclkhs0_4l" };
|
||||
PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
|
||||
"div_dphy", "none", "div_pwi" };
|
||||
PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
|
||||
"none", "arm_clk_div_2", "div_corem0",
|
||||
"div_corem1", "div_corem0", "div_atb",
|
||||
"div_periph", "div_pclk_dbg", "div_hpm" };
|
||||
|
||||
/* Exynos 4x12-specific parent groups */
|
||||
PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
|
||||
PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
|
||||
PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
|
||||
PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
|
||||
PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
|
||||
PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
|
||||
"none", "sclk_hdmiphy", "mout_mpll_user_t",
|
||||
@ -418,6 +469,32 @@ PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
|
||||
PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
|
||||
PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
|
||||
PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
|
||||
PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
|
||||
"none", "sclk_hdmiphy", "sclk_mpll",
|
||||
"sclk_epll", "sclk_vpll" };
|
||||
PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
|
||||
"div_gdl", "div_gpl" };
|
||||
PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
|
||||
"div_gdr", "div_gpr" };
|
||||
PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
|
||||
"sclk_usbphy0", "none", "sclk_hdmiphy",
|
||||
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
|
||||
"aclk160", "aclk133", "aclk200", "aclk100",
|
||||
"sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
|
||||
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
|
||||
"s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
|
||||
"rx_half_byte_clk_csis1", "div_jpeg",
|
||||
"sclk_pwm_isp", "sclk_spi0_isp",
|
||||
"sclk_spi1_isp", "sclk_uart_isp",
|
||||
"sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
|
||||
"sclk_pcm0" };
|
||||
PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
|
||||
"div_dmc", "div_dphy", "fout_mpll_div_2",
|
||||
"div_pwi", "none", "div_c2c", "div_c2c_aclk" };
|
||||
PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
|
||||
"arm_clk_div_2", "div_corem0", "div_corem1",
|
||||
"div_cores", "div_atb", "div_periph",
|
||||
"div_pclk_dbg", "div_hpm" };
|
||||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
|
||||
@ -436,6 +513,24 @@ static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
|
||||
FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
|
||||
FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
|
||||
FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
|
||||
FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
|
||||
FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
|
||||
FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
|
||||
FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
|
||||
};
|
||||
|
||||
/* list of mux clocks supported in all exynos4 soc's */
|
||||
static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
|
||||
MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
@ -451,6 +546,9 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
|
||||
MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
|
||||
MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
|
||||
|
||||
MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
|
||||
MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
|
||||
};
|
||||
|
||||
/* list of mux clocks supported in exynos4210 soc */
|
||||
@ -459,6 +557,14 @@ static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
|
||||
MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
|
||||
CLKOUT_CMU_LEFTBUS, 0, 5),
|
||||
|
||||
MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
|
||||
MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
|
||||
CLKOUT_CMU_RIGHTBUS, 0, 5),
|
||||
|
||||
MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
|
||||
MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
|
||||
MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
|
||||
@ -472,6 +578,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
|
||||
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
|
||||
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
|
||||
MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
|
||||
MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
|
||||
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
|
||||
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
|
||||
@ -503,12 +610,30 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
|
||||
MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
|
||||
MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
|
||||
MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
|
||||
|
||||
MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
|
||||
MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
|
||||
|
||||
MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
|
||||
};
|
||||
|
||||
/* list of mux clocks supported in exynos4x12 soc */
|
||||
static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
|
||||
MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
|
||||
MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
|
||||
CLKOUT_CMU_LEFTBUS, 0, 5),
|
||||
|
||||
MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
|
||||
MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
|
||||
MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
|
||||
CLKOUT_CMU_RIGHTBUS, 0, 5),
|
||||
|
||||
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
|
||||
SRC_CPU, 24, 1),
|
||||
MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
|
||||
|
||||
MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
|
||||
MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
|
||||
MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
|
||||
@ -531,6 +656,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
|
||||
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
|
||||
MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
|
||||
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
|
||||
MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
|
||||
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
|
||||
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
|
||||
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
|
||||
@ -565,15 +691,39 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
|
||||
MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
|
||||
MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
|
||||
MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
|
||||
|
||||
MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
|
||||
MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
|
||||
MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
|
||||
MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
|
||||
MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
|
||||
MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
|
||||
};
|
||||
|
||||
/* list of divider clocks supported in all exynos4 soc's */
|
||||
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
|
||||
DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
|
||||
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
|
||||
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
|
||||
CLKOUT_CMU_LEFTBUS, 8, 6),
|
||||
|
||||
DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
|
||||
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
|
||||
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
|
||||
CLKOUT_CMU_RIGHTBUS, 8, 6),
|
||||
|
||||
DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
|
||||
DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
|
||||
DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
|
||||
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
|
||||
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
|
||||
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
|
||||
DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
|
||||
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
|
||||
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
|
||||
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
|
||||
|
||||
DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
|
||||
DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
|
||||
DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
|
||||
@ -631,6 +781,16 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
|
||||
|
||||
DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
|
||||
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
|
||||
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
|
||||
DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
|
||||
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
|
||||
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
|
||||
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
|
||||
DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
|
||||
};
|
||||
|
||||
/* list of divider clocks supported in exynos4210 soc */
|
||||
@ -671,6 +831,8 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
|
||||
DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
|
||||
8, 3, CLK_GET_RATE_NOCACHE, 0),
|
||||
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
|
||||
DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
|
||||
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
|
||||
};
|
||||
|
||||
/* list of gate clocks supported in all exynos4 soc's */
|
||||
@ -680,6 +842,8 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
|
||||
* the device name and clock alias names specified below for some
|
||||
* of the clocks can be removed.
|
||||
*/
|
||||
GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
|
||||
GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
|
||||
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
|
||||
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
|
||||
0),
|
||||
@ -695,11 +859,13 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
|
||||
GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
|
||||
GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
|
||||
GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
|
||||
GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
|
||||
GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
|
||||
GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
|
||||
GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
|
||||
GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
|
||||
GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
|
||||
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
@ -781,19 +947,24 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
|
||||
0, 0),
|
||||
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
|
||||
0, 0),
|
||||
GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
|
||||
GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
|
||||
GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
|
||||
GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
|
||||
0, 0),
|
||||
GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
|
||||
GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
|
||||
0, 0),
|
||||
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
|
||||
0, 0),
|
||||
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
|
||||
GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
|
||||
GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
|
||||
0, 0),
|
||||
GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
|
||||
0, 0),
|
||||
GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
|
||||
GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
|
||||
0, 0),
|
||||
GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
|
||||
@ -806,6 +977,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
|
||||
0, 0),
|
||||
GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
|
||||
0, 0),
|
||||
GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
|
||||
GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
|
||||
0, 0),
|
||||
GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
|
||||
@ -852,6 +1024,21 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
|
||||
0, 0),
|
||||
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
|
||||
0, 0),
|
||||
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
|
||||
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
|
||||
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
|
||||
GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
|
||||
|
||||
GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
|
||||
CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
|
||||
CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
|
||||
CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
|
||||
CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
|
||||
CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
/* list of gate clocks supported in exynos4210 soc */
|
||||
@ -863,6 +1050,9 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
|
||||
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
|
||||
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
|
||||
0),
|
||||
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
|
||||
0),
|
||||
GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
|
||||
GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
|
||||
GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
|
||||
GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
|
||||
@ -906,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
|
||||
GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
|
||||
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
|
||||
0),
|
||||
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
|
||||
0),
|
||||
GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
|
||||
GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
|
||||
GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
|
||||
@ -1062,7 +1254,7 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
|
||||
|
||||
}
|
||||
|
||||
static struct of_device_id ext_clk_match[] __initdata = {
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
|
||||
{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
|
||||
{},
|
||||
@ -1164,6 +1356,32 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
|
||||
VPLL_LOCK, VPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
/*
|
||||
* Enable arm clock down (in idle) and set arm divider
|
||||
* ratios in WFI/WFE state.
|
||||
*/
|
||||
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
|
||||
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
|
||||
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
|
||||
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
|
||||
/* On Exynos4412 enable it also on core 2 and 3 */
|
||||
if (num_possible_cpus() == 4)
|
||||
tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
|
||||
PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
|
||||
__raw_writel(tmp, reg_base + PWR_CTRL1);
|
||||
|
||||
/*
|
||||
* Disable the clock up feature on Exynos4x12, in case it was
|
||||
* enabled by bootloader.
|
||||
*/
|
||||
if (exynos4_soc == EXYNOS4X12)
|
||||
__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
|
||||
}
|
||||
|
||||
/* register exynos4 clocks */
|
||||
static void __init exynos4_clk_init(struct device_node *np,
|
||||
enum exynos4_soc soc)
|
||||
@ -1224,6 +1442,8 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
ARRAY_SIZE(exynos4_div_clks));
|
||||
samsung_clk_register_gate(ctx, exynos4_gate_clks,
|
||||
ARRAY_SIZE(exynos4_gate_clks));
|
||||
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4_fixed_factor_clks));
|
||||
|
||||
if (exynos4_soc == EXYNOS4210) {
|
||||
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
|
||||
@ -1236,6 +1456,9 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
ARRAY_SIZE(exynos4210_gate_clks));
|
||||
samsung_clk_register_alias(ctx, exynos4210_aliases,
|
||||
ARRAY_SIZE(exynos4210_aliases));
|
||||
samsung_clk_register_fixed_factor(ctx,
|
||||
exynos4210_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4210_fixed_factor_clks));
|
||||
} else {
|
||||
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
|
||||
ARRAY_SIZE(exynos4x12_mux_clks));
|
||||
@ -1245,13 +1468,19 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
ARRAY_SIZE(exynos4x12_gate_clks));
|
||||
samsung_clk_register_alias(ctx, exynos4x12_aliases,
|
||||
ARRAY_SIZE(exynos4x12_aliases));
|
||||
samsung_clk_register_fixed_factor(ctx,
|
||||
exynos4x12_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
|
||||
}
|
||||
|
||||
samsung_clk_register_alias(ctx, exynos4_aliases,
|
||||
ARRAY_SIZE(exynos4_aliases));
|
||||
|
||||
exynos4_core_down_clock(soc);
|
||||
exynos4_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
|
||||
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
|
||||
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
|
||||
|
||||
@ -748,7 +748,7 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
|
||||
VPLL_LOCK, VPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
static struct of_device_id ext_clk_match[] __initdata = {
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
|
||||
{ },
|
||||
};
|
||||
@ -820,6 +820,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
||||
|
||||
exynos5250_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
|
||||
_get_rate("div_arm2"));
|
||||
}
|
||||
|
||||
@ -206,6 +206,8 @@ void __init exynos5260_cmu_register_one(struct device_node *np,
|
||||
if (cmu->clk_regs)
|
||||
exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
|
||||
cmu->nr_clk_regs);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -204,6 +204,8 @@ static void __init exynos5410_clk_init(struct device_node *np)
|
||||
samsung_clk_register_gate(ctx, exynos5410_gate_clks,
|
||||
ARRAY_SIZE(exynos5410_gate_clks));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_debug("Exynos5410: clock setup completed.\n");
|
||||
}
|
||||
CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
#define GATE_BUS_CPU 0x700
|
||||
#define GATE_SCLK_CPU 0x800
|
||||
#define CLKOUT_CMU_CPU 0xa00
|
||||
#define SRC_MASK_CPERI 0x4300
|
||||
#define GATE_IP_G2D 0x8800
|
||||
#define CPLL_LOCK 0x10020
|
||||
#define DPLL_LOCK 0x10030
|
||||
@ -70,6 +71,8 @@
|
||||
#define SRC_TOP11 0x10284
|
||||
#define SRC_TOP12 0x10288
|
||||
#define SRC_TOP13 0x1028c /* 5800 specific */
|
||||
#define SRC_MASK_TOP0 0x10300
|
||||
#define SRC_MASK_TOP1 0x10304
|
||||
#define SRC_MASK_TOP2 0x10308
|
||||
#define SRC_MASK_TOP7 0x1031c
|
||||
#define SRC_MASK_DISP10 0x1032c
|
||||
@ -77,6 +80,7 @@
|
||||
#define SRC_MASK_FSYS 0x10340
|
||||
#define SRC_MASK_PERIC0 0x10350
|
||||
#define SRC_MASK_PERIC1 0x10354
|
||||
#define SRC_MASK_ISP 0x10370
|
||||
#define DIV_TOP0 0x10500
|
||||
#define DIV_TOP1 0x10504
|
||||
#define DIV_TOP2 0x10508
|
||||
@ -98,6 +102,7 @@
|
||||
#define DIV2_RATIO0 0x10590
|
||||
#define DIV4_RATIO 0x105a0
|
||||
#define GATE_BUS_TOP 0x10700
|
||||
#define GATE_BUS_DISP1 0x10728
|
||||
#define GATE_BUS_GEN 0x1073c
|
||||
#define GATE_BUS_FSYS0 0x10740
|
||||
#define GATE_BUS_FSYS2 0x10748
|
||||
@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
|
||||
SRC_MASK_FSYS,
|
||||
SRC_MASK_PERIC0,
|
||||
SRC_MASK_PERIC1,
|
||||
SRC_MASK_TOP0,
|
||||
SRC_MASK_TOP1,
|
||||
SRC_MASK_MAU,
|
||||
SRC_MASK_ISP,
|
||||
SRC_ISP,
|
||||
DIV_TOP0,
|
||||
DIV_TOP1,
|
||||
@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
|
||||
SCLK_DIV_ISP1,
|
||||
DIV2_RATIO0,
|
||||
DIV4_RATIO,
|
||||
GATE_BUS_DISP1,
|
||||
GATE_BUS_TOP,
|
||||
GATE_BUS_GEN,
|
||||
GATE_BUS_FSYS0,
|
||||
@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = {
|
||||
GATE_IP_CAM,
|
||||
};
|
||||
|
||||
static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
|
||||
{ .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
|
||||
{ .offset = SRC_MASK_TOP0, .value = 0x11111111, },
|
||||
{ .offset = SRC_MASK_TOP1, .value = 0x11101111, },
|
||||
{ .offset = SRC_MASK_TOP2, .value = 0x11111110, },
|
||||
{ .offset = SRC_MASK_TOP7, .value = 0x00111100, },
|
||||
{ .offset = SRC_MASK_DISP10, .value = 0x11111110, },
|
||||
{ .offset = SRC_MASK_MAU, .value = 0x10000000, },
|
||||
{ .offset = SRC_MASK_FSYS, .value = 0x11111110, },
|
||||
{ .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
|
||||
{ .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
|
||||
{ .offset = SRC_MASK_ISP, .value = 0x11111000, },
|
||||
{ .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
|
||||
{ .offset = GATE_IP_PERIC, .value = 0xffffffff, },
|
||||
};
|
||||
|
||||
static int exynos5420_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, exynos5x_save,
|
||||
@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void)
|
||||
samsung_clk_save(reg_base, exynos5800_save,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
|
||||
samsung_clk_restore(reg_base, exynos5420_set_clksrc,
|
||||
ARRAY_SIZE(exynos5420_set_clksrc));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1167,6 +1196,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
|
||||
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
|
||||
PLL_35XX_RATE(2000000000, 250, 3, 0),
|
||||
PLL_35XX_RATE(1900000000, 475, 6, 0),
|
||||
PLL_35XX_RATE(1800000000, 225, 3, 0),
|
||||
PLL_35XX_RATE(1700000000, 425, 6, 0),
|
||||
PLL_35XX_RATE(1600000000, 200, 3, 0),
|
||||
PLL_35XX_RATE(1500000000, 250, 4, 0),
|
||||
PLL_35XX_RATE(1400000000, 175, 3, 0),
|
||||
PLL_35XX_RATE(1300000000, 325, 6, 0),
|
||||
PLL_35XX_RATE(1200000000, 200, 2, 1),
|
||||
PLL_35XX_RATE(1100000000, 275, 3, 1),
|
||||
PLL_35XX_RATE(1000000000, 250, 3, 1),
|
||||
PLL_35XX_RATE(900000000, 150, 2, 1),
|
||||
PLL_35XX_RATE(800000000, 200, 3, 1),
|
||||
PLL_35XX_RATE(700000000, 175, 3, 1),
|
||||
PLL_35XX_RATE(600000000, 200, 2, 2),
|
||||
PLL_35XX_RATE(500000000, 250, 3, 2),
|
||||
PLL_35XX_RATE(400000000, 200, 3, 2),
|
||||
PLL_35XX_RATE(300000000, 200, 2, 3),
|
||||
PLL_35XX_RATE(200000000, 200, 3, 3),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
|
||||
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
|
||||
APLL_CON0, NULL),
|
||||
@ -1192,7 +1243,7 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
|
||||
KPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
static struct of_device_id ext_clk_match[] __initdata = {
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
|
||||
{ },
|
||||
};
|
||||
@ -1220,6 +1271,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
||||
if (_get_rate("fin_pll") == 24 * MHZ) {
|
||||
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
}
|
||||
|
||||
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
|
||||
reg_base);
|
||||
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
|
||||
@ -1251,6 +1308,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
}
|
||||
|
||||
exynos5420_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init exynos5420_clk_init(struct device_node *np)
|
||||
|
||||
@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
|
||||
GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
};
|
||||
|
||||
static struct of_device_id ext_clk_match[] __initdata = {
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
|
||||
{},
|
||||
};
|
||||
@ -123,6 +123,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
||||
samsung_clk_register_gate(ctx, exynos5440_gate_clks,
|
||||
ARRAY_SIZE(exynos5440_gate_clks));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
|
||||
pr_info("exynos5440 clock initialization complete\n");
|
||||
}
|
||||
|
||||
@ -466,6 +466,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
}
|
||||
|
||||
s3c2410_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init s3c2410_clk_init(struct device_node *np)
|
||||
|
||||
@ -265,6 +265,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
ARRAY_SIZE(s3c2412_aliases));
|
||||
|
||||
s3c2412_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init s3c2412_clk_init(struct device_node *np)
|
||||
|
||||
@ -445,6 +445,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
}
|
||||
|
||||
s3c2443_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init s3c2416_clk_init(struct device_node *np)
|
||||
|
||||
@ -518,6 +518,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
||||
ARRAY_SIZE(s3c64xx_clock_aliases));
|
||||
s3c64xx_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
|
||||
"\tepll = %lu, arm_clk = %lu\n",
|
||||
is_s3c6400 ? "S3C6400" : "S3C6410",
|
||||
|
||||
@ -53,7 +53,6 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk **clk_table;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
|
||||
@ -72,17 +71,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
|
||||
ctx->clk_data.clk_num = nr_clks;
|
||||
spin_lock_init(&ctx->lock);
|
||||
|
||||
if (!np)
|
||||
return ctx;
|
||||
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&ctx->clk_data);
|
||||
if (ret)
|
||||
panic("could not register clock provide\n");
|
||||
|
||||
return ctx;
|
||||
}
|
||||
|
||||
void __init samsung_clk_of_add_provider(struct device_node *np,
|
||||
struct samsung_clk_provider *ctx)
|
||||
{
|
||||
if (np) {
|
||||
if (of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&ctx->clk_data))
|
||||
panic("could not register clk provider\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* add a clock instance to the clock lookup table used for dt based lookup */
|
||||
void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
|
||||
unsigned int id)
|
||||
@ -284,7 +285,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
|
||||
void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
struct of_device_id *clk_matches)
|
||||
const struct of_device_id *clk_matches)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *clk_np;
|
||||
|
||||
@ -327,11 +327,13 @@ struct samsung_pll_clock {
|
||||
extern struct samsung_clk_provider *__init samsung_clk_init(
|
||||
struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks);
|
||||
extern void __init samsung_clk_of_add_provider(struct device_node *np,
|
||||
struct samsung_clk_provider *ctx);
|
||||
extern void __init samsung_clk_of_register_fixed_ext(
|
||||
struct samsung_clk_provider *ctx,
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
struct of_device_id *clk_matches);
|
||||
const struct of_device_id *clk_matches);
|
||||
|
||||
extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
|
||||
struct clk *clk, unsigned int id);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -34,6 +34,11 @@
|
||||
#define CLK_MOUT_CORE 19
|
||||
#define CLK_MOUT_APLL 20
|
||||
#define CLK_SCLK_HDMIPHY 22
|
||||
#define CLK_OUT_DMC 23
|
||||
#define CLK_OUT_TOP 24
|
||||
#define CLK_OUT_LEFTBUS 25
|
||||
#define CLK_OUT_RIGHTBUS 26
|
||||
#define CLK_OUT_CPU 27
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_FIMC0 128
|
||||
@ -230,6 +235,24 @@
|
||||
#define CLK_MOUT_G3D 394
|
||||
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
|
||||
|
||||
/* gate clocks - ppmu */
|
||||
#define CLK_PPMULEFT 400
|
||||
#define CLK_PPMURIGHT 401
|
||||
#define CLK_PPMUCAMIF 402
|
||||
#define CLK_PPMUTV 403
|
||||
#define CLK_PPMUMFC_L 404
|
||||
#define CLK_PPMUMFC_R 405
|
||||
#define CLK_PPMUG3D 406
|
||||
#define CLK_PPMUIMAGE 407
|
||||
#define CLK_PPMULCD0 408
|
||||
#define CLK_PPMULCD1 409 /* Exynos4210 only */
|
||||
#define CLK_PPMUFILE 410
|
||||
#define CLK_PPMUGPS 411
|
||||
#define CLK_PPMUDMC0 412
|
||||
#define CLK_PPMUDMC1 413
|
||||
#define CLK_PPMUCPU 414
|
||||
#define CLK_PPMUACP 415
|
||||
|
||||
/* div clocks */
|
||||
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user