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https://github.com/FEX-Emu/linux.git
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Merge branch 'for-florian' of git://gitorious.org/linux-omap-dss2/linux into fbdev-next
Conflicts: drivers/video/omap2/dss/core.c drivers/video/omap2/dss/dispc.c
This commit is contained in:
Florian Tobias Schandinat
commit
d9053b4879
@ -37,6 +37,7 @@
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#define DISPC_CONTROL 0x0040
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#define DISPC_CONTROL2 0x0238
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#define DISPC_CONTROL3 0x0848
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#define DISPC_IRQSTATUS 0x0018
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#define DSS_SYSCONFIG 0x10
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@ -52,6 +53,7 @@
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#define EVSYNC_EVEN_IRQ_SHIFT 2
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#define EVSYNC_ODD_IRQ_SHIFT 3
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#define FRAMEDONE2_IRQ_SHIFT 22
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#define FRAMEDONE3_IRQ_SHIFT 30
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#define FRAMEDONETV_IRQ_SHIFT 24
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/*
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@ -376,7 +378,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
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static void dispc_disable_outputs(void)
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{
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u32 v, irq_mask = 0;
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bool lcd_en, digit_en, lcd2_en = false;
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bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
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int i;
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struct omap_dss_dispc_dev_attr *da;
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struct omap_hwmod *oh;
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@ -405,7 +407,13 @@ static void dispc_disable_outputs(void)
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lcd2_en = v & LCD_EN_MASK;
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}
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if (!(lcd_en | digit_en | lcd2_en))
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/* store value of LCDENABLE for LCD3 */
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if (da->manager_count > 3) {
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v = omap_hwmod_read(oh, DISPC_CONTROL3);
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lcd3_en = v & LCD_EN_MASK;
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}
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if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
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return; /* no managers currently enabled */
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/*
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@ -426,10 +434,12 @@ static void dispc_disable_outputs(void)
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if (lcd2_en)
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irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
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if (lcd3_en)
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irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
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/*
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* clear any previous FRAMEDONE, FRAMEDONETV,
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* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
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* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
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*/
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omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
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@ -445,12 +455,19 @@ static void dispc_disable_outputs(void)
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omap_hwmod_write(v, oh, DISPC_CONTROL2);
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}
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/* disable LCD3 manager */
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if (da->manager_count > 3) {
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v = omap_hwmod_read(oh, DISPC_CONTROL3);
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v &= ~LCD_EN_MASK;
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omap_hwmod_write(v, oh, DISPC_CONTROL3);
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}
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i = 0;
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while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
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irq_mask) {
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i++;
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if (i > FRAMEDONE_IRQ_TIMEOUT) {
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pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
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pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
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break;
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}
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mdelay(1);
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@ -487,6 +487,13 @@ static struct omap_video_timings acx_panel_timings = {
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.vfp = 3,
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.vsw = 3,
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.vbp = 4,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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};
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static int acx_panel_probe(struct omap_dss_device *dssdev)
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@ -498,8 +505,7 @@ static int acx_panel_probe(struct omap_dss_device *dssdev)
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struct backlight_properties props;
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dev_dbg(&dssdev->dev, "%s\n", __func__);
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dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS;
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/* FIXME AC bias ? */
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dssdev->panel.timings = acx_panel_timings;
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@ -40,12 +40,6 @@
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struct panel_config {
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struct omap_video_timings timings;
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int acbi; /* ac-bias pin transitions per interrupt */
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/* Unit: line clocks */
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int acb; /* ac-bias pin frequency */
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enum omap_panel_config config;
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int power_on_delay;
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int power_off_delay;
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@ -73,11 +67,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 11,
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.vfp = 3,
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.vbp = 2,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_LOW,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
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.power_on_delay = 50,
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.power_off_delay = 100,
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.name = "sharp_lq",
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@ -98,11 +94,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 1,
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.vfp = 1,
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.vbp = 1,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x28,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.power_on_delay = 50,
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.power_off_delay = 100,
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.name = "sharp_ls",
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@ -123,12 +121,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vfp = 4,
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.vsw = 2,
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.vbp = 2,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
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OMAP_DSS_LCD_ONOFF,
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.power_on_delay = 0,
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.power_off_delay = 0,
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.name = "toppoly_tdo35s",
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@ -149,11 +148,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vfp = 4,
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.vsw = 10,
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.vbp = 12 - 10,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.power_on_delay = 0,
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.power_off_delay = 0,
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.name = "samsung_lte430wq_f0c",
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@ -174,11 +175,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 2,
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.vfp = 4,
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.vbp = 11,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.power_on_delay = 0,
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.power_off_delay = 0,
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.name = "seiko_70wvw1tz3",
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@ -199,11 +202,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 10,
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.vfp = 2,
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.vbp = 2,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_LOW,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
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.power_on_delay = 0,
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.power_off_delay = 0,
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.name = "powertip_ph480272t",
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@ -224,11 +229,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 3,
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.vfp = 12,
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.vbp = 25,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.acbi = 0x0,
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.acb = 0x28,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.power_on_delay = 0,
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.power_off_delay = 0,
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.name = "innolux_at070tn83",
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@ -249,9 +256,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 1,
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.vfp = 2,
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.vbp = 7,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.name = "nec_nl2432dr22-11b",
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},
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@ -270,9 +281,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 1,
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.vfp = 1,
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.vbp = 1,
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},
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.config = OMAP_DSS_LCD_TFT,
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.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.name = "h4",
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},
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@ -291,10 +306,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 10,
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.vfp = 2,
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.vbp = 2,
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},
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.name = "apollon",
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},
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/* FocalTech ETM070003DH6 */
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@ -312,9 +330,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 3,
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.vfp = 13,
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.vbp = 29,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
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},
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
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OMAP_DSS_LCD_IHS,
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.name = "focaltech_etm070003dh6",
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},
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@ -333,11 +355,13 @@ static struct panel_config generic_dpi_panels[] = {
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.vsw = 23,
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.vfp = 1,
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.vbp = 1,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
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},
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.acbi = 0x0,
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.acb = 0x0,
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
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OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
|
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.power_on_delay = 0,
|
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.power_off_delay = 0,
|
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.name = "microtips_umsh_8173md",
|
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@ -358,9 +382,13 @@ static struct panel_config generic_dpi_panels[] = {
|
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.vsw = 10,
|
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.vfp = 4,
|
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.vbp = 2,
|
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},
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.config = OMAP_DSS_LCD_TFT,
|
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.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
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},
|
||||
.name = "ortustech_com43h4m10xtc",
|
||||
},
|
||||
|
||||
@ -379,11 +407,13 @@ static struct panel_config generic_dpi_panels[] = {
|
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.vsw = 10,
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.vfp = 12,
|
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.vbp = 23,
|
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},
|
||||
.acb = 0x0,
|
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.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
|
||||
|
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
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.de_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
},
|
||||
.name = "innolux_at080tn52",
|
||||
},
|
||||
|
||||
@ -401,8 +431,13 @@ static struct panel_config generic_dpi_panels[] = {
|
||||
.vsw = 1,
|
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.vfp = 26,
|
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.vbp = 1,
|
||||
|
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.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
},
|
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.config = OMAP_DSS_LCD_TFT,
|
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.name = "mitsubishi_aa084sb01",
|
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},
|
||||
/* EDT ET0500G0DH6 */
|
||||
@ -419,8 +454,13 @@ static struct panel_config generic_dpi_panels[] = {
|
||||
.vsw = 2,
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.vfp = 35,
|
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.vbp = 10,
|
||||
|
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.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
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},
|
||||
.config = OMAP_DSS_LCD_TFT,
|
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.name = "edt_et0500g0dh6",
|
||||
},
|
||||
|
||||
@ -439,9 +479,13 @@ static struct panel_config generic_dpi_panels[] = {
|
||||
.vsw = 2,
|
||||
.vfp = 10,
|
||||
.vbp = 33,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
},
|
||||
.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
|
||||
.name = "primeview_pd050vl1",
|
||||
},
|
||||
|
||||
@ -460,9 +504,13 @@ static struct panel_config generic_dpi_panels[] = {
|
||||
.vsw = 2,
|
||||
.vfp = 10,
|
||||
.vbp = 33,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
},
|
||||
.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
|
||||
.name = "primeview_pm070wl4",
|
||||
},
|
||||
|
||||
@ -481,9 +529,13 @@ static struct panel_config generic_dpi_panels[] = {
|
||||
.vsw = 4,
|
||||
.vfp = 1,
|
||||
.vbp = 23,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
},
|
||||
.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
|
||||
.name = "primeview_pd104slf",
|
||||
},
|
||||
};
|
||||
@ -573,10 +625,7 @@ static int generic_dpi_panel_probe(struct omap_dss_device *dssdev)
|
||||
if (!panel_config)
|
||||
return -EINVAL;
|
||||
|
||||
dssdev->panel.config = panel_config->config;
|
||||
dssdev->panel.timings = panel_config->timings;
|
||||
dssdev->panel.acb = panel_config->acb;
|
||||
dssdev->panel.acbi = panel_config->acbi;
|
||||
|
||||
drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);
|
||||
if (!drv_data)
|
||||
|
||||
@ -40,6 +40,12 @@ static struct omap_video_timings lb035q02_timings = {
|
||||
.vsw = 2,
|
||||
.vfp = 4,
|
||||
.vbp = 18,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
};
|
||||
|
||||
static int lb035q02_panel_power_on(struct omap_dss_device *dssdev)
|
||||
@ -82,8 +88,6 @@ static int lb035q02_panel_probe(struct omap_dss_device *dssdev)
|
||||
struct lb035q02_data *ld;
|
||||
int r;
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS;
|
||||
dssdev->panel.timings = lb035q02_timings;
|
||||
|
||||
ld = kzalloc(sizeof(*ld), GFP_KERNEL);
|
||||
|
||||
@ -473,7 +473,6 @@ static int n8x0_panel_probe(struct omap_dss_device *dssdev)
|
||||
|
||||
mutex_init(&ddata->lock);
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT;
|
||||
dssdev->panel.timings.x_res = 800;
|
||||
dssdev->panel.timings.y_res = 480;
|
||||
dssdev->ctrl.pixel_size = 16;
|
||||
|
||||
@ -76,6 +76,12 @@ static struct omap_video_timings nec_8048_panel_timings = {
|
||||
.vfp = 3,
|
||||
.vsw = 1,
|
||||
.vbp = 4,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
};
|
||||
|
||||
static int nec_8048_bl_update_status(struct backlight_device *bl)
|
||||
@ -116,9 +122,6 @@ static int nec_8048_panel_probe(struct omap_dss_device *dssdev)
|
||||
struct backlight_properties props;
|
||||
int r;
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_RF |
|
||||
OMAP_DSS_LCD_ONOFF;
|
||||
dssdev->panel.timings = nec_8048_panel_timings;
|
||||
|
||||
necd = kzalloc(sizeof(*necd), GFP_KERNEL);
|
||||
|
||||
@ -69,6 +69,12 @@ static struct omap_video_timings pico_ls_timings = {
|
||||
.vsw = 2,
|
||||
.vfp = 3,
|
||||
.vbp = 14,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
};
|
||||
|
||||
static inline struct picodlp_panel_data
|
||||
@ -414,9 +420,6 @@ static int picodlp_panel_probe(struct omap_dss_device *dssdev)
|
||||
struct i2c_client *picodlp_i2c_client;
|
||||
int r = 0, picodlp_adapter_id;
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_ONOFF |
|
||||
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS;
|
||||
dssdev->panel.acb = 0x0;
|
||||
dssdev->panel.timings = pico_ls_timings;
|
||||
|
||||
picod = kzalloc(sizeof(struct picodlp_data), GFP_KERNEL);
|
||||
|
||||
@ -44,6 +44,12 @@ static struct omap_video_timings sharp_ls_timings = {
|
||||
.vsw = 1,
|
||||
.vfp = 1,
|
||||
.vbp = 1,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
};
|
||||
|
||||
static int sharp_ls_bl_update_status(struct backlight_device *bl)
|
||||
@ -86,9 +92,6 @@ static int sharp_ls_panel_probe(struct omap_dss_device *dssdev)
|
||||
struct sharp_data *sd;
|
||||
int r;
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
|
||||
OMAP_DSS_LCD_IHS;
|
||||
dssdev->panel.acb = 0x28;
|
||||
dssdev->panel.timings = sharp_ls_timings;
|
||||
|
||||
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
|
||||
|
||||
@ -882,7 +882,6 @@ static int taal_probe(struct omap_dss_device *dssdev)
|
||||
goto err;
|
||||
}
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT;
|
||||
dssdev->panel.timings = panel_config->timings;
|
||||
dssdev->panel.dsi_pix_fmt = OMAP_DSS_DSI_FMT_RGB888;
|
||||
|
||||
|
||||
@ -39,6 +39,12 @@ static const struct omap_video_timings tfp410_default_timings = {
|
||||
.vfp = 3,
|
||||
.vsw = 4,
|
||||
.vbp = 7,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
};
|
||||
|
||||
struct panel_drv_data {
|
||||
@ -95,7 +101,6 @@ static int tfp410_probe(struct omap_dss_device *dssdev)
|
||||
return -ENOMEM;
|
||||
|
||||
dssdev->panel.timings = tfp410_default_timings;
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT;
|
||||
|
||||
ddata->dssdev = dssdev;
|
||||
mutex_init(&ddata->lock);
|
||||
|
||||
@ -267,6 +267,12 @@ static const struct omap_video_timings tpo_td043_timings = {
|
||||
.vsw = 1,
|
||||
.vfp = 39,
|
||||
.vbp = 34,
|
||||
|
||||
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
|
||||
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
};
|
||||
|
||||
static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043)
|
||||
@ -423,8 +429,6 @@ static int tpo_td043_probe(struct omap_dss_device *dssdev)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS |
|
||||
OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IPC;
|
||||
dssdev->panel.timings = tpo_td043_timings;
|
||||
dssdev->ctrl.pixel_size = 24;
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@ config OMAP2_DSS_RFBI
|
||||
DBI is a bus between the host processor and a peripheral,
|
||||
such as a display or a framebuffer chip.
|
||||
|
||||
See http://www.mipi.org/ for DBI spesifications.
|
||||
See http://www.mipi.org/ for DBI specifications.
|
||||
|
||||
config OMAP2_DSS_VENC
|
||||
bool "VENC support"
|
||||
@ -92,7 +92,7 @@ config OMAP2_DSS_DSI
|
||||
DSI is a high speed half-duplex serial interface between the host
|
||||
processor and a peripheral, such as a display or a framebuffer chip.
|
||||
|
||||
See http://www.mipi.org/ for DSI spesifications.
|
||||
See http://www.mipi.org/ for DSI specifications.
|
||||
|
||||
config OMAP2_DSS_MIN_FCK_PER_PCK
|
||||
int "Minimum FCK/PCK ratio (for scaling)"
|
||||
|
||||
@ -104,6 +104,7 @@ struct mgr_priv_data {
|
||||
bool shadow_extra_info_dirty;
|
||||
|
||||
struct omap_video_timings timings;
|
||||
struct dss_lcd_mgr_config lcd_config;
|
||||
};
|
||||
|
||||
static struct {
|
||||
@ -137,6 +138,7 @@ static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr)
|
||||
void dss_apply_init(void)
|
||||
{
|
||||
const int num_ovls = dss_feat_get_num_ovls();
|
||||
struct mgr_priv_data *mp;
|
||||
int i;
|
||||
|
||||
spin_lock_init(&data_lock);
|
||||
@ -168,16 +170,35 @@ void dss_apply_init(void)
|
||||
|
||||
op->user_info = op->info;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize some of the lcd_config fields for TV manager, this lets
|
||||
* us prevent checking if the manager is LCD or TV at some places
|
||||
*/
|
||||
mp = &dss_data.mgr_priv_data_array[OMAP_DSS_CHANNEL_DIGIT];
|
||||
|
||||
mp->lcd_config.video_port_width = 24;
|
||||
mp->lcd_config.clock_info.lck_div = 1;
|
||||
mp->lcd_config.clock_info.pck_div = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* A LCD manager's stallmode decides whether it is in manual or auto update. TV
|
||||
* manager is always auto update, stallmode field for TV manager is false by
|
||||
* default
|
||||
*/
|
||||
static bool ovl_manual_update(struct omap_overlay *ovl)
|
||||
{
|
||||
return ovl->manager->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
|
||||
struct mgr_priv_data *mp = get_mgr_priv(ovl->manager);
|
||||
|
||||
return mp->lcd_config.stallmode;
|
||||
}
|
||||
|
||||
static bool mgr_manual_update(struct omap_overlay_manager *mgr)
|
||||
{
|
||||
return mgr->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
|
||||
struct mgr_priv_data *mp = get_mgr_priv(mgr);
|
||||
|
||||
return mp->lcd_config.stallmode;
|
||||
}
|
||||
|
||||
static int dss_check_settings_low(struct omap_overlay_manager *mgr,
|
||||
@ -214,7 +235,7 @@ static int dss_check_settings_low(struct omap_overlay_manager *mgr,
|
||||
ois[ovl->id] = oi;
|
||||
}
|
||||
|
||||
return dss_mgr_check(mgr, mi, &mp->timings, ois);
|
||||
return dss_mgr_check(mgr, mi, &mp->timings, &mp->lcd_config, ois);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -537,7 +558,7 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl)
|
||||
{
|
||||
struct ovl_priv_data *op = get_ovl_priv(ovl);
|
||||
struct omap_overlay_info *oi;
|
||||
bool ilace, replication;
|
||||
bool replication;
|
||||
struct mgr_priv_data *mp;
|
||||
int r;
|
||||
|
||||
@ -550,11 +571,9 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl)
|
||||
|
||||
mp = get_mgr_priv(ovl->manager);
|
||||
|
||||
replication = dss_use_replication(ovl->manager->device, oi->color_mode);
|
||||
replication = dss_ovl_use_replication(mp->lcd_config, oi->color_mode);
|
||||
|
||||
ilace = ovl->manager->device->type == OMAP_DISPLAY_TYPE_VENC;
|
||||
|
||||
r = dispc_ovl_setup(ovl->id, oi, ilace, replication, &mp->timings);
|
||||
r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings);
|
||||
if (r) {
|
||||
/*
|
||||
* We can't do much here, as this function can be called from
|
||||
@ -635,6 +654,24 @@ static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
|
||||
|
||||
dispc_mgr_set_timings(mgr->id, &mp->timings);
|
||||
|
||||
/* lcd_config parameters */
|
||||
if (dss_mgr_is_lcd(mgr->id)) {
|
||||
dispc_mgr_set_io_pad_mode(mp->lcd_config.io_pad_mode);
|
||||
|
||||
dispc_mgr_enable_stallmode(mgr->id, mp->lcd_config.stallmode);
|
||||
dispc_mgr_enable_fifohandcheck(mgr->id,
|
||||
mp->lcd_config.fifohandcheck);
|
||||
|
||||
dispc_mgr_set_clock_div(mgr->id, &mp->lcd_config.clock_info);
|
||||
|
||||
dispc_mgr_set_tft_data_lines(mgr->id,
|
||||
mp->lcd_config.video_port_width);
|
||||
|
||||
dispc_lcd_enable_signal_polarity(mp->lcd_config.lcden_sig_polarity);
|
||||
|
||||
dispc_mgr_set_lcd_type_tft(mgr->id);
|
||||
}
|
||||
|
||||
mp->extra_info_dirty = false;
|
||||
if (mp->updating)
|
||||
mp->shadow_extra_info_dirty = true;
|
||||
@ -1294,6 +1331,44 @@ void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
|
||||
mutex_unlock(&apply_lock);
|
||||
}
|
||||
|
||||
static void dss_apply_mgr_lcd_config(struct omap_overlay_manager *mgr,
|
||||
const struct dss_lcd_mgr_config *config)
|
||||
{
|
||||
struct mgr_priv_data *mp = get_mgr_priv(mgr);
|
||||
|
||||
mp->lcd_config = *config;
|
||||
mp->extra_info_dirty = true;
|
||||
}
|
||||
|
||||
void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
|
||||
const struct dss_lcd_mgr_config *config)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct mgr_priv_data *mp = get_mgr_priv(mgr);
|
||||
|
||||
mutex_lock(&apply_lock);
|
||||
|
||||
if (mp->enabled) {
|
||||
DSSERR("cannot apply lcd config for %s: manager needs to be disabled\n",
|
||||
mgr->name);
|
||||
goto out;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&data_lock, flags);
|
||||
|
||||
dss_apply_mgr_lcd_config(mgr, config);
|
||||
|
||||
dss_write_regs();
|
||||
dss_set_go_bits();
|
||||
|
||||
spin_unlock_irqrestore(&data_lock, flags);
|
||||
|
||||
wait_pending_extra_info_updates();
|
||||
|
||||
out:
|
||||
mutex_unlock(&apply_lock);
|
||||
}
|
||||
|
||||
int dss_ovl_set_info(struct omap_overlay *ovl,
|
||||
struct omap_overlay_info *info)
|
||||
{
|
||||
|
||||
@ -119,6 +119,97 @@ enum omap_color_component {
|
||||
DISPC_COLOR_COMPONENT_UV = 1 << 1,
|
||||
};
|
||||
|
||||
enum mgr_reg_fields {
|
||||
DISPC_MGR_FLD_ENABLE,
|
||||
DISPC_MGR_FLD_STNTFT,
|
||||
DISPC_MGR_FLD_GO,
|
||||
DISPC_MGR_FLD_TFTDATALINES,
|
||||
DISPC_MGR_FLD_STALLMODE,
|
||||
DISPC_MGR_FLD_TCKENABLE,
|
||||
DISPC_MGR_FLD_TCKSELECTION,
|
||||
DISPC_MGR_FLD_CPR,
|
||||
DISPC_MGR_FLD_FIFOHANDCHECK,
|
||||
/* used to maintain a count of the above fields */
|
||||
DISPC_MGR_FLD_NUM,
|
||||
};
|
||||
|
||||
static const struct {
|
||||
const char *name;
|
||||
u32 vsync_irq;
|
||||
u32 framedone_irq;
|
||||
u32 sync_lost_irq;
|
||||
struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
|
||||
} mgr_desc[] = {
|
||||
[OMAP_DSS_CHANNEL_LCD] = {
|
||||
.name = "LCD",
|
||||
.vsync_irq = DISPC_IRQ_VSYNC,
|
||||
.framedone_irq = DISPC_IRQ_FRAMEDONE,
|
||||
.sync_lost_irq = DISPC_IRQ_SYNC_LOST,
|
||||
.reg_desc = {
|
||||
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
|
||||
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
|
||||
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
|
||||
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
|
||||
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
|
||||
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
|
||||
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
|
||||
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
|
||||
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
|
||||
},
|
||||
},
|
||||
[OMAP_DSS_CHANNEL_DIGIT] = {
|
||||
.name = "DIGIT",
|
||||
.vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
|
||||
.framedone_irq = 0,
|
||||
.sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
|
||||
.reg_desc = {
|
||||
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
|
||||
[DISPC_MGR_FLD_STNTFT] = { },
|
||||
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
|
||||
[DISPC_MGR_FLD_TFTDATALINES] = { },
|
||||
[DISPC_MGR_FLD_STALLMODE] = { },
|
||||
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
|
||||
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
|
||||
[DISPC_MGR_FLD_CPR] = { },
|
||||
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
|
||||
},
|
||||
},
|
||||
[OMAP_DSS_CHANNEL_LCD2] = {
|
||||
.name = "LCD2",
|
||||
.vsync_irq = DISPC_IRQ_VSYNC2,
|
||||
.framedone_irq = DISPC_IRQ_FRAMEDONE2,
|
||||
.sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
|
||||
.reg_desc = {
|
||||
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
|
||||
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
|
||||
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
|
||||
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
|
||||
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
|
||||
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
|
||||
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
|
||||
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
|
||||
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
|
||||
},
|
||||
},
|
||||
[OMAP_DSS_CHANNEL_LCD3] = {
|
||||
.name = "LCD3",
|
||||
.vsync_irq = DISPC_IRQ_VSYNC3,
|
||||
.framedone_irq = DISPC_IRQ_FRAMEDONE3,
|
||||
.sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
|
||||
.reg_desc = {
|
||||
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
|
||||
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
|
||||
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
|
||||
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
|
||||
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
|
||||
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
|
||||
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
|
||||
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
|
||||
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static void _omap_dispc_set_irqs(void);
|
||||
|
||||
static inline void dispc_write_reg(const u16 idx, u32 val)
|
||||
@ -131,6 +222,18 @@ static inline u32 dispc_read_reg(const u16 idx)
|
||||
return __raw_readl(dispc.base + idx);
|
||||
}
|
||||
|
||||
static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
|
||||
{
|
||||
const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
|
||||
return REG_GET(rfld.reg, rfld.high, rfld.low);
|
||||
}
|
||||
|
||||
static void mgr_fld_write(enum omap_channel channel,
|
||||
enum mgr_reg_fields regfld, int val) {
|
||||
const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
|
||||
REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
|
||||
}
|
||||
|
||||
#define SR(reg) \
|
||||
dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
|
||||
#define RR(reg) \
|
||||
@ -153,6 +256,10 @@ static void dispc_save_context(void)
|
||||
SR(CONTROL2);
|
||||
SR(CONFIG2);
|
||||
}
|
||||
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
||||
SR(CONTROL3);
|
||||
SR(CONFIG3);
|
||||
}
|
||||
|
||||
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
|
||||
SR(DEFAULT_COLOR(i));
|
||||
@ -266,6 +373,8 @@ static void dispc_restore_context(void)
|
||||
RR(GLOBAL_ALPHA);
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
RR(CONFIG2);
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
RR(CONFIG3);
|
||||
|
||||
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
|
||||
RR(DEFAULT_COLOR(i));
|
||||
@ -351,6 +460,8 @@ static void dispc_restore_context(void)
|
||||
RR(CONTROL);
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
RR(CONTROL2);
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
RR(CONTROL3);
|
||||
/* clear spurious SYNC_LOST_DIGIT interrupts */
|
||||
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
|
||||
|
||||
@ -387,101 +498,41 @@ void dispc_runtime_put(void)
|
||||
WARN_ON(r < 0 && r != -ENOSYS);
|
||||
}
|
||||
|
||||
static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
|
||||
{
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD ||
|
||||
channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case OMAP_DSS_CHANNEL_LCD:
|
||||
return DISPC_IRQ_VSYNC;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return DISPC_IRQ_VSYNC2;
|
||||
case OMAP_DSS_CHANNEL_DIGIT:
|
||||
return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
}
|
||||
return mgr_desc[channel].vsync_irq;
|
||||
}
|
||||
|
||||
u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case OMAP_DSS_CHANNEL_LCD:
|
||||
return DISPC_IRQ_FRAMEDONE;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return DISPC_IRQ_FRAMEDONE2;
|
||||
case OMAP_DSS_CHANNEL_DIGIT:
|
||||
return 0;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
}
|
||||
return mgr_desc[channel].framedone_irq;
|
||||
}
|
||||
|
||||
bool dispc_mgr_go_busy(enum omap_channel channel)
|
||||
{
|
||||
int bit;
|
||||
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
bit = 5; /* GOLCD */
|
||||
else
|
||||
bit = 6; /* GODIGIT */
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
|
||||
else
|
||||
return REG_GET(DISPC_CONTROL, bit, bit) == 1;
|
||||
return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
|
||||
}
|
||||
|
||||
void dispc_mgr_go(enum omap_channel channel)
|
||||
{
|
||||
int bit;
|
||||
bool enable_bit, go_bit;
|
||||
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
bit = 0; /* LCDENABLE */
|
||||
else
|
||||
bit = 1; /* DIGITALENABLE */
|
||||
|
||||
/* if the channel is not enabled, we don't need GO */
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
|
||||
else
|
||||
enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
|
||||
enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
|
||||
|
||||
if (!enable_bit)
|
||||
return;
|
||||
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
bit = 5; /* GOLCD */
|
||||
else
|
||||
bit = 6; /* GODIGIT */
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
|
||||
else
|
||||
go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
|
||||
go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
|
||||
|
||||
if (go_bit) {
|
||||
DSSERR("GO bit not down for channel %d\n", channel);
|
||||
return;
|
||||
}
|
||||
|
||||
DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
|
||||
(channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
|
||||
DSSDBG("GO %s\n", mgr_desc[channel].name);
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
|
||||
else
|
||||
REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
|
||||
}
|
||||
|
||||
static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
|
||||
@ -832,6 +883,15 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
|
||||
chan = 0;
|
||||
chan2 = 1;
|
||||
break;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
||||
chan = 0;
|
||||
chan2 = 2;
|
||||
} else {
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
@ -867,7 +927,14 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
|
||||
|
||||
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
|
||||
|
||||
if (dss_has_feature(FEAT_MGR_LCD2)) {
|
||||
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
||||
if (FLD_GET(val, 31, 30) == 0)
|
||||
channel = FLD_GET(val, shift, shift);
|
||||
else if (FLD_GET(val, 31, 30) == 1)
|
||||
channel = OMAP_DSS_CHANNEL_LCD2;
|
||||
else
|
||||
channel = OMAP_DSS_CHANNEL_LCD3;
|
||||
} else if (dss_has_feature(FEAT_MGR_LCD2)) {
|
||||
if (FLD_GET(val, 31, 30) == 0)
|
||||
channel = FLD_GET(val, shift, shift);
|
||||
else
|
||||
@ -922,16 +989,10 @@ void dispc_enable_gamma_table(bool enable)
|
||||
|
||||
static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
|
||||
{
|
||||
u16 reg;
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD)
|
||||
reg = DISPC_CONFIG;
|
||||
else if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
reg = DISPC_CONFIG2;
|
||||
else
|
||||
if (channel == OMAP_DSS_CHANNEL_DIGIT)
|
||||
return;
|
||||
|
||||
REG_FLD_MOD(reg, enable, 15, 15);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
|
||||
}
|
||||
|
||||
static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
|
||||
@ -939,7 +1000,7 @@ static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
|
||||
{
|
||||
u32 coef_r, coef_g, coef_b;
|
||||
|
||||
if (!dispc_mgr_is_lcd(channel))
|
||||
if (!dss_mgr_is_lcd(channel))
|
||||
return;
|
||||
|
||||
coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
|
||||
@ -1798,7 +1859,7 @@ static int check_horiz_timing_omap3(enum omap_channel channel,
|
||||
|
||||
nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
|
||||
pclk = dispc_mgr_pclk_rate(channel);
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
if (dss_mgr_is_lcd(channel))
|
||||
lclk = dispc_mgr_lclk_rate(channel);
|
||||
else
|
||||
lclk = dispc_fclk_rate();
|
||||
@ -2086,8 +2147,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
|
||||
}
|
||||
|
||||
int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
|
||||
bool ilace, bool replication,
|
||||
const struct omap_video_timings *mgr_timings)
|
||||
bool replication, const struct omap_video_timings *mgr_timings)
|
||||
{
|
||||
struct omap_overlay *ovl = omap_dss_get_overlay(plane);
|
||||
bool five_taps = true;
|
||||
@ -2103,6 +2163,7 @@ int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
|
||||
u16 out_width, out_height;
|
||||
enum omap_channel channel;
|
||||
int x_predecim = 1, y_predecim = 1;
|
||||
bool ilace = mgr_timings->interlace;
|
||||
|
||||
channel = dispc_ovl_get_channel_out(plane);
|
||||
|
||||
@ -2254,14 +2315,9 @@ static void dispc_disable_isr(void *data, u32 mask)
|
||||
|
||||
static void _enable_lcd_out(enum omap_channel channel, bool enable)
|
||||
{
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2) {
|
||||
REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
|
||||
/* flush posted write */
|
||||
dispc_read_reg(DISPC_CONTROL2);
|
||||
} else {
|
||||
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
|
||||
dispc_read_reg(DISPC_CONTROL);
|
||||
}
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
|
||||
/* flush posted write */
|
||||
mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
|
||||
}
|
||||
|
||||
static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
|
||||
@ -2274,12 +2330,9 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
|
||||
/* When we disable LCD output, we need to wait until frame is done.
|
||||
* Otherwise the DSS is still working, and turning off the clocks
|
||||
* prevents DSS from going to OFF mode */
|
||||
is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
|
||||
REG_GET(DISPC_CONTROL2, 0, 0) :
|
||||
REG_GET(DISPC_CONTROL, 0, 0);
|
||||
is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
|
||||
|
||||
irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
|
||||
DISPC_IRQ_FRAMEDONE;
|
||||
irq = mgr_desc[channel].framedone_irq;
|
||||
|
||||
if (!enable && is_on) {
|
||||
init_completion(&frame_done_completion);
|
||||
@ -2384,21 +2437,12 @@ static void dispc_mgr_enable_digit_out(bool enable)
|
||||
|
||||
bool dispc_mgr_is_enabled(enum omap_channel channel)
|
||||
{
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD)
|
||||
return !!REG_GET(DISPC_CONTROL, 0, 0);
|
||||
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
|
||||
return !!REG_GET(DISPC_CONTROL, 1, 1);
|
||||
else if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
return !!REG_GET(DISPC_CONTROL2, 0, 0);
|
||||
else {
|
||||
BUG();
|
||||
return false;
|
||||
}
|
||||
return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
|
||||
}
|
||||
|
||||
void dispc_mgr_enable(enum omap_channel channel, bool enable)
|
||||
{
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
if (dss_mgr_is_lcd(channel))
|
||||
dispc_mgr_enable_lcd_out(channel, enable);
|
||||
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
|
||||
dispc_mgr_enable_digit_out(enable);
|
||||
@ -2432,36 +2476,13 @@ void dispc_pck_free_enable(bool enable)
|
||||
|
||||
void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
|
||||
{
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
|
||||
else
|
||||
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
|
||||
}
|
||||
|
||||
|
||||
void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
|
||||
enum omap_lcd_display_type type)
|
||||
void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
|
||||
{
|
||||
int mode;
|
||||
|
||||
switch (type) {
|
||||
case OMAP_DSS_LCD_DISPLAY_STN:
|
||||
mode = 0;
|
||||
break;
|
||||
|
||||
case OMAP_DSS_LCD_DISPLAY_TFT:
|
||||
mode = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
|
||||
else
|
||||
REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
|
||||
}
|
||||
|
||||
void dispc_set_loadmode(enum omap_dss_load_mode mode)
|
||||
@ -2479,24 +2500,14 @@ static void dispc_mgr_set_trans_key(enum omap_channel ch,
|
||||
enum omap_dss_trans_key_type type,
|
||||
u32 trans_key)
|
||||
{
|
||||
if (ch == OMAP_DSS_CHANNEL_LCD)
|
||||
REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
|
||||
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
|
||||
REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
|
||||
else /* OMAP_DSS_CHANNEL_LCD2 */
|
||||
REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
|
||||
mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
|
||||
|
||||
dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
|
||||
}
|
||||
|
||||
static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
|
||||
{
|
||||
if (ch == OMAP_DSS_CHANNEL_LCD)
|
||||
REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
|
||||
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
|
||||
REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
|
||||
else /* OMAP_DSS_CHANNEL_LCD2 */
|
||||
REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
|
||||
mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
|
||||
}
|
||||
|
||||
static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
|
||||
@ -2547,10 +2558,7 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
|
||||
return;
|
||||
}
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
|
||||
else
|
||||
REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
|
||||
}
|
||||
|
||||
void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
|
||||
@ -2584,10 +2592,7 @@ void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
|
||||
|
||||
void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
|
||||
{
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2)
|
||||
REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
|
||||
else
|
||||
REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
|
||||
mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
|
||||
}
|
||||
|
||||
static bool _dispc_mgr_size_ok(u16 width, u16 height)
|
||||
@ -2627,7 +2632,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
|
||||
|
||||
timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
|
||||
|
||||
if (dispc_mgr_is_lcd(channel))
|
||||
if (dss_mgr_is_lcd(channel))
|
||||
timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
|
||||
timings->hfp, timings->hbp,
|
||||
timings->vsw, timings->vfp,
|
||||
@ -2637,9 +2642,16 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
|
||||
}
|
||||
|
||||
static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
|
||||
int hfp, int hbp, int vsw, int vfp, int vbp)
|
||||
int hfp, int hbp, int vsw, int vfp, int vbp,
|
||||
enum omap_dss_signal_level vsync_level,
|
||||
enum omap_dss_signal_level hsync_level,
|
||||
enum omap_dss_signal_edge data_pclk_edge,
|
||||
enum omap_dss_signal_level de_level,
|
||||
enum omap_dss_signal_edge sync_pclk_edge)
|
||||
|
||||
{
|
||||
u32 timing_h, timing_v;
|
||||
u32 timing_h, timing_v, l;
|
||||
bool onoff, rf, ipc;
|
||||
|
||||
if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
|
||||
timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
|
||||
@ -2657,6 +2669,44 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
|
||||
|
||||
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
|
||||
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
|
||||
|
||||
switch (data_pclk_edge) {
|
||||
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
|
||||
ipc = false;
|
||||
break;
|
||||
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
|
||||
ipc = true;
|
||||
break;
|
||||
case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
switch (sync_pclk_edge) {
|
||||
case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
|
||||
onoff = false;
|
||||
rf = false;
|
||||
break;
|
||||
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
|
||||
onoff = true;
|
||||
rf = false;
|
||||
break;
|
||||
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
|
||||
onoff = true;
|
||||
rf = true;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
};
|
||||
|
||||
l = dispc_read_reg(DISPC_POL_FREQ(channel));
|
||||
l |= FLD_VAL(onoff, 17, 17);
|
||||
l |= FLD_VAL(rf, 16, 16);
|
||||
l |= FLD_VAL(de_level, 15, 15);
|
||||
l |= FLD_VAL(ipc, 14, 14);
|
||||
l |= FLD_VAL(hsync_level, 13, 13);
|
||||
l |= FLD_VAL(vsync_level, 12, 12);
|
||||
dispc_write_reg(DISPC_POL_FREQ(channel), l);
|
||||
}
|
||||
|
||||
/* change name to mode? */
|
||||
@ -2674,9 +2724,10 @@ void dispc_mgr_set_timings(enum omap_channel channel,
|
||||
return;
|
||||
}
|
||||
|
||||
if (dispc_mgr_is_lcd(channel)) {
|
||||
if (dss_mgr_is_lcd(channel)) {
|
||||
_dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
|
||||
t.vfp, t.vbp);
|
||||
t.vfp, t.vbp, t.vsync_level, t.hsync_level,
|
||||
t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
|
||||
|
||||
xtot = t.x_res + t.hfp + t.hsw + t.hbp;
|
||||
ytot = t.y_res + t.vfp + t.vsw + t.vbp;
|
||||
@ -2687,14 +2738,13 @@ void dispc_mgr_set_timings(enum omap_channel channel,
|
||||
DSSDBG("pck %u\n", timings->pixel_clock);
|
||||
DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
|
||||
t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
|
||||
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
|
||||
t.vsync_level, t.hsync_level, t.data_pclk_edge,
|
||||
t.de_level, t.sync_pclk_edge);
|
||||
|
||||
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
|
||||
} else {
|
||||
enum dss_hdmi_venc_clk_source_select source;
|
||||
|
||||
source = dss_get_hdmi_venc_clk_source();
|
||||
|
||||
if (source == DSS_VENC_TV_CLK)
|
||||
if (t.interlace == true)
|
||||
t.y_res /= 2;
|
||||
}
|
||||
|
||||
@ -2780,7 +2830,7 @@ unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
|
||||
{
|
||||
unsigned long r;
|
||||
|
||||
if (dispc_mgr_is_lcd(channel)) {
|
||||
if (dss_mgr_is_lcd(channel)) {
|
||||
int pcd;
|
||||
u32 l;
|
||||
|
||||
@ -2821,12 +2871,32 @@ unsigned long dispc_core_clk_rate(void)
|
||||
return fclk / lcd;
|
||||
}
|
||||
|
||||
void dispc_dump_clocks(struct seq_file *s)
|
||||
static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
|
||||
{
|
||||
int lcd, pcd;
|
||||
enum omap_dss_clk_source lcd_clk_src;
|
||||
|
||||
seq_printf(s, "- %s -\n", mgr_desc[channel].name);
|
||||
|
||||
lcd_clk_src = dss_get_lcd_clk_source(channel);
|
||||
|
||||
seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
|
||||
dss_get_generic_clk_source_name(lcd_clk_src),
|
||||
dss_feat_get_clk_source_name(lcd_clk_src));
|
||||
|
||||
dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
|
||||
|
||||
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
|
||||
dispc_mgr_lclk_rate(channel), lcd);
|
||||
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
|
||||
dispc_mgr_pclk_rate(channel), pcd);
|
||||
}
|
||||
|
||||
void dispc_dump_clocks(struct seq_file *s)
|
||||
{
|
||||
int lcd;
|
||||
u32 l;
|
||||
enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
|
||||
enum omap_dss_clk_source lcd_clk_src;
|
||||
|
||||
if (dispc_runtime_get())
|
||||
return;
|
||||
@ -2847,36 +2917,13 @@ void dispc_dump_clocks(struct seq_file *s)
|
||||
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
|
||||
(dispc_fclk_rate()/lcd), lcd);
|
||||
}
|
||||
seq_printf(s, "- LCD1 -\n");
|
||||
|
||||
lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
|
||||
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
|
||||
|
||||
seq_printf(s, "lcd1_clk source = %s (%s)\n",
|
||||
dss_get_generic_clk_source_name(lcd_clk_src),
|
||||
dss_feat_get_clk_source_name(lcd_clk_src));
|
||||
|
||||
dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
|
||||
|
||||
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
|
||||
dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
|
||||
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
|
||||
dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
|
||||
if (dss_has_feature(FEAT_MGR_LCD2)) {
|
||||
seq_printf(s, "- LCD2 -\n");
|
||||
|
||||
lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
|
||||
|
||||
seq_printf(s, "lcd2_clk source = %s (%s)\n",
|
||||
dss_get_generic_clk_source_name(lcd_clk_src),
|
||||
dss_feat_get_clk_source_name(lcd_clk_src));
|
||||
|
||||
dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
|
||||
|
||||
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
|
||||
dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
|
||||
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
|
||||
dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
|
||||
}
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
|
||||
|
||||
dispc_runtime_put();
|
||||
}
|
||||
@ -2929,6 +2976,12 @@ void dispc_dump_irqs(struct seq_file *s)
|
||||
PIS(ACBIAS_COUNT_STAT2);
|
||||
PIS(SYNC_LOST2);
|
||||
}
|
||||
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
||||
PIS(FRAMEDONE3);
|
||||
PIS(VSYNC3);
|
||||
PIS(ACBIAS_COUNT_STAT3);
|
||||
PIS(SYNC_LOST3);
|
||||
}
|
||||
#undef PIS
|
||||
}
|
||||
#endif
|
||||
@ -2940,6 +2993,7 @@ static void dispc_dump_regs(struct seq_file *s)
|
||||
[OMAP_DSS_CHANNEL_LCD] = "LCD",
|
||||
[OMAP_DSS_CHANNEL_DIGIT] = "TV",
|
||||
[OMAP_DSS_CHANNEL_LCD2] = "LCD2",
|
||||
[OMAP_DSS_CHANNEL_LCD3] = "LCD3",
|
||||
};
|
||||
const char *ovl_names[] = {
|
||||
[OMAP_DSS_GFX] = "GFX",
|
||||
@ -2972,6 +3026,10 @@ static void dispc_dump_regs(struct seq_file *s)
|
||||
DUMPREG(DISPC_CONTROL2);
|
||||
DUMPREG(DISPC_CONFIG2);
|
||||
}
|
||||
if (dss_has_feature(FEAT_MGR_LCD3)) {
|
||||
DUMPREG(DISPC_CONTROL3);
|
||||
DUMPREG(DISPC_CONFIG3);
|
||||
}
|
||||
|
||||
#undef DUMPREG
|
||||
|
||||
@ -3093,41 +3151,8 @@ static void dispc_dump_regs(struct seq_file *s)
|
||||
#undef DUMPREG
|
||||
}
|
||||
|
||||
static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
|
||||
bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
|
||||
u8 acb)
|
||||
{
|
||||
u32 l = 0;
|
||||
|
||||
DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
|
||||
onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
|
||||
|
||||
l |= FLD_VAL(onoff, 17, 17);
|
||||
l |= FLD_VAL(rf, 16, 16);
|
||||
l |= FLD_VAL(ieo, 15, 15);
|
||||
l |= FLD_VAL(ipc, 14, 14);
|
||||
l |= FLD_VAL(ihs, 13, 13);
|
||||
l |= FLD_VAL(ivs, 12, 12);
|
||||
l |= FLD_VAL(acbi, 11, 8);
|
||||
l |= FLD_VAL(acb, 7, 0);
|
||||
|
||||
dispc_write_reg(DISPC_POL_FREQ(channel), l);
|
||||
}
|
||||
|
||||
void dispc_mgr_set_pol_freq(enum omap_channel channel,
|
||||
enum omap_panel_config config, u8 acbi, u8 acb)
|
||||
{
|
||||
_dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
|
||||
(config & OMAP_DSS_LCD_RF) != 0,
|
||||
(config & OMAP_DSS_LCD_IEO) != 0,
|
||||
(config & OMAP_DSS_LCD_IPC) != 0,
|
||||
(config & OMAP_DSS_LCD_IHS) != 0,
|
||||
(config & OMAP_DSS_LCD_IVS) != 0,
|
||||
acbi, acb);
|
||||
}
|
||||
|
||||
/* with fck as input clock rate, find dispc dividers that produce req_pck */
|
||||
void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
||||
void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
|
||||
struct dispc_clock_info *cinfo)
|
||||
{
|
||||
u16 pcd_min, pcd_max;
|
||||
@ -3138,9 +3163,6 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
||||
pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
|
||||
pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
|
||||
|
||||
if (!is_tft)
|
||||
pcd_min = 3;
|
||||
|
||||
best_pck = 0;
|
||||
best_ld = 0;
|
||||
best_pd = 0;
|
||||
@ -3192,15 +3214,13 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dispc_mgr_set_clock_div(enum omap_channel channel,
|
||||
void dispc_mgr_set_clock_div(enum omap_channel channel,
|
||||
struct dispc_clock_info *cinfo)
|
||||
{
|
||||
DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
|
||||
DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
|
||||
|
||||
dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dispc_mgr_get_clock_div(enum omap_channel channel,
|
||||
@ -3354,6 +3374,8 @@ static void print_irq_status(u32 status)
|
||||
PIS(SYNC_LOST_DIGIT);
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
PIS(SYNC_LOST2);
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
PIS(SYNC_LOST3);
|
||||
#undef PIS
|
||||
|
||||
printk("\n");
|
||||
@ -3450,12 +3472,6 @@ static void dispc_error_worker(struct work_struct *work)
|
||||
DISPC_IRQ_VID3_FIFO_UNDERFLOW,
|
||||
};
|
||||
|
||||
static const unsigned sync_lost_bits[] = {
|
||||
DISPC_IRQ_SYNC_LOST,
|
||||
DISPC_IRQ_SYNC_LOST_DIGIT,
|
||||
DISPC_IRQ_SYNC_LOST2,
|
||||
};
|
||||
|
||||
spin_lock_irqsave(&dispc.irq_lock, flags);
|
||||
errors = dispc.error_irqs;
|
||||
dispc.error_irqs = 0;
|
||||
@ -3484,7 +3500,7 @@ static void dispc_error_worker(struct work_struct *work)
|
||||
unsigned bit;
|
||||
|
||||
mgr = omap_dss_get_overlay_manager(i);
|
||||
bit = sync_lost_bits[i];
|
||||
bit = mgr_desc[i].sync_lost_irq;
|
||||
|
||||
if (bit & errors) {
|
||||
struct omap_dss_device *dssdev = mgr->device;
|
||||
@ -3603,6 +3619,8 @@ static void _omap_dispc_initialize_irq(void)
|
||||
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
|
||||
if (dss_feat_get_num_ovls() > 3)
|
||||
dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
|
||||
|
||||
|
||||
@ -36,6 +36,8 @@
|
||||
#define DISPC_CONTROL2 0x0238
|
||||
#define DISPC_CONFIG2 0x0620
|
||||
#define DISPC_DIVISOR 0x0804
|
||||
#define DISPC_CONTROL3 0x0848
|
||||
#define DISPC_CONFIG3 0x084C
|
||||
|
||||
/* DISPC overlay registers */
|
||||
#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
|
||||
@ -118,6 +120,8 @@ static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
|
||||
return 0x0050;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03AC;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0814;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -133,6 +137,8 @@ static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
|
||||
return 0x0058;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03B0;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0818;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -149,6 +155,8 @@ static inline u16 DISPC_TIMING_H(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x0400;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0840;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -165,6 +173,8 @@ static inline u16 DISPC_TIMING_V(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x0404;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0844;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -181,6 +191,8 @@ static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x0408;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x083C;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -197,6 +209,8 @@ static inline u16 DISPC_DIVISORo(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x040C;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0838;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -213,6 +227,8 @@ static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
|
||||
return 0x0078;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03CC;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0834;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -229,6 +245,8 @@ static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03C0;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0828;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -245,6 +263,8 @@ static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03C4;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x082C;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -261,6 +281,8 @@ static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03C8;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0830;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -277,6 +299,8 @@ static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03BC;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0824;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -293,6 +317,8 @@ static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03B8;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x0820;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
@ -309,6 +335,8 @@ static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
|
||||
return 0;
|
||||
case OMAP_DSS_CHANNEL_LCD2:
|
||||
return 0x03B4;
|
||||
case OMAP_DSS_CHANNEL_LCD3:
|
||||
return 0x081C;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
|
||||
@ -116,7 +116,7 @@ static ssize_t display_timings_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t size)
|
||||
{
|
||||
struct omap_dss_device *dssdev = to_dss_device(dev);
|
||||
struct omap_video_timings t;
|
||||
struct omap_video_timings t = dssdev->panel.timings;
|
||||
int r, found;
|
||||
|
||||
if (!dssdev->driver->set_timings || !dssdev->driver->check_timings)
|
||||
@ -316,44 +316,6 @@ void omapdss_default_get_timings(struct omap_dss_device *dssdev,
|
||||
}
|
||||
EXPORT_SYMBOL(omapdss_default_get_timings);
|
||||
|
||||
/* Checks if replication logic should be used. Only use for active matrix,
|
||||
* when overlay is in RGB12U or RGB16 mode, and LCD interface is
|
||||
* 18bpp or 24bpp */
|
||||
bool dss_use_replication(struct omap_dss_device *dssdev,
|
||||
enum omap_color_mode mode)
|
||||
{
|
||||
int bpp;
|
||||
|
||||
if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16)
|
||||
return false;
|
||||
|
||||
if (dssdev->type == OMAP_DISPLAY_TYPE_DPI &&
|
||||
(dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0)
|
||||
return false;
|
||||
|
||||
switch (dssdev->type) {
|
||||
case OMAP_DISPLAY_TYPE_DPI:
|
||||
bpp = dssdev->phy.dpi.data_lines;
|
||||
break;
|
||||
case OMAP_DISPLAY_TYPE_HDMI:
|
||||
case OMAP_DISPLAY_TYPE_VENC:
|
||||
case OMAP_DISPLAY_TYPE_SDI:
|
||||
bpp = 24;
|
||||
break;
|
||||
case OMAP_DISPLAY_TYPE_DBI:
|
||||
bpp = dssdev->ctrl.pixel_size;
|
||||
break;
|
||||
case OMAP_DISPLAY_TYPE_DSI:
|
||||
bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return false;
|
||||
}
|
||||
|
||||
return bpp > 16;
|
||||
}
|
||||
|
||||
void dss_init_device(struct platform_device *pdev,
|
||||
struct omap_dss_device *dssdev)
|
||||
{
|
||||
|
||||
@ -38,6 +38,8 @@
|
||||
static struct {
|
||||
struct regulator *vdds_dsi_reg;
|
||||
struct platform_device *dsidev;
|
||||
|
||||
struct dss_lcd_mgr_config mgr_config;
|
||||
} dpi;
|
||||
|
||||
static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
|
||||
@ -64,7 +66,7 @@ static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
|
||||
return false;
|
||||
}
|
||||
|
||||
static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
|
||||
unsigned long pck_req, unsigned long *fck, int *lck_div,
|
||||
int *pck_div)
|
||||
{
|
||||
@ -72,8 +74,8 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
int r;
|
||||
|
||||
r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
|
||||
&dsi_cinfo, &dispc_cinfo);
|
||||
r = dsi_pll_calc_clock_div_pck(dpi.dsidev, pck_req, &dsi_cinfo,
|
||||
&dispc_cinfo);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
@ -83,11 +85,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
|
||||
dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
|
||||
|
||||
r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
|
||||
if (r) {
|
||||
dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
|
||||
return r;
|
||||
}
|
||||
dpi.mgr_config.clock_info = dispc_cinfo;
|
||||
|
||||
*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
|
||||
*lck_div = dispc_cinfo.lck_div;
|
||||
@ -96,7 +94,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
static int dpi_set_dispc_clk(struct omap_dss_device *dssdev,
|
||||
unsigned long pck_req, unsigned long *fck, int *lck_div,
|
||||
int *pck_div)
|
||||
{
|
||||
@ -104,7 +102,7 @@ static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
int r;
|
||||
|
||||
r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
|
||||
r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
@ -112,9 +110,7 @@ static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
|
||||
if (r)
|
||||
return r;
|
||||
dpi.mgr_config.clock_info = dispc_cinfo;
|
||||
|
||||
*fck = dss_cinfo.fck;
|
||||
*lck_div = dispc_cinfo.lck_div;
|
||||
@ -129,20 +125,14 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
|
||||
int lck_div = 0, pck_div = 0;
|
||||
unsigned long fck = 0;
|
||||
unsigned long pck;
|
||||
bool is_tft;
|
||||
int r = 0;
|
||||
|
||||
dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
|
||||
dssdev->panel.acbi, dssdev->panel.acb);
|
||||
|
||||
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
|
||||
|
||||
if (dpi_use_dsi_pll(dssdev))
|
||||
r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
|
||||
&fck, &lck_div, &pck_div);
|
||||
r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
|
||||
&lck_div, &pck_div);
|
||||
else
|
||||
r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
|
||||
&fck, &lck_div, &pck_div);
|
||||
r = dpi_set_dispc_clk(dssdev, t->pixel_clock * 1000, &fck,
|
||||
&lck_div, &pck_div);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
@ -161,19 +151,18 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dpi_basic_init(struct omap_dss_device *dssdev)
|
||||
static void dpi_config_lcd_manager(struct omap_dss_device *dssdev)
|
||||
{
|
||||
bool is_tft;
|
||||
dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
|
||||
|
||||
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
|
||||
dpi.mgr_config.stallmode = false;
|
||||
dpi.mgr_config.fifohandcheck = false;
|
||||
|
||||
dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
|
||||
dispc_mgr_enable_stallmode(dssdev->manager->id, false);
|
||||
dpi.mgr_config.video_port_width = dssdev->phy.dpi.data_lines;
|
||||
|
||||
dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
|
||||
OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
|
||||
dispc_mgr_set_tft_data_lines(dssdev->manager->id,
|
||||
dssdev->phy.dpi.data_lines);
|
||||
dpi.mgr_config.lcden_sig_polarity = 0;
|
||||
|
||||
dss_mgr_set_lcd_config(dssdev->manager, &dpi.mgr_config);
|
||||
}
|
||||
|
||||
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
|
||||
@ -206,8 +195,6 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
|
||||
if (r)
|
||||
goto err_get_dispc;
|
||||
|
||||
dpi_basic_init(dssdev);
|
||||
|
||||
if (dpi_use_dsi_pll(dssdev)) {
|
||||
r = dsi_runtime_get(dpi.dsidev);
|
||||
if (r)
|
||||
@ -222,6 +209,8 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
|
||||
if (r)
|
||||
goto err_set_mode;
|
||||
|
||||
dpi_config_lcd_manager(dssdev);
|
||||
|
||||
mdelay(2);
|
||||
|
||||
r = dss_mgr_enable(dssdev->manager);
|
||||
@ -292,7 +281,6 @@ EXPORT_SYMBOL(dpi_set_timings);
|
||||
int dpi_check_timings(struct omap_dss_device *dssdev,
|
||||
struct omap_video_timings *timings)
|
||||
{
|
||||
bool is_tft;
|
||||
int r;
|
||||
int lck_div, pck_div;
|
||||
unsigned long fck;
|
||||
@ -305,11 +293,9 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
|
||||
if (timings->pixel_clock == 0)
|
||||
return -EINVAL;
|
||||
|
||||
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
|
||||
|
||||
if (dpi_use_dsi_pll(dssdev)) {
|
||||
struct dsi_clock_info dsi_cinfo;
|
||||
r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
|
||||
r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
|
||||
timings->pixel_clock * 1000,
|
||||
&dsi_cinfo, &dispc_cinfo);
|
||||
|
||||
@ -319,7 +305,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
|
||||
fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
|
||||
} else {
|
||||
struct dss_clock_info dss_cinfo;
|
||||
r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
|
||||
r = dss_calc_clock_div(timings->pixel_clock * 1000,
|
||||
&dss_cinfo, &dispc_cinfo);
|
||||
|
||||
if (r)
|
||||
|
||||
@ -331,6 +331,8 @@ struct dsi_data {
|
||||
unsigned num_lanes_used;
|
||||
|
||||
unsigned scp_clk_refcount;
|
||||
|
||||
struct dss_lcd_mgr_config mgr_config;
|
||||
};
|
||||
|
||||
struct dsi_packet_sent_handler_data {
|
||||
@ -1085,9 +1087,9 @@ static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
|
||||
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
|
||||
|
||||
if (enable)
|
||||
clk_enable(dsi->sys_clk);
|
||||
clk_prepare_enable(dsi->sys_clk);
|
||||
else
|
||||
clk_disable(dsi->sys_clk);
|
||||
clk_disable_unprepare(dsi->sys_clk);
|
||||
|
||||
if (enable && dsi->pll_locked) {
|
||||
if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
|
||||
@ -1316,7 +1318,7 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
|
||||
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
|
||||
unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo)
|
||||
{
|
||||
@ -1335,8 +1337,8 @@ int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
|
||||
dsi->cache_cinfo.clkin == dss_sys_clk) {
|
||||
DSSDBG("DSI clock info found from cache\n");
|
||||
*dsi_cinfo = dsi->cache_cinfo;
|
||||
dispc_find_clk_divs(is_tft, req_pck,
|
||||
dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
|
||||
dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
|
||||
dispc_cinfo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1402,7 +1404,7 @@ retry:
|
||||
|
||||
match = 1;
|
||||
|
||||
dispc_find_clk_divs(is_tft, req_pck,
|
||||
dispc_find_clk_divs(req_pck,
|
||||
cur.dsi_pll_hsdiv_dispc_clk,
|
||||
&cur_dispc);
|
||||
|
||||
@ -3631,17 +3633,14 @@ static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
|
||||
static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
|
||||
int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
|
||||
int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
|
||||
bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
|
||||
bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
|
||||
u32 r;
|
||||
|
||||
r = dsi_read_reg(dsidev, DSI_CTRL);
|
||||
r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
|
||||
r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
|
||||
r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
|
||||
r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
|
||||
r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
|
||||
r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
|
||||
r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
|
||||
r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
|
||||
r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
|
||||
@ -4340,52 +4339,101 @@ EXPORT_SYMBOL(omap_dsi_update);
|
||||
|
||||
/* Display funcs */
|
||||
|
||||
static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
int r;
|
||||
unsigned long long fck;
|
||||
|
||||
fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
|
||||
|
||||
dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
|
||||
dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
|
||||
|
||||
r = dispc_calc_clock_rates(fck, &dispc_cinfo);
|
||||
if (r) {
|
||||
DSSERR("Failed to calc dispc clocks\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
dsi->mgr_config.clock_info = dispc_cinfo;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
|
||||
struct omap_video_timings timings;
|
||||
int r;
|
||||
u32 irq = 0;
|
||||
|
||||
if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
|
||||
u16 dw, dh;
|
||||
u32 irq;
|
||||
struct omap_video_timings timings = {
|
||||
.hsw = 1,
|
||||
.hfp = 1,
|
||||
.hbp = 1,
|
||||
.vsw = 1,
|
||||
.vfp = 0,
|
||||
.vbp = 0,
|
||||
};
|
||||
|
||||
dssdev->driver->get_resolution(dssdev, &dw, &dh);
|
||||
|
||||
timings.x_res = dw;
|
||||
timings.y_res = dh;
|
||||
timings.hsw = 1;
|
||||
timings.hfp = 1;
|
||||
timings.hbp = 1;
|
||||
timings.vsw = 1;
|
||||
timings.vfp = 0;
|
||||
timings.vbp = 0;
|
||||
|
||||
irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
|
||||
DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
|
||||
irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
|
||||
|
||||
r = omap_dispc_register_isr(dsi_framedone_irq_callback,
|
||||
(void *) dssdev, irq);
|
||||
if (r) {
|
||||
DSSERR("can't get FRAMEDONE irq\n");
|
||||
return r;
|
||||
goto err;
|
||||
}
|
||||
|
||||
dispc_mgr_enable_stallmode(dssdev->manager->id, true);
|
||||
dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
|
||||
|
||||
dss_mgr_set_timings(dssdev->manager, &timings);
|
||||
dsi->mgr_config.stallmode = true;
|
||||
dsi->mgr_config.fifohandcheck = true;
|
||||
} else {
|
||||
dispc_mgr_enable_stallmode(dssdev->manager->id, false);
|
||||
dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
|
||||
timings = dssdev->panel.timings;
|
||||
|
||||
dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
|
||||
dsi->mgr_config.stallmode = false;
|
||||
dsi->mgr_config.fifohandcheck = false;
|
||||
}
|
||||
|
||||
dispc_mgr_set_lcd_display_type(dssdev->manager->id,
|
||||
OMAP_DSS_LCD_DISPLAY_TFT);
|
||||
dispc_mgr_set_tft_data_lines(dssdev->manager->id,
|
||||
dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
|
||||
/*
|
||||
* override interlace, logic level and edge related parameters in
|
||||
* omap_video_timings with default values
|
||||
*/
|
||||
timings.interlace = false;
|
||||
timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
|
||||
timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
|
||||
|
||||
dss_mgr_set_timings(dssdev->manager, &timings);
|
||||
|
||||
r = dsi_configure_dispc_clocks(dssdev);
|
||||
if (r)
|
||||
goto err1;
|
||||
|
||||
dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
|
||||
dsi->mgr_config.video_port_width =
|
||||
dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
|
||||
dsi->mgr_config.lcden_sig_polarity = 0;
|
||||
|
||||
dss_mgr_set_lcd_config(dssdev->manager, &dsi->mgr_config);
|
||||
|
||||
return 0;
|
||||
err1:
|
||||
if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE)
|
||||
omap_dispc_unregister_isr(dsi_framedone_irq_callback,
|
||||
(void *) dssdev, irq);
|
||||
err:
|
||||
return r;
|
||||
}
|
||||
|
||||
static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
|
||||
@ -4393,8 +4441,7 @@ static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
|
||||
if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
|
||||
u32 irq;
|
||||
|
||||
irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
|
||||
DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
|
||||
irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
|
||||
|
||||
omap_dispc_unregister_isr(dsi_framedone_irq_callback,
|
||||
(void *) dssdev, irq);
|
||||
@ -4426,33 +4473,6 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
int r;
|
||||
unsigned long long fck;
|
||||
|
||||
fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
|
||||
|
||||
dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
|
||||
dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
|
||||
|
||||
r = dispc_calc_clock_rates(fck, &dispc_cinfo);
|
||||
if (r) {
|
||||
DSSERR("Failed to calc dispc clocks\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
|
||||
if (r) {
|
||||
DSSERR("Failed to set dispc clocks\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
@ -4474,10 +4494,6 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
|
||||
|
||||
DSSDBG("PLL OK\n");
|
||||
|
||||
r = dsi_configure_dispc_clocks(dssdev);
|
||||
if (r)
|
||||
goto err2;
|
||||
|
||||
r = dsi_cio_init(dssdev);
|
||||
if (r)
|
||||
goto err2;
|
||||
|
||||
@ -388,7 +388,8 @@ void dss_select_lcd_clk_source(enum omap_channel channel,
|
||||
dsi_wait_pll_hsdiv_dispc_active(dsidev);
|
||||
break;
|
||||
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
|
||||
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
|
||||
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
|
||||
channel != OMAP_DSS_CHANNEL_LCD3);
|
||||
b = 1;
|
||||
dsidev = dsi_get_dsidev_from_id(1);
|
||||
dsi_wait_pll_hsdiv_dispc_active(dsidev);
|
||||
@ -398,10 +399,12 @@ void dss_select_lcd_clk_source(enum omap_channel channel,
|
||||
return;
|
||||
}
|
||||
|
||||
pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
|
||||
pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
||||
(channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
|
||||
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
|
||||
|
||||
ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
|
||||
ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
||||
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
|
||||
dss.lcd_clk_source[ix] = clk_src;
|
||||
}
|
||||
|
||||
@ -418,7 +421,8 @@ enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
|
||||
enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
|
||||
{
|
||||
if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
|
||||
int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
|
||||
int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
||||
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
|
||||
return dss.lcd_clk_source[ix];
|
||||
} else {
|
||||
/* LCD_CLK source is the same as DISPC_FCLK source for
|
||||
@ -502,8 +506,7 @@ unsigned long dss_get_dpll4_rate(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
|
||||
struct dss_clock_info *dss_cinfo,
|
||||
int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo)
|
||||
{
|
||||
unsigned long prate;
|
||||
@ -551,7 +554,7 @@ retry:
|
||||
fck = clk_get_rate(dss.dss_clk);
|
||||
fck_div = 1;
|
||||
|
||||
dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
|
||||
dispc_find_clk_divs(req_pck, fck, &cur_dispc);
|
||||
match = 1;
|
||||
|
||||
best_dss.fck = fck;
|
||||
@ -581,7 +584,7 @@ retry:
|
||||
|
||||
match = 1;
|
||||
|
||||
dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
|
||||
dispc_find_clk_divs(req_pck, fck, &cur_dispc);
|
||||
|
||||
if (abs(cur_dispc.pck - req_pck) <
|
||||
abs(best_dispc.pck - req_pck)) {
|
||||
|
||||
@ -152,6 +152,25 @@ struct dsi_clock_info {
|
||||
u16 lp_clk_div;
|
||||
};
|
||||
|
||||
struct reg_field {
|
||||
u16 reg;
|
||||
u8 high;
|
||||
u8 low;
|
||||
};
|
||||
|
||||
struct dss_lcd_mgr_config {
|
||||
enum dss_io_pad_mode io_pad_mode;
|
||||
|
||||
bool stallmode;
|
||||
bool fifohandcheck;
|
||||
|
||||
struct dispc_clock_info clock_info;
|
||||
|
||||
int video_port_width;
|
||||
|
||||
int lcden_sig_polarity;
|
||||
};
|
||||
|
||||
struct seq_file;
|
||||
struct platform_device;
|
||||
|
||||
@ -188,6 +207,8 @@ int dss_mgr_set_device(struct omap_overlay_manager *mgr,
|
||||
int dss_mgr_unset_device(struct omap_overlay_manager *mgr);
|
||||
void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
|
||||
struct omap_video_timings *timings);
|
||||
void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
|
||||
const struct dss_lcd_mgr_config *config);
|
||||
const struct omap_video_timings *dss_mgr_get_timings(struct omap_overlay_manager *mgr);
|
||||
|
||||
bool dss_ovl_is_enabled(struct omap_overlay *ovl);
|
||||
@ -210,8 +231,6 @@ void dss_init_device(struct platform_device *pdev,
|
||||
struct omap_dss_device *dssdev);
|
||||
void dss_uninit_device(struct platform_device *pdev,
|
||||
struct omap_dss_device *dssdev);
|
||||
bool dss_use_replication(struct omap_dss_device *dssdev,
|
||||
enum omap_color_mode mode);
|
||||
|
||||
/* manager */
|
||||
int dss_init_overlay_managers(struct platform_device *pdev);
|
||||
@ -223,8 +242,18 @@ int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
|
||||
int dss_mgr_check(struct omap_overlay_manager *mgr,
|
||||
struct omap_overlay_manager_info *info,
|
||||
const struct omap_video_timings *mgr_timings,
|
||||
const struct dss_lcd_mgr_config *config,
|
||||
struct omap_overlay_info **overlay_infos);
|
||||
|
||||
static inline bool dss_mgr_is_lcd(enum omap_channel id)
|
||||
{
|
||||
if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
|
||||
id == OMAP_DSS_CHANNEL_LCD3)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
/* overlay */
|
||||
void dss_init_overlays(struct platform_device *pdev);
|
||||
void dss_uninit_overlays(struct platform_device *pdev);
|
||||
@ -234,6 +263,8 @@ int dss_ovl_simple_check(struct omap_overlay *ovl,
|
||||
const struct omap_overlay_info *info);
|
||||
int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
|
||||
const struct omap_video_timings *mgr_timings);
|
||||
bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
|
||||
enum omap_color_mode mode);
|
||||
|
||||
/* DSS */
|
||||
int dss_init_platform_driver(void) __init;
|
||||
@ -268,8 +299,7 @@ unsigned long dss_get_dpll4_rate(void);
|
||||
int dss_calc_clock_rates(struct dss_clock_info *cinfo);
|
||||
int dss_set_clock_div(struct dss_clock_info *cinfo);
|
||||
int dss_get_clock_div(struct dss_clock_info *cinfo);
|
||||
int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
|
||||
struct dss_clock_info *dss_cinfo,
|
||||
int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo);
|
||||
|
||||
/* SDI */
|
||||
@ -296,7 +326,7 @@ u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
|
||||
unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
|
||||
int dsi_pll_set_clock_div(struct platform_device *dsidev,
|
||||
struct dsi_clock_info *cinfo);
|
||||
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
|
||||
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
|
||||
unsigned long req_pck, struct dsi_clock_info *cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo);
|
||||
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
|
||||
@ -330,7 +360,7 @@ static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
|
||||
bool is_tft, unsigned long req_pck,
|
||||
unsigned long req_pck,
|
||||
struct dsi_clock_info *dsi_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo)
|
||||
{
|
||||
@ -387,7 +417,7 @@ void dispc_set_loadmode(enum omap_dss_load_mode mode);
|
||||
bool dispc_mgr_timings_ok(enum omap_channel channel,
|
||||
const struct omap_video_timings *timings);
|
||||
unsigned long dispc_fclk_rate(void);
|
||||
void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
||||
void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
|
||||
struct dispc_clock_info *cinfo);
|
||||
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
|
||||
struct dispc_clock_info *cinfo);
|
||||
@ -398,8 +428,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
|
||||
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
|
||||
bool manual_update);
|
||||
int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
|
||||
bool ilace, bool replication,
|
||||
const struct omap_video_timings *mgr_timings);
|
||||
bool replication, const struct omap_video_timings *mgr_timings);
|
||||
int dispc_ovl_enable(enum omap_plane plane, bool enable);
|
||||
void dispc_ovl_set_channel_out(enum omap_plane plane,
|
||||
enum omap_channel channel);
|
||||
@ -415,16 +444,13 @@ bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
|
||||
void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
|
||||
void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
|
||||
void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
|
||||
void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
|
||||
enum omap_lcd_display_type type);
|
||||
void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
|
||||
void dispc_mgr_set_timings(enum omap_channel channel,
|
||||
struct omap_video_timings *timings);
|
||||
void dispc_mgr_set_pol_freq(enum omap_channel channel,
|
||||
enum omap_panel_config config, u8 acbi, u8 acb);
|
||||
unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
|
||||
unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
|
||||
unsigned long dispc_core_clk_rate(void);
|
||||
int dispc_mgr_set_clock_div(enum omap_channel channel,
|
||||
void dispc_mgr_set_clock_div(enum omap_channel channel,
|
||||
struct dispc_clock_info *cinfo);
|
||||
int dispc_mgr_get_clock_div(enum omap_channel channel,
|
||||
struct dispc_clock_info *cinfo);
|
||||
|
||||
@ -24,9 +24,9 @@
|
||||
#include "ti_hdmi.h"
|
||||
#endif
|
||||
|
||||
#define MAX_DSS_MANAGERS 3
|
||||
#define MAX_DSS_MANAGERS 4
|
||||
#define MAX_DSS_OVERLAYS 4
|
||||
#define MAX_DSS_LCD_MANAGERS 2
|
||||
#define MAX_DSS_LCD_MANAGERS 3
|
||||
#define MAX_NUM_DSI 2
|
||||
|
||||
/* DSS has feature id */
|
||||
@ -36,6 +36,7 @@ enum dss_feat_id {
|
||||
FEAT_PCKFREEENABLE,
|
||||
FEAT_FUNCGATED,
|
||||
FEAT_MGR_LCD2,
|
||||
FEAT_MGR_LCD3,
|
||||
FEAT_LINEBUFFERSPLIT,
|
||||
FEAT_ROWREPEATENABLE,
|
||||
FEAT_RESIZECONF,
|
||||
|
||||
@ -78,43 +78,214 @@ static struct {
|
||||
*/
|
||||
|
||||
static const struct hdmi_config cea_timings[] = {
|
||||
{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
|
||||
{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
|
||||
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
|
||||
{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
|
||||
{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
|
||||
{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
|
||||
{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
|
||||
{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
|
||||
{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
|
||||
{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
|
||||
{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
|
||||
{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
|
||||
{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
|
||||
{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
|
||||
{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
|
||||
{
|
||||
{ 640, 480, 25200, 96, 16, 48, 2, 10, 33,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 1, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 720, 480, 27027, 62, 16, 60, 6, 9, 30,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 2, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 4, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
true, },
|
||||
{ 5, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
true, },
|
||||
{ 6, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 16, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 720, 576, 27000, 64, 12, 68, 5, 5, 39,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 17, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 19, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
true, },
|
||||
{ 20, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
true, },
|
||||
{ 21, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 29, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 31, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 32, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 35, HDMI_HDMI },
|
||||
},
|
||||
{
|
||||
{ 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 37, HDMI_HDMI },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct hdmi_config vesa_timings[] = {
|
||||
/* VESA From Here */
|
||||
{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
|
||||
{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
|
||||
{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
|
||||
{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
|
||||
{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
|
||||
{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
|
||||
{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
|
||||
{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
|
||||
{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
|
||||
{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
|
||||
{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
|
||||
{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
|
||||
{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
|
||||
{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
|
||||
{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
|
||||
{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
|
||||
{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
|
||||
{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
|
||||
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
|
||||
{
|
||||
{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 4, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 800, 600, 40000, 128, 40, 88, 4, 1, 23,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 9, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 848, 480, 33750, 112, 16, 112, 8, 6, 23,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0xE, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x17, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x1C, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x27, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x20, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x23, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x10, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x2A, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x2F, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false, },
|
||||
{ 0x3A, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x51, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x52, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x16, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x29, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x39, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x1B, HDMI_DVI },
|
||||
},
|
||||
{
|
||||
{ 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
|
||||
OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
|
||||
false, },
|
||||
{ 0x55, HDMI_DVI },
|
||||
},
|
||||
};
|
||||
|
||||
static int hdmi_runtime_get(void)
|
||||
@ -179,7 +350,7 @@ static const struct hdmi_config *hdmi_get_timings(void)
|
||||
}
|
||||
|
||||
static bool hdmi_timings_compare(struct omap_video_timings *timing1,
|
||||
const struct hdmi_video_timings *timing2)
|
||||
const struct omap_video_timings *timing2)
|
||||
{
|
||||
int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
|
||||
|
||||
@ -758,6 +929,7 @@ static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
|
||||
hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
|
||||
hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
|
||||
hdmi.ip_data.phy_offset = HDMI_PHY;
|
||||
mutex_init(&hdmi.ip_data.lock);
|
||||
|
||||
hdmi_panel_init();
|
||||
|
||||
@ -785,7 +957,7 @@ static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
|
||||
|
||||
static int hdmi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
clk_disable(hdmi.sys_clk);
|
||||
clk_disable_unprepare(hdmi.sys_clk);
|
||||
|
||||
dispc_runtime_put();
|
||||
|
||||
@ -800,7 +972,7 @@ static int hdmi_runtime_resume(struct device *dev)
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
clk_enable(hdmi.sys_clk);
|
||||
clk_prepare_enable(hdmi.sys_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -43,10 +43,11 @@ static int hdmi_panel_probe(struct omap_dss_device *dssdev)
|
||||
{
|
||||
DSSDBG("ENTER hdmi_panel_probe\n");
|
||||
|
||||
dssdev->panel.config = OMAP_DSS_LCD_TFT |
|
||||
OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS;
|
||||
|
||||
dssdev->panel.timings = (struct omap_video_timings){640, 480, 25175, 96, 16, 48, 2 , 11, 31};
|
||||
dssdev->panel.timings = (struct omap_video_timings)
|
||||
{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,
|
||||
OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
|
||||
false,
|
||||
};
|
||||
|
||||
DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
|
||||
dssdev->panel.timings.x_res,
|
||||
|
||||
@ -500,16 +500,12 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
|
||||
if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC)
|
||||
irq = DISPC_IRQ_EVSYNC_ODD;
|
||||
} else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) {
|
||||
else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI)
|
||||
irq = DISPC_IRQ_EVSYNC_EVEN;
|
||||
} else {
|
||||
if (mgr->id == OMAP_DSS_CHANNEL_LCD)
|
||||
irq = DISPC_IRQ_VSYNC;
|
||||
else
|
||||
irq = DISPC_IRQ_VSYNC2;
|
||||
}
|
||||
else
|
||||
irq = dispc_mgr_get_vsync_irq(mgr->id);
|
||||
|
||||
r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
|
||||
|
||||
@ -545,6 +541,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
|
||||
mgr->name = "lcd2";
|
||||
mgr->id = OMAP_DSS_CHANNEL_LCD2;
|
||||
break;
|
||||
case 3:
|
||||
mgr->name = "lcd3";
|
||||
mgr->id = OMAP_DSS_CHANNEL_LCD3;
|
||||
break;
|
||||
}
|
||||
|
||||
mgr->set_device = &dss_mgr_set_device;
|
||||
@ -665,9 +665,40 @@ int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dss_mgr_check_lcd_config(struct omap_overlay_manager *mgr,
|
||||
const struct dss_lcd_mgr_config *config)
|
||||
{
|
||||
struct dispc_clock_info cinfo = config->clock_info;
|
||||
int dl = config->video_port_width;
|
||||
bool stallmode = config->stallmode;
|
||||
bool fifohandcheck = config->fifohandcheck;
|
||||
|
||||
if (cinfo.lck_div < 1 || cinfo.lck_div > 255)
|
||||
return -EINVAL;
|
||||
|
||||
if (cinfo.pck_div < 1 || cinfo.pck_div > 255)
|
||||
return -EINVAL;
|
||||
|
||||
if (dl != 12 && dl != 16 && dl != 18 && dl != 24)
|
||||
return -EINVAL;
|
||||
|
||||
/* fifohandcheck should be used only with stallmode */
|
||||
if (stallmode == false && fifohandcheck == true)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* io pad mode can be only checked by using dssdev connected to the
|
||||
* manager. Ignore checking these for now, add checks when manager
|
||||
* is capable of holding information related to the connected interface
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dss_mgr_check(struct omap_overlay_manager *mgr,
|
||||
struct omap_overlay_manager_info *info,
|
||||
const struct omap_video_timings *mgr_timings,
|
||||
const struct dss_lcd_mgr_config *lcd_config,
|
||||
struct omap_overlay_info **overlay_infos)
|
||||
{
|
||||
struct omap_overlay *ovl;
|
||||
@ -683,6 +714,10 @@ int dss_mgr_check(struct omap_overlay_manager *mgr,
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = dss_mgr_check_lcd_config(mgr, lcd_config);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
list_for_each_entry(ovl, &mgr->overlays, list) {
|
||||
struct omap_overlay_info *oi;
|
||||
int r;
|
||||
|
||||
@ -528,14 +528,24 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
|
||||
struct omap_overlay_manager *lcd_mgr;
|
||||
struct omap_overlay_manager *tv_mgr;
|
||||
struct omap_overlay_manager *lcd2_mgr = NULL;
|
||||
struct omap_overlay_manager *lcd3_mgr = NULL;
|
||||
struct omap_overlay_manager *mgr = NULL;
|
||||
|
||||
lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
|
||||
tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
|
||||
lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_CHANNEL_LCD);
|
||||
tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_CHANNEL_DIGIT);
|
||||
if (dss_has_feature(FEAT_MGR_LCD3))
|
||||
lcd3_mgr = omap_dss_get_overlay_manager(OMAP_DSS_CHANNEL_LCD3);
|
||||
if (dss_has_feature(FEAT_MGR_LCD2))
|
||||
lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2);
|
||||
lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_CHANNEL_LCD2);
|
||||
|
||||
if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
|
||||
if (dssdev->channel == OMAP_DSS_CHANNEL_LCD3) {
|
||||
if (!lcd3_mgr->device || force) {
|
||||
if (lcd3_mgr->device)
|
||||
lcd3_mgr->unset_device(lcd3_mgr);
|
||||
lcd3_mgr->set_device(lcd3_mgr, dssdev);
|
||||
mgr = lcd3_mgr;
|
||||
}
|
||||
} else if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
|
||||
if (!lcd2_mgr->device || force) {
|
||||
if (lcd2_mgr->device)
|
||||
lcd2_mgr->unset_device(lcd2_mgr);
|
||||
@ -677,3 +687,16 @@ int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Checks if replication logic should be used. Only use when overlay is in
|
||||
* RGB12U or RGB16 mode, and video port width interface is 18bpp or 24bpp
|
||||
*/
|
||||
bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
|
||||
enum omap_color_mode mode)
|
||||
{
|
||||
if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16)
|
||||
return false;
|
||||
|
||||
return config.video_port_width > 16;
|
||||
}
|
||||
|
||||
@ -300,10 +300,11 @@ void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
|
||||
}
|
||||
EXPORT_SYMBOL(omap_rfbi_write_pixels);
|
||||
|
||||
static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
|
||||
static int rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
|
||||
u16 height, void (*callback)(void *data), void *data)
|
||||
{
|
||||
u32 l;
|
||||
int r;
|
||||
struct omap_video_timings timings = {
|
||||
.hsw = 1,
|
||||
.hfp = 1,
|
||||
@ -322,7 +323,9 @@ static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
|
||||
|
||||
dss_mgr_set_timings(dssdev->manager, &timings);
|
||||
|
||||
dispc_mgr_enable(dssdev->manager->id, true);
|
||||
r = dss_mgr_enable(dssdev->manager);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
rfbi.framedone_callback = callback;
|
||||
rfbi.framedone_callback_data = data;
|
||||
@ -335,6 +338,8 @@ static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
|
||||
l = FLD_MOD(l, 1, 4, 4); /* ITE */
|
||||
|
||||
rfbi_write_reg(RFBI_CONTROL, l);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void framedone_callback(void *data, u32 mask)
|
||||
@ -814,8 +819,11 @@ int omap_rfbi_update(struct omap_dss_device *dssdev,
|
||||
u16 x, u16 y, u16 w, u16 h,
|
||||
void (*callback)(void *), void *data)
|
||||
{
|
||||
rfbi_transfer_area(dssdev, w, h, callback, data);
|
||||
return 0;
|
||||
int r;
|
||||
|
||||
r = rfbi_transfer_area(dssdev, w, h, callback, data);
|
||||
|
||||
return r;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_rfbi_update);
|
||||
|
||||
@ -859,6 +867,22 @@ static void rfbi_dump_regs(struct seq_file *s)
|
||||
#undef DUMPREG
|
||||
}
|
||||
|
||||
static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct dss_lcd_mgr_config mgr_config;
|
||||
|
||||
mgr_config.io_pad_mode = DSS_IO_PAD_MODE_RFBI;
|
||||
|
||||
mgr_config.stallmode = true;
|
||||
/* Do we need fifohandcheck for RFBI? */
|
||||
mgr_config.fifohandcheck = false;
|
||||
|
||||
mgr_config.video_port_width = dssdev->ctrl.pixel_size;
|
||||
mgr_config.lcden_sig_polarity = 0;
|
||||
|
||||
dss_mgr_set_lcd_config(dssdev->manager, &mgr_config);
|
||||
}
|
||||
|
||||
int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
int r;
|
||||
@ -885,13 +909,7 @@ int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
|
||||
goto err1;
|
||||
}
|
||||
|
||||
dispc_mgr_set_lcd_display_type(dssdev->manager->id,
|
||||
OMAP_DSS_LCD_DISPLAY_TFT);
|
||||
|
||||
dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_RFBI);
|
||||
dispc_mgr_enable_stallmode(dssdev->manager->id, true);
|
||||
|
||||
dispc_mgr_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
|
||||
rfbi_config_lcd_manager(dssdev);
|
||||
|
||||
rfbi_configure(dssdev->phy.rfbi.channel,
|
||||
dssdev->ctrl.pixel_size,
|
||||
|
||||
@ -32,19 +32,21 @@
|
||||
static struct {
|
||||
bool update_enabled;
|
||||
struct regulator *vdds_sdi_reg;
|
||||
|
||||
struct dss_lcd_mgr_config mgr_config;
|
||||
} sdi;
|
||||
|
||||
static void sdi_basic_init(struct omap_dss_device *dssdev)
|
||||
|
||||
static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
|
||||
{
|
||||
dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
|
||||
dispc_mgr_enable_stallmode(dssdev->manager->id, false);
|
||||
sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
|
||||
|
||||
dispc_mgr_set_lcd_display_type(dssdev->manager->id,
|
||||
OMAP_DSS_LCD_DISPLAY_TFT);
|
||||
sdi.mgr_config.stallmode = false;
|
||||
sdi.mgr_config.fifohandcheck = false;
|
||||
|
||||
dispc_mgr_set_tft_data_lines(dssdev->manager->id, 24);
|
||||
dispc_lcd_enable_signal_polarity(1);
|
||||
sdi.mgr_config.video_port_width = 24;
|
||||
sdi.mgr_config.lcden_sig_polarity = 1;
|
||||
|
||||
dss_mgr_set_lcd_config(dssdev->manager, &sdi.mgr_config);
|
||||
}
|
||||
|
||||
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
@ -52,8 +54,6 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
struct omap_video_timings *t = &dssdev->panel.timings;
|
||||
struct dss_clock_info dss_cinfo;
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
u16 lck_div, pck_div;
|
||||
unsigned long fck;
|
||||
unsigned long pck;
|
||||
int r;
|
||||
|
||||
@ -76,24 +76,17 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
if (r)
|
||||
goto err_get_dispc;
|
||||
|
||||
sdi_basic_init(dssdev);
|
||||
|
||||
/* 15.5.9.1.2 */
|
||||
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
|
||||
dssdev->panel.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
|
||||
dssdev->panel.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
|
||||
|
||||
dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
|
||||
dssdev->panel.acbi, dssdev->panel.acb);
|
||||
|
||||
r = dss_calc_clock_div(1, t->pixel_clock * 1000,
|
||||
&dss_cinfo, &dispc_cinfo);
|
||||
r = dss_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
|
||||
if (r)
|
||||
goto err_calc_clock_div;
|
||||
|
||||
fck = dss_cinfo.fck;
|
||||
lck_div = dispc_cinfo.lck_div;
|
||||
pck_div = dispc_cinfo.pck_div;
|
||||
sdi.mgr_config.clock_info = dispc_cinfo;
|
||||
|
||||
pck = fck / lck_div / pck_div / 1000;
|
||||
pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
|
||||
|
||||
if (pck != t->pixel_clock) {
|
||||
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
|
||||
@ -110,9 +103,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
if (r)
|
||||
goto err_set_dss_clock_div;
|
||||
|
||||
r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
|
||||
if (r)
|
||||
goto err_set_dispc_clock_div;
|
||||
sdi_config_lcd_manager(dssdev);
|
||||
|
||||
dss_sdi_init(dssdev->phy.sdi.datapairs);
|
||||
r = dss_sdi_enable();
|
||||
@ -129,7 +120,6 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
err_mgr_enable:
|
||||
dss_sdi_disable();
|
||||
err_sdi_enable:
|
||||
err_set_dispc_clock_div:
|
||||
err_set_dss_clock_div:
|
||||
err_calc_clock_div:
|
||||
dispc_runtime_put();
|
||||
|
||||
@ -42,30 +42,13 @@ enum hdmi_clk_refsel {
|
||||
HDMI_REFSEL_SYSCLK = 3
|
||||
};
|
||||
|
||||
/* HDMI timing structure */
|
||||
struct hdmi_video_timings {
|
||||
u16 x_res;
|
||||
u16 y_res;
|
||||
/* Unit: KHz */
|
||||
u32 pixel_clock;
|
||||
u16 hsw;
|
||||
u16 hfp;
|
||||
u16 hbp;
|
||||
u16 vsw;
|
||||
u16 vfp;
|
||||
u16 vbp;
|
||||
bool vsync_pol;
|
||||
bool hsync_pol;
|
||||
bool interlace;
|
||||
};
|
||||
|
||||
struct hdmi_cm {
|
||||
int code;
|
||||
int mode;
|
||||
};
|
||||
|
||||
struct hdmi_config {
|
||||
struct hdmi_video_timings timings;
|
||||
struct omap_video_timings timings;
|
||||
struct hdmi_cm cm;
|
||||
};
|
||||
|
||||
@ -177,7 +160,7 @@ struct hdmi_ip_data {
|
||||
|
||||
/* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
|
||||
int hpd_gpio;
|
||||
bool phy_tx_enabled;
|
||||
struct mutex lock;
|
||||
};
|
||||
int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
|
||||
void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
|
||||
|
||||
@ -157,6 +157,10 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
|
||||
/* PHY_PWR_CMD */
|
||||
static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
|
||||
{
|
||||
/* Return if already the state */
|
||||
if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val)
|
||||
return 0;
|
||||
|
||||
/* Command for power control of HDMI PHY */
|
||||
REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
|
||||
|
||||
@ -231,21 +235,13 @@ void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
|
||||
|
||||
static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
|
||||
{
|
||||
unsigned long flags;
|
||||
bool hpd;
|
||||
int r;
|
||||
/* this should be in ti_hdmi_4xxx_ip private data */
|
||||
static DEFINE_SPINLOCK(phy_tx_lock);
|
||||
|
||||
spin_lock_irqsave(&phy_tx_lock, flags);
|
||||
mutex_lock(&ip_data->lock);
|
||||
|
||||
hpd = gpio_get_value(ip_data->hpd_gpio);
|
||||
|
||||
if (hpd == ip_data->phy_tx_enabled) {
|
||||
spin_unlock_irqrestore(&phy_tx_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (hpd)
|
||||
r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
|
||||
else
|
||||
@ -257,9 +253,8 @@ static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ip_data->phy_tx_enabled = hpd;
|
||||
err:
|
||||
spin_unlock_irqrestore(&phy_tx_lock, flags);
|
||||
mutex_unlock(&ip_data->lock);
|
||||
return r;
|
||||
}
|
||||
|
||||
@ -327,7 +322,6 @@ void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
|
||||
free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
|
||||
|
||||
hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
|
||||
ip_data->phy_tx_enabled = false;
|
||||
}
|
||||
|
||||
static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
|
||||
@ -747,11 +741,15 @@ static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
|
||||
static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
|
||||
{
|
||||
u32 r;
|
||||
bool vsync_pol, hsync_pol;
|
||||
pr_debug("Enter hdmi_wp_video_config_interface\n");
|
||||
|
||||
vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
|
||||
r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
|
||||
r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7);
|
||||
r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6);
|
||||
r = FLD_MOD(r, vsync_pol, 7, 7);
|
||||
r = FLD_MOD(r, hsync_pol, 6, 6);
|
||||
r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
|
||||
r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
|
||||
hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
|
||||
|
||||
@ -272,6 +272,8 @@ const struct omap_video_timings omap_dss_pal_timings = {
|
||||
.vsw = 5,
|
||||
.vfp = 5,
|
||||
.vbp = 41,
|
||||
|
||||
.interlace = true,
|
||||
};
|
||||
EXPORT_SYMBOL(omap_dss_pal_timings);
|
||||
|
||||
@ -285,6 +287,8 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
|
||||
.vsw = 6,
|
||||
.vfp = 6,
|
||||
.vbp = 31,
|
||||
|
||||
.interlace = true,
|
||||
};
|
||||
EXPORT_SYMBOL(omap_dss_ntsc_timings);
|
||||
|
||||
@ -930,7 +934,7 @@ static int __exit omap_venchw_remove(struct platform_device *pdev)
|
||||
static int venc_runtime_suspend(struct device *dev)
|
||||
{
|
||||
if (venc.tv_dac_clk)
|
||||
clk_disable(venc.tv_dac_clk);
|
||||
clk_disable_unprepare(venc.tv_dac_clk);
|
||||
|
||||
dispc_runtime_put();
|
||||
|
||||
@ -946,7 +950,7 @@ static int venc_runtime_resume(struct device *dev)
|
||||
return r;
|
||||
|
||||
if (venc.tv_dac_clk)
|
||||
clk_enable(venc.tv_dac_clk);
|
||||
clk_prepare_enable(venc.tv_dac_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -733,6 +733,12 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
|
||||
var->lower_margin = timings.vfp;
|
||||
var->hsync_len = timings.hsw;
|
||||
var->vsync_len = timings.vsw;
|
||||
var->sync |= timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
|
||||
FB_SYNC_HOR_HIGH_ACT : 0;
|
||||
var->sync |= timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
|
||||
FB_SYNC_VERT_HIGH_ACT : 0;
|
||||
var->vmode = timings.interlace ?
|
||||
FB_VMODE_INTERLACED : FB_VMODE_NONINTERLACED;
|
||||
} else {
|
||||
var->pixclock = 0;
|
||||
var->left_margin = 0;
|
||||
@ -741,12 +747,10 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
|
||||
var->lower_margin = 0;
|
||||
var->hsync_len = 0;
|
||||
var->vsync_len = 0;
|
||||
var->sync = 0;
|
||||
var->vmode = FB_VMODE_NONINTERLACED;
|
||||
}
|
||||
|
||||
/* TODO: get these from panel->config */
|
||||
var->vmode = FB_VMODE_NONINTERLACED;
|
||||
var->sync = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1993,6 +1997,7 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
|
||||
}
|
||||
|
||||
static int omapfb_mode_to_timings(const char *mode_str,
|
||||
struct omap_dss_device *display,
|
||||
struct omap_video_timings *timings, u8 *bpp)
|
||||
{
|
||||
struct fb_info *fbi;
|
||||
@ -2046,6 +2051,14 @@ static int omapfb_mode_to_timings(const char *mode_str,
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (display->driver->get_timings) {
|
||||
display->driver->get_timings(display, timings);
|
||||
} else {
|
||||
timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
|
||||
timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
|
||||
}
|
||||
|
||||
timings->pixel_clock = PICOS2KHZ(var->pixclock);
|
||||
timings->hbp = var->left_margin;
|
||||
timings->hfp = var->right_margin;
|
||||
@ -2055,6 +2068,13 @@ static int omapfb_mode_to_timings(const char *mode_str,
|
||||
timings->vsw = var->vsync_len;
|
||||
timings->x_res = var->xres;
|
||||
timings->y_res = var->yres;
|
||||
timings->hsync_level = var->sync & FB_SYNC_HOR_HIGH_ACT ?
|
||||
OMAPDSS_SIG_ACTIVE_HIGH :
|
||||
OMAPDSS_SIG_ACTIVE_LOW;
|
||||
timings->vsync_level = var->sync & FB_SYNC_VERT_HIGH_ACT ?
|
||||
OMAPDSS_SIG_ACTIVE_HIGH :
|
||||
OMAPDSS_SIG_ACTIVE_LOW;
|
||||
timings->interlace = var->vmode & FB_VMODE_INTERLACED;
|
||||
|
||||
switch (var->bits_per_pixel) {
|
||||
case 16:
|
||||
@ -2085,7 +2105,7 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
|
||||
struct omap_video_timings timings, temp_timings;
|
||||
struct omapfb_display_data *d;
|
||||
|
||||
r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
|
||||
r = omapfb_mode_to_timings(mode_str, display, &timings, &bpp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
@ -2178,8 +2198,17 @@ static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
|
||||
}
|
||||
|
||||
static void fb_videomode_to_omap_timings(struct fb_videomode *m,
|
||||
struct omap_dss_device *display,
|
||||
struct omap_video_timings *t)
|
||||
{
|
||||
if (display->driver->get_timings) {
|
||||
display->driver->get_timings(display, t);
|
||||
} else {
|
||||
t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
|
||||
t->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
|
||||
}
|
||||
|
||||
t->x_res = m->xres;
|
||||
t->y_res = m->yres;
|
||||
t->pixel_clock = PICOS2KHZ(m->pixclock);
|
||||
@ -2189,6 +2218,13 @@ static void fb_videomode_to_omap_timings(struct fb_videomode *m,
|
||||
t->vsw = m->vsync_len;
|
||||
t->vfp = m->lower_margin;
|
||||
t->vbp = m->upper_margin;
|
||||
t->hsync_level = m->sync & FB_SYNC_HOR_HIGH_ACT ?
|
||||
OMAPDSS_SIG_ACTIVE_HIGH :
|
||||
OMAPDSS_SIG_ACTIVE_LOW;
|
||||
t->vsync_level = m->sync & FB_SYNC_VERT_HIGH_ACT ?
|
||||
OMAPDSS_SIG_ACTIVE_HIGH :
|
||||
OMAPDSS_SIG_ACTIVE_LOW;
|
||||
t->interlace = m->vmode & FB_VMODE_INTERLACED;
|
||||
}
|
||||
|
||||
static int omapfb_find_best_mode(struct omap_dss_device *display,
|
||||
@ -2231,7 +2267,7 @@ static int omapfb_find_best_mode(struct omap_dss_device *display,
|
||||
if (m->xres == 2880 || m->xres == 1440)
|
||||
continue;
|
||||
|
||||
fb_videomode_to_omap_timings(m, &t);
|
||||
fb_videomode_to_omap_timings(m, display, &t);
|
||||
|
||||
r = display->driver->check_timings(display, &t);
|
||||
if (r == 0 && best_xres < m->xres) {
|
||||
@ -2245,7 +2281,8 @@ static int omapfb_find_best_mode(struct omap_dss_device *display,
|
||||
goto err2;
|
||||
}
|
||||
|
||||
fb_videomode_to_omap_timings(&specs->modedb[best_idx], timings);
|
||||
fb_videomode_to_omap_timings(&specs->modedb[best_idx], display,
|
||||
timings);
|
||||
|
||||
r = 0;
|
||||
|
||||
|
||||
@ -48,6 +48,10 @@
|
||||
#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
|
||||
#define DISPC_IRQ_FRAMEDONETV (1 << 24)
|
||||
#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
|
||||
#define DISPC_IRQ_FRAMEDONE3 (1 << 26)
|
||||
#define DISPC_IRQ_VSYNC3 (1 << 27)
|
||||
#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 28)
|
||||
#define DISPC_IRQ_SYNC_LOST3 (1 << 29)
|
||||
|
||||
struct omap_dss_device;
|
||||
struct omap_overlay_manager;
|
||||
@ -75,6 +79,7 @@ enum omap_channel {
|
||||
OMAP_DSS_CHANNEL_LCD = 0,
|
||||
OMAP_DSS_CHANNEL_DIGIT = 1,
|
||||
OMAP_DSS_CHANNEL_LCD2 = 2,
|
||||
OMAP_DSS_CHANNEL_LCD3 = 3,
|
||||
};
|
||||
|
||||
enum omap_color_mode {
|
||||
@ -99,11 +104,6 @@ enum omap_color_mode {
|
||||
OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
|
||||
};
|
||||
|
||||
enum omap_lcd_display_type {
|
||||
OMAP_DSS_LCD_DISPLAY_STN,
|
||||
OMAP_DSS_LCD_DISPLAY_TFT,
|
||||
};
|
||||
|
||||
enum omap_dss_load_mode {
|
||||
OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
|
||||
OMAP_DSS_LOAD_CLUT_ONLY = 1,
|
||||
@ -121,15 +121,15 @@ enum omap_rfbi_te_mode {
|
||||
OMAP_DSS_RFBI_TE_MODE_2 = 2,
|
||||
};
|
||||
|
||||
enum omap_panel_config {
|
||||
OMAP_DSS_LCD_IVS = 1<<0,
|
||||
OMAP_DSS_LCD_IHS = 1<<1,
|
||||
OMAP_DSS_LCD_IPC = 1<<2,
|
||||
OMAP_DSS_LCD_IEO = 1<<3,
|
||||
OMAP_DSS_LCD_RF = 1<<4,
|
||||
OMAP_DSS_LCD_ONOFF = 1<<5,
|
||||
enum omap_dss_signal_level {
|
||||
OMAPDSS_SIG_ACTIVE_HIGH = 0,
|
||||
OMAPDSS_SIG_ACTIVE_LOW = 1,
|
||||
};
|
||||
|
||||
OMAP_DSS_LCD_TFT = 1<<20,
|
||||
enum omap_dss_signal_edge {
|
||||
OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
|
||||
OMAPDSS_DRIVE_SIG_RISING_EDGE,
|
||||
OMAPDSS_DRIVE_SIG_FALLING_EDGE,
|
||||
};
|
||||
|
||||
enum omap_dss_venc_type {
|
||||
@ -167,13 +167,6 @@ enum omap_dss_audio_state {
|
||||
OMAP_DSS_AUDIO_PLAYING,
|
||||
};
|
||||
|
||||
/* XXX perhaps this should be removed */
|
||||
enum omap_dss_overlay_managers {
|
||||
OMAP_DSS_OVL_MGR_LCD,
|
||||
OMAP_DSS_OVL_MGR_TV,
|
||||
OMAP_DSS_OVL_MGR_LCD2,
|
||||
};
|
||||
|
||||
enum omap_dss_rotation_type {
|
||||
OMAP_DSS_ROT_DMA = 1 << 0,
|
||||
OMAP_DSS_ROT_VRFB = 1 << 1,
|
||||
@ -268,9 +261,6 @@ struct omap_dss_dsi_videomode_data {
|
||||
int hfp_blanking_mode;
|
||||
|
||||
/* Video port sync events */
|
||||
int vp_de_pol;
|
||||
int vp_hsync_pol;
|
||||
int vp_vsync_pol;
|
||||
bool vp_vsync_end;
|
||||
bool vp_hsync_end;
|
||||
|
||||
@ -346,6 +336,19 @@ struct omap_video_timings {
|
||||
u16 vfp; /* Vertical front porch */
|
||||
/* Unit: line clocks */
|
||||
u16 vbp; /* Vertical back porch */
|
||||
|
||||
/* Vsync logic level */
|
||||
enum omap_dss_signal_level vsync_level;
|
||||
/* Hsync logic level */
|
||||
enum omap_dss_signal_level hsync_level;
|
||||
/* Interlaced or Progressive timings */
|
||||
bool interlace;
|
||||
/* Pixel clock edge to drive LCD data */
|
||||
enum omap_dss_signal_edge data_pclk_edge;
|
||||
/* Data enable logic level */
|
||||
enum omap_dss_signal_level de_level;
|
||||
/* Pixel clock edges to drive HSYNC and VSYNC signals */
|
||||
enum omap_dss_signal_edge sync_pclk_edge;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP2_DSS_VENC
|
||||
@ -559,8 +562,6 @@ struct omap_dss_device {
|
||||
/* Unit: line clocks */
|
||||
int acb; /* ac-bias pin frequency */
|
||||
|
||||
enum omap_panel_config config;
|
||||
|
||||
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
|
||||
enum omap_dss_dsi_mode dsi_mode;
|
||||
struct omap_dss_dsi_videomode_data dsi_vm_data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user