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phy: rockchip-inno-usb2: add support of usb2-phy for rk3328
Add usb2-phy config information in the data of match table for rk3328. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -1138,6 +1138,49 @@ disable_clks:
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return ret;
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}
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static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
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{
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.reg = 0x100,
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.num_ports = 2,
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.clkout_ctl = { 0x108, 4, 4, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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.phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
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.bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
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.bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
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.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
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.ls_det_en = { 0x0110, 0, 0, 0, 1 },
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.ls_det_st = { 0x0114, 0, 0, 0, 1 },
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.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
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.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
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.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
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.utmi_ls = { 0x0120, 5, 4, 0, 1 },
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
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.ls_det_en = { 0x110, 1, 1, 0, 1 },
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.ls_det_st = { 0x114, 1, 1, 0, 1 },
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.ls_det_clr = { 0x118, 1, 1, 0, 1 },
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.utmi_ls = { 0x120, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x120, 19, 19, 0, 1 }
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}
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},
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.chg_det = {
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.opmode = { 0x0100, 3, 0, 5, 1 },
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.cp_det = { 0x0120, 24, 24, 0, 1 },
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.dcp_det = { 0x0120, 23, 23, 0, 1 },
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.dp_det = { 0x0120, 25, 25, 0, 1 },
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.idm_sink_en = { 0x0108, 8, 8, 0, 1 },
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.idp_sink_en = { 0x0108, 7, 7, 0, 1 },
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.idp_src_en = { 0x0108, 9, 9, 0, 1 },
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.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
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.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
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.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
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},
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},
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{ /* sentinel */ }
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};
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static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
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{
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.reg = 0x700,
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@ -1220,6 +1263,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
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};
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static const struct of_device_id rockchip_usb2phy_dt_match[] = {
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{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
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{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
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{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
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{}
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