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powerpc/fsl: Added aliased MSIIR register address to MSI node in dts
The MSIIR register for each MSI bank is aliased to a different address. The MSI node reg property was updated to contain this address: e.g. reg = <0x41600 0x200 0x44140 4>; The first region contains the address and length of the MSI register set and the second region contains the address of the aliased MSIIR register at 0x44140. Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -6,8 +6,10 @@ Required properties:
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etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
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the parent type.
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- reg : should contain the address and the length of the shared message
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interrupt register set.
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- reg : It may contain one or two regions. The first region should contain
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the address and the length of the shared message interrupt register set.
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The second region should contain the address of aliased MSIIR register for
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platforms that have such an alias.
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- msi-available-ranges: use <start count> style section to define which
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msi interrupt can be used in the 256 msi interrupts. This property is
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@ -53,7 +53,7 @@ timer@41100 {
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msi0: msi@41600 {
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compatible = "fsl,mpic-msi";
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reg = <0x41600 0x200>;
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reg = <0x41600 0x200 0x44140 4>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0 0 0
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@ -68,7 +68,7 @@ msi0: msi@41600 {
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msi1: msi@41800 {
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compatible = "fsl,mpic-msi";
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reg = <0x41800 0x200>;
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reg = <0x41800 0x200 0x45140 4>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe8 0 0 0
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@ -83,7 +83,7 @@ msi1: msi@41800 {
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msi2: msi@41a00 {
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compatible = "fsl,mpic-msi";
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reg = <0x41a00 0x200>;
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reg = <0x41a00 0x200 0x46140 4>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xf0 0 0 0
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