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clk: tegra: Update struct tegra_clk_pll_params kerneldoc

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Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.

Reported-by: Benson Leung <bleung@chromium.org>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2015-06-18 17:28:16 -04:00
parent fdc1feadc0
commit db592c4e2b
1 changed files with 15 additions and 3 deletions
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18
drivers/clk/tegra/clk.h
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@ -157,7 +157,7 @@ struct div_nmp {
};
/**
* struct clk_pll_params - PLL parameters
* struct tegra_clk_pll_params - PLL parameters
*
* @input_min: Minimum input frequency
* @input_max: Maximum input frequency
@ -168,12 +168,24 @@ struct div_nmp {
* @base_reg: PLL base reg offset
* @misc_reg: PLL misc reg offset
* @lock_reg: PLL lock reg offset
* @lock_bit_idx: Bit index for PLL lock status
* @lock_mask: Bitmask for PLL lock status
* @lock_enable_bit_idx: Bit index to enable PLL lock
* @iddq_reg: PLL IDDQ register offset
* @iddq_bit_idx: Bit index to enable PLL IDDQ
* @aux_reg: AUX register offset
* @dyn_ramp_reg: Dynamic ramp control register offset
* @ext_misc_reg: Miscellaneous control register offsets
* @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
* @pmc_divp_reg: p divider PMC override register offset (PLLM)
* @flags: PLL flags
* @stepa_shift: Dynamic ramp step A field shift
* @stepb_shift: Dynamic ramp step B field shift
* @lock_delay: Delay in us if PLL lock is not used
* @max_p: maximum value for the p divider
* @pdiv_tohw: mapping of p divider to register values
* @div_nmp: offsets and widths on n, m and p fields
* @freq_table: array of frequencies supported by PLL
* @fixed_rate: PLL rate if it is fixed
* @flags: PLL flags
*
* Flags:
* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for