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Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
This commit is contained in:
Joerg Roedel
commit
dc03753b98
@ -48,6 +48,12 @@ conditions.
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from the mmu-masters towards memory) node for this
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SMMU.
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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Example:
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smmu {
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@ -48,7 +48,7 @@
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#include <asm/pgalloc.h>
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/* Maximum number of stream IDs assigned to a single device */
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#define MAX_MASTER_STREAMIDS 8
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#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
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/* Maximum number of context banks per SMMU */
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#define ARM_SMMU_MAX_CBS 128
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@ -60,6 +60,16 @@
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
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/*
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* SMMU global address space with conditional offset to access secure
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* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
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* nsGFSYNR0: 0x450)
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*/
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#define ARM_SMMU_GR0_NS(smmu) \
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((smmu)->base + \
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((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
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? 0x400 : 0))
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/* Page table bits */
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#define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
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#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
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@ -351,6 +361,9 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
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#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
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u32 features;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
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u32 options;
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int version;
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u32 num_context_banks;
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@ -401,6 +414,29 @@ struct arm_smmu_domain {
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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static LIST_HEAD(arm_smmu_devices);
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struct arm_smmu_option_prop {
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u32 opt;
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const char *prop;
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};
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static struct arm_smmu_option_prop arm_smmu_options [] = {
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{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
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{ 0, NULL},
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};
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static void parse_driver_options(struct arm_smmu_device *smmu)
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{
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int i = 0;
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do {
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if (of_property_read_bool(smmu->dev->of_node,
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arm_smmu_options[i].prop)) {
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smmu->options |= arm_smmu_options[i].opt;
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dev_notice(smmu->dev, "option %s\n",
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arm_smmu_options[i].prop);
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}
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} while (arm_smmu_options[++i].opt);
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}
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static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
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struct device_node *dev_node)
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{
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@ -614,16 +650,16 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
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{
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u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
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struct arm_smmu_device *smmu = dev;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
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gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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if (!gfsr)
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return IRQ_NONE;
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gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
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gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
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gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
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if (!gfsr)
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return IRQ_NONE;
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dev_err_ratelimited(smmu->dev,
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"Unexpected global fault, this could be serious\n");
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dev_err_ratelimited(smmu->dev,
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@ -642,7 +678,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
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/* Ensure new page tables are visible to the hardware walker */
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if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
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dsb();
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dsb(ishst);
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} else {
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/*
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* If the SMMU can't walk tables in the CPU caches, treat them
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@ -990,9 +1026,8 @@ static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
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/*
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* Recursively free the page tables for this domain. We don't
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* care about speculative TLB filling, because the TLB will be
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* nuked next time this context bank is re-allocated and no devices
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* currently map to these tables.
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* care about speculative TLB filling because the tables should
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* not be active in any context bank at this point (SCTLR.M is 0).
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*/
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pgd = pgd_base;
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for (i = 0; i < PTRS_PER_PGD; ++i) {
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@ -1218,7 +1253,7 @@ static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
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static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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unsigned long addr, unsigned long end,
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unsigned long pfn, int flags, int stage)
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unsigned long pfn, int prot, int stage)
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{
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pte_t *pte, *start;
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pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
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@ -1240,28 +1275,28 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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if (stage == 1) {
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pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
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if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
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if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
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pteval |= ARM_SMMU_PTE_AP_RDONLY;
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if (flags & IOMMU_CACHE)
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if (prot & IOMMU_CACHE)
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pteval |= (MAIR_ATTR_IDX_CACHE <<
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ARM_SMMU_PTE_ATTRINDX_SHIFT);
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} else {
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pteval |= ARM_SMMU_PTE_HAP_FAULT;
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if (flags & IOMMU_READ)
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if (prot & IOMMU_READ)
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pteval |= ARM_SMMU_PTE_HAP_READ;
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if (flags & IOMMU_WRITE)
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if (prot & IOMMU_WRITE)
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pteval |= ARM_SMMU_PTE_HAP_WRITE;
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if (flags & IOMMU_CACHE)
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if (prot & IOMMU_CACHE)
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pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
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else
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pteval |= ARM_SMMU_PTE_MEMATTR_NC;
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}
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/* If no access, create a faulting entry to avoid TLB fills */
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if (flags & IOMMU_EXEC)
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if (prot & IOMMU_EXEC)
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pteval &= ~ARM_SMMU_PTE_XN;
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else if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
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else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
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pteval &= ~ARM_SMMU_PTE_PAGE;
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pteval |= ARM_SMMU_PTE_SH_IS;
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@ -1323,7 +1358,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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unsigned long addr, unsigned long end,
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phys_addr_t phys, int flags, int stage)
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phys_addr_t phys, int prot, int stage)
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{
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int ret;
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pmd_t *pmd;
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@ -1347,7 +1382,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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do {
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next = pmd_addr_end(addr, end);
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ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
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flags, stage);
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prot, stage);
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phys += next - addr;
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} while (pmd++, addr = next, addr < end);
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@ -1356,7 +1391,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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unsigned long addr, unsigned long end,
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phys_addr_t phys, int flags, int stage)
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phys_addr_t phys, int prot, int stage)
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{
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int ret = 0;
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pud_t *pud;
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@ -1380,7 +1415,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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do {
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next = pud_addr_end(addr, end);
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ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
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flags, stage);
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prot, stage);
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phys += next - addr;
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} while (pud++, addr = next, addr < end);
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@ -1389,7 +1424,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int flags)
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size_t size, int prot)
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{
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int ret, stage;
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unsigned long end;
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@ -1397,7 +1432,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
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pgd_t *pgd = root_cfg->pgd;
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struct arm_smmu_device *smmu = root_cfg->smmu;
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unsigned long irqflags;
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unsigned long flags;
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if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
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stage = 2;
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@ -1420,14 +1455,14 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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if (paddr & ~output_mask)
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return -ERANGE;
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spin_lock_irqsave(&smmu_domain->lock, irqflags);
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spin_lock_irqsave(&smmu_domain->lock, flags);
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pgd += pgd_index(iova);
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end = iova + size;
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do {
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unsigned long next = pgd_addr_end(iova, end);
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ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
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flags, stage);
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prot, stage);
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if (ret)
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goto out_unlock;
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@ -1436,13 +1471,13 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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} while (pgd++, iova != end);
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out_unlock:
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spin_unlock_irqrestore(&smmu_domain->lock, irqflags);
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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}
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static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int flags)
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phys_addr_t paddr, size_t size, int prot)
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{
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struct arm_smmu_domain *smmu_domain = domain->priv;
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@ -1453,7 +1488,7 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
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if ((phys_addr_t)iova & ~smmu_domain->output_mask)
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return -ERANGE;
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return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
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return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
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}
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static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
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@ -1597,9 +1632,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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int i = 0;
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u32 reg;
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/* Clear Global FSR */
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reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR);
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/* clear global FSR */
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reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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/* Mark all SMRn as invalid and all S2CRn as bypass */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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@ -1619,7 +1654,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
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reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
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reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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/* Enable fault reporting */
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reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
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@ -1638,7 +1673,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Push the button */
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arm_smmu_tlb_sync(smmu);
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writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0);
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writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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}
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static int arm_smmu_id_size_to_bits(int size)
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@ -1885,6 +1920,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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if (err)
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goto out_put_parent;
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parse_driver_options(smmu);
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if (smmu->version > 1 &&
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smmu->num_context_banks != smmu->num_context_irqs) {
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dev_err(dev,
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@ -1969,7 +2006,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
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free_irq(smmu->irqs[i], smmu);
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/* Turn the thing off */
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writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
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writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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return 0;
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}
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