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https://github.com/FEX-Emu/linux.git
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Merge branch 'topic/pl08x' into for-linus
This commit is contained in:
Vinod Koul
commit
dd2b9ff8a9
@ -106,6 +106,7 @@ struct pl08x_driver_data;
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/**
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* struct vendor_data - vendor-specific config parameters for PL08x derivatives
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* @config_offset: offset to the configuration register
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* @channels: the number of channels available in this variant
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* @signals: the number of request signals available from the hardware
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* @dualmaster: whether this version supports dual AHB masters or not.
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@ -145,6 +146,8 @@ struct pl08x_bus_data {
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/**
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* struct pl08x_phy_chan - holder for the physical channels
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* @id: physical index to this channel
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* @base: memory base address for this physical channel
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* @reg_config: configuration address for this physical channel
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* @lock: a lock to use when altering an instance of this struct
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* @serving: the virtual channel currently being served by this physical
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* channel
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@ -203,7 +206,7 @@ struct pl08x_txd {
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};
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/**
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* enum pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* states
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* @PL08X_CHAN_IDLE: the channel is idle
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* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
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@ -226,9 +229,8 @@ enum pl08x_dma_chan_state {
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* @phychan: the physical channel utilized by this channel, if there is one
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* @name: name of channel
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* @cd: channel platform data
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* @runtime_addr: address for RX/TX according to the runtime config
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* @cfg: slave configuration
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* @at: active transaction on this channel
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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@ -262,7 +264,7 @@ struct pl08x_dma_chan {
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* @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
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* fetches
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* @mem_buses: set to indicate memory transfers on AHB2.
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* @lock: a spinlock for this struct
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* @lli_words: how many words are used in each LLI item for this variant
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*/
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struct pl08x_driver_data {
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struct dma_device slave;
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@ -417,7 +419,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
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/* Enable the DMA channel */
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/* Do not access config register until channel shows as disabled */
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while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
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while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
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cpu_relax();
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/* Do not access config register until channel shows as inactive */
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@ -484,8 +486,8 @@ static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
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writel(val, ch->reg_config);
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writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
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writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
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writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
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writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
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}
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static inline u32 get_bytes_in_cctl(u32 cctl)
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@ -1834,7 +1836,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
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return IRQ_NONE;
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for (i = 0; i < pl08x->vd->channels; i++) {
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if (((1 << i) & err) || ((1 << i) & tc)) {
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if ((BIT(i) & err) || (BIT(i) & tc)) {
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/* Locate physical channel */
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struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
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struct pl08x_dma_chan *plchan = phychan->serving;
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@ -1872,7 +1874,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
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}
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spin_unlock(&plchan->vc.lock);
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mask |= (1 << i);
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mask |= BIT(i);
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}
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}
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@ -38,24 +38,16 @@
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#define PL080_SOFT_LSREQ (0x2C)
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#define PL080_CONFIG (0x30)
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#define PL080_CONFIG_M2_BE (1 << 2)
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#define PL080_CONFIG_M1_BE (1 << 1)
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#define PL080_CONFIG_ENABLE (1 << 0)
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#define PL080_CONFIG_M2_BE BIT(2)
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#define PL080_CONFIG_M1_BE BIT(1)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_SYNC (0x34)
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/* Per channel configuration registers */
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#define PL080_Cx_STRIDE (0x20)
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/* Per channel configuration registers */
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#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
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#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
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#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
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#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
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#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
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#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
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#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
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#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
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#define PL080_CH_SRC_ADDR (0x00)
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#define PL080_CH_DST_ADDR (0x04)
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#define PL080_CH_LLI (0x08)
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@ -66,18 +58,18 @@
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#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
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#define PL080_LLI_ADDR_SHIFT (2)
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#define PL080_LLI_LM_AHB2 (1 << 0)
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#define PL080_LLI_LM_AHB2 BIT(0)
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#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
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#define PL080_CONTROL_TC_IRQ_EN BIT(31)
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#define PL080_CONTROL_PROT_MASK (0x7 << 28)
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#define PL080_CONTROL_PROT_SHIFT (28)
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#define PL080_CONTROL_PROT_CACHE (1 << 30)
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#define PL080_CONTROL_PROT_BUFF (1 << 29)
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#define PL080_CONTROL_PROT_SYS (1 << 28)
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#define PL080_CONTROL_DST_INCR (1 << 27)
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#define PL080_CONTROL_SRC_INCR (1 << 26)
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#define PL080_CONTROL_DST_AHB2 (1 << 25)
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#define PL080_CONTROL_SRC_AHB2 (1 << 24)
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#define PL080_CONTROL_PROT_CACHE BIT(30)
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#define PL080_CONTROL_PROT_BUFF BIT(29)
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#define PL080_CONTROL_PROT_SYS BIT(28)
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#define PL080_CONTROL_DST_INCR BIT(27)
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#define PL080_CONTROL_SRC_INCR BIT(26)
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#define PL080_CONTROL_DST_AHB2 BIT(25)
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#define PL080_CONTROL_SRC_AHB2 BIT(24)
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#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
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#define PL080_CONTROL_DWIDTH_SHIFT (21)
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#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
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@ -103,20 +95,20 @@
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#define PL080_WIDTH_16BIT (0x1)
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#define PL080_WIDTH_32BIT (0x2)
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#define PL080N_CONFIG_ITPROT (1 << 20)
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#define PL080N_CONFIG_SECPROT (1 << 19)
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#define PL080_CONFIG_HALT (1 << 18)
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#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
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#define PL080_CONFIG_LOCK (1 << 16)
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#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
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#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
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#define PL080N_CONFIG_ITPROT BIT(20)
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#define PL080N_CONFIG_SECPROT BIT(19)
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#define PL080_CONFIG_HALT BIT(18)
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#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
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#define PL080_CONFIG_LOCK BIT(16)
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#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
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#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
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#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
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#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
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#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
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#define PL080_CONFIG_DST_SEL_SHIFT (6)
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#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
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#define PL080_CONFIG_SRC_SEL_SHIFT (1)
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#define PL080_CONFIG_ENABLE (1 << 0)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_FLOW_MEM2MEM (0x0)
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#define PL080_FLOW_MEM2PER (0x1)
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