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ALSA: hda - add more ML register definitions
This patch refines the definition of AZX_MLCTL_SPA and AZX_MLCTL_CPA and add more definitions of ML registers Signed-off-by: Libin Yang <libin.yang@intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -261,9 +261,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define AZX_REG_ML_LOUTPAY 0x20
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#define AZX_REG_ML_LINPAY 0x30
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#define AZX_MLCTL_SPA (1<<16)
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#define AZX_MLCTL_CPA 23
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#define ML_LCTL_SCF_MASK 0xF
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#define AZX_MLCTL_SPA (0x1 << 16)
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#define AZX_MLCTL_CPA (0x1 << 23)
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#define AZX_MLCTL_SPA_SHIFT 16
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#define AZX_MLCTL_CPA_SHIFT 23
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/* registers for DMA Resume Capability Structure */
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#define AZX_DRSM_CAP_ID 0x5
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@ -171,7 +171,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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{
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int timeout;
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u32 val;
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int mask = (1 << AZX_MLCTL_CPA);
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int mask = (1 << AZX_MLCTL_CPA_SHIFT);
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udelay(3);
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timeout = 150;
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@ -179,10 +179,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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do {
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val = readl(link->ml_addr + AZX_REG_ML_LCTL);
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if (enable) {
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if (((val & mask) >> AZX_MLCTL_CPA))
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if (((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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return 0;
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} else {
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if (!((val & mask) >> AZX_MLCTL_CPA))
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if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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return 0;
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}
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udelay(3);
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