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clk: ux500: Provide u8500_clk with skeleton Device Tree support

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The functional components will be added on a per-clock basis.

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Lee Jones 2013-09-17 10:26:24 +01:00 committed by Linus Walleij
parent 82b0f4b7c5
commit dec759d8ef
1 changed files with 19 additions and 0 deletions
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19
drivers/clk/ux500/u8500_of_clk.c
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@ -7,6 +7,7 @@
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
@ -14,13 +15,27 @@
#include <linux/platform_data/clk-ux500.h>
#include "clk.h"
static const struct of_device_id u8500_clk_of_match[] = {
{ .compatible = "stericsson,u8500-clks", },
{ },
};
void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
u32 clkrst5_base, u32 clkrst6_base)
{
struct prcmu_fw_version *fw_version;
struct device_node *np = NULL;
struct device_node *child = NULL;
const char *sgaclk_parent = NULL;
struct clk *clk;
if (of_have_populated_dt())
np = of_find_matching_node(NULL, u8500_clk_of_match);
if (!np) {
pr_err("Either DT or U8500 Clock node not found\n");
return;
}
/* Clock sources */
clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
CLK_IS_ROOT|CLK_IGNORE_UNUSED);
@ -378,4 +393,8 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
/* Periph6 */
clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
for_each_child_of_node(np, child) {
/* Place holder for supported nodes. */
}
}