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Blackfin arch: unify/cleanup cache code
- to be correct wrt to end ranges - to be optimal with a one-instruction hardware loop Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger
Bryan Wu
parent
f51501551e
commit
ded963a486
@ -1,148 +1,91 @@
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/*
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* File: arch/blackfin/mach-common/cache.S
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* Based on:
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* Author: LG Soft India
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* Blackfin cache control code
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*
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* Created:
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* Description: cache control support
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/cplb.h>
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#include <asm/entry.h>
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#include <asm/blackfin.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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.text
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/*
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* blackfin_cache_flush_range(start, end)
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* Invalidate all cache lines assocoiated with this
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* area of memory.
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/* Since all L1 caches work the same way, we use the same method for flushing
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* them. Only the actual flush instruction differs. We write this in asm as
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* GCC can be hard to coax into writing nice hardware loops.
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*
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* start: Start address
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* end: End address
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* Also, we assume the following register setup:
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* R0 = start address
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* R1 = end address
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*/
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ENTRY(_blackfin_icache_flush_range)
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.macro do_flush flushins:req optflushins optnopins label
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/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
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R1 += -1;
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R2 = -L1_CACHE_BYTES;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC(R3);
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IFLUSH [P0];
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R1 = R1 & R2;
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R1 += L1_CACHE_BYTES;
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/* count = (end - start) >> L1_CACHE_SHIFT */
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R2 = R1 - R0;
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R2 >>= L1_CACHE_SHIFT;
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P1 = R2;
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.ifnb \label
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\label :
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.endif
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P0 = R0;
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LSETUP (1f, 2f) LC1 = P1;
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1:
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IFLUSH [P0++];
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CC = P0 < P1 (iu);
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IF CC JUMP 1b (bp);
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IFLUSH [P0];
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SSYNC(R3);
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.ifnb \optflushins
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\optflushins [P0];
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.endif
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.ifb \optnopins
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2:
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.endif
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\flushins [P0++];
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.ifnb \optnopins
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2: \optnopins;
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.endif
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RTS;
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.endm
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/* Invalidate all instruction cache lines assocoiated with this memory area */
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ENTRY(_blackfin_icache_flush_range)
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do_flush IFLUSH, , nop
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ENDPROC(_blackfin_icache_flush_range)
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/*
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* blackfin_icache_dcache_flush_range(start, end)
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* FLUSH all cache lines assocoiated with this
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* area of memory.
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*
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* start: Start address
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* end: End address
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*/
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/* Flush all cache lines assocoiated with this area of memory. */
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ENTRY(_blackfin_icache_dcache_flush_range)
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R2 = -L1_CACHE_BYTES;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC(R3);
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IFLUSH [P0];
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1:
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FLUSH [P0];
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IFLUSH [P0++];
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CC = P0 < P1 (iu);
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IF CC JUMP 1b (bp);
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IFLUSH [P0];
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FLUSH [P0];
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SSYNC(R3);
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RTS;
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do_flush IFLUSH, FLUSH
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ENDPROC(_blackfin_icache_dcache_flush_range)
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/* Throw away all D-cached data in specified region without any obligation to
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* write them back. However, we must clean the D-cached entries around the
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* boundaries of the start and/or end address is not cache aligned.
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*
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* Start: start address,
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* end : end address.
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* write them back. Since the Blackfin ISA does not have an "invalidate"
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* instruction, we use flush/invalidate. Perhaps as a speed optimization we
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* could bang on the DTEST MMRs ...
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*/
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ENTRY(_blackfin_dcache_invalidate_range)
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R2 = -L1_CACHE_BYTES;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC(R3);
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FLUSHINV[P0];
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1:
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FLUSHINV[P0++];
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CC = P0 < P1 (iu);
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IF CC JUMP 1b (bp);
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/* If the data crosses a cache line, then we'll be pointing to
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* the last cache line, but won't have flushed/invalidated it yet,
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* so do one more.
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*/
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FLUSHINV[P0];
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SSYNC(R3);
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RTS;
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do_flush FLUSHINV
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ENDPROC(_blackfin_dcache_invalidate_range)
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/* Flush all data cache lines assocoiated with this memory area */
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ENTRY(_blackfin_dcache_flush_range)
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R2 = -L1_CACHE_BYTES;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC(R3);
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FLUSH[P0];
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1:
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FLUSH[P0++];
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CC = P0 < P1 (iu);
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IF CC JUMP 1b (bp);
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/* If the data crosses a cache line, then we'll be pointing to
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* the last cache line, but won't have flushed it yet, so do
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* one more.
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*/
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FLUSH[P0];
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SSYNC(R3);
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RTS;
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do_flush FLUSH, , , .Ldfr
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ENDPROC(_blackfin_dcache_flush_range)
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/* Our headers convert the page structure to an address, so just need to flush
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* its contents like normal. We know the start address is page aligned (which
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* greater than our cache alignment), as is the end address. So just jump into
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* the middle of the dcache flush function.
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*/
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ENTRY(_blackfin_dflush_page)
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P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
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P0 = R0;
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CSYNC(R3);
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FLUSH[P0];
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LSETUP (.Lfl1, .Lfl1) LC0 = P1;
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.Lfl1: FLUSH [P0++];
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SSYNC(R3);
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RTS;
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jump .Ldfr;
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ENDPROC(_blackfin_dflush_page)
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