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[TG3]: Add recovery logic when MMIOs are re-ordered
Add recovery logic when we suspect that the system is re-ordering MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx completions and hit BUG_ON() in the tx completion path. tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs that must be strictly ordered (such as the send mailbox). Determining when to enable the flush is currently a manual process of adding known chipsets to a list. The new code replaces the BUG_ON() in the tx completion path with the call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER flag and reset the chip later in the workqueue to recover and start flushing MMIOs to the mailbox. A message to report the problem will be printed. We will then decide whether or not to add the host bridge to the list of chipsets that do re-ordering. We may add some additional code later to print the host bridge's ID so that the user can report it more easily. The assumption that re-ordering can only happen on x86 systems is also removed. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2967,6 +2967,29 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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return err;
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}
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/* This is called whenever we suspect that the system chipset is re-
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* ordering the sequence of MMIO to the tx send mailbox. The symptom
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* is bogus tx completions. We try to recover by setting the
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* TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
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* in the workqueue.
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*/
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static void tg3_tx_recover(struct tg3 *tp)
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{
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BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
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tp->write32_tx_mbox == tg3_write_indirect_mbox);
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printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
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"mapped I/O cycles to the network device, attempting to "
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"recover. Please report the problem to the driver maintainer "
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"and include system chipset information.\n", tp->dev->name);
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spin_lock(&tp->lock);
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spin_lock(&tp->tx_lock);
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tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
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spin_unlock(&tp->tx_lock);
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spin_unlock(&tp->lock);
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}
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/* Tigon3 never reports partial packet sends. So we do not
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* need special logic to handle SKBs that have not had all
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* of their frags sent yet, like SunGEM does.
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@ -2979,9 +3002,13 @@ static void tg3_tx(struct tg3 *tp)
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while (sw_idx != hw_idx) {
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struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
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struct sk_buff *skb = ri->skb;
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int i;
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int i, tx_bug = 0;
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if (unlikely(skb == NULL)) {
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tg3_tx_recover(tp);
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return;
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}
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BUG_ON(skb == NULL);
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pci_unmap_single(tp->pdev,
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pci_unmap_addr(ri, mapping),
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skb_headlen(skb),
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@ -2992,10 +3019,9 @@ static void tg3_tx(struct tg3 *tp)
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sw_idx = NEXT_TX(sw_idx);
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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BUG_ON(sw_idx == hw_idx);
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ri = &tp->tx_buffers[sw_idx];
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BUG_ON(ri->skb != NULL);
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if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
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tx_bug = 1;
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pci_unmap_page(tp->pdev,
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pci_unmap_addr(ri, mapping),
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@ -3006,6 +3032,11 @@ static void tg3_tx(struct tg3 *tp)
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}
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dev_kfree_skb(skb);
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if (unlikely(tx_bug)) {
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tg3_tx_recover(tp);
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return;
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}
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}
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tp->tx_cons = sw_idx;
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@ -3333,6 +3364,11 @@ static int tg3_poll(struct net_device *netdev, int *budget)
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/* run TX completion thread */
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if (sblk->idx[0].tx_consumer != tp->tx_cons) {
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tg3_tx(tp);
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if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
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netif_rx_complete(netdev);
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schedule_work(&tp->reset_task);
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return 0;
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}
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}
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/* run RX thread, within the bounds set by NAPI.
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@ -3581,6 +3617,13 @@ static void tg3_reset_task(void *_data)
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restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
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tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
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if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
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tp->write32_tx_mbox = tg3_write32_tx_mbox;
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tp->write32_rx_mbox = tg3_write_flush_reg32;
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tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
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tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
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}
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tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
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tg3_init_hw(tp, 1);
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@ -2155,11 +2155,7 @@ struct tg3 {
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#define TG3_FLAG_ENABLE_ASF 0x00000020
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#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
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#define TG3_FLAG_POLL_SERDES 0x00000080
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#if defined(CONFIG_X86)
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#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
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#else
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#define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
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#endif
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#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
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#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
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#define TG3_FLAG_WOL_ENABLE 0x00000800
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@ -2172,6 +2168,7 @@ struct tg3 {
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#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
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#define TG3_FLAG_PCI_32BIT 0x00080000
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#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
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#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
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#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
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#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
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#define TG3_FLAG_10_100_ONLY 0x01000000
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