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MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Add: MADDF.fmt To perform a fused multiply-add of FP values. MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft]) Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras
Ralf Baechle
parent
130fe357ee
commit
e24c3bec3e
@ -4,9 +4,9 @@
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obj-y += cp1emu.o ieee754dp.o ieee754sp.o ieee754.o \
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dp_div.o dp_mul.o dp_sub.o dp_add.o dp_fsp.o dp_cmp.o dp_simple.o \
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dp_tint.o dp_fint.o \
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dp_tint.o dp_fint.o dp_maddf.o \
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sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_simple.o \
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sp_tint.o sp_fint.o \
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sp_tint.o sp_fint.o sp_maddf.o \
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dsemul.o
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lib-y += ieee754d.o \
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@ -1765,6 +1765,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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rv.w = 0;
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break;
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case fmaddf_op: {
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union ieee754sp ft, fs, fd;
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if (!cpu_has_mips_r6)
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return SIGILL;
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SPFROMREG(ft, MIPSInst_FT(ir));
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SPFROMREG(fs, MIPSInst_FS(ir));
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SPFROMREG(fd, MIPSInst_FD(ir));
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rv.s = ieee754sp_maddf(fd, fs, ft);
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break;
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}
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case fabs_op:
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handler.u = ieee754sp_abs;
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goto scopuop;
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@ -1985,6 +1998,19 @@ copcsr:
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rv.l = 0;
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break;
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case fmaddf_op: {
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union ieee754dp ft, fs, fd;
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if (!cpu_has_mips_r6)
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return SIGILL;
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DPFROMREG(ft, MIPSInst_FT(ir));
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DPFROMREG(fs, MIPSInst_FS(ir));
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DPFROMREG(fd, MIPSInst_FD(ir));
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rv.d = ieee754dp_maddf(fd, fs, ft);
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break;
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}
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case fabs_op:
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handler.u = ieee754dp_abs;
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goto dcopuop;
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265
arch/mips/math-emu/dp_maddf.c
Normal file
265
arch/mips/math-emu/dp_maddf.c
Normal file
@ -0,0 +1,265 @@
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/*
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* IEEE754 floating point arithmetic
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* double precision: MADDF.f (Fused Multiply Add)
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
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*
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* MIPS floating point support
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* Copyright (C) 2015 Imagination Technologies, Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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#include "ieee754dp.h"
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union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y)
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{
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int re;
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int rs;
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u64 rm;
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unsigned lxm;
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unsigned hxm;
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unsigned lym;
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unsigned hym;
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u64 lrm;
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u64 hrm;
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u64 t;
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u64 at;
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int s;
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COMPXDP;
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COMPYDP;
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u64 zm; int ze; int zs __maybe_unused; int zc;
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EXPLODEXDP;
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EXPLODEYDP;
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EXPLODEDP(z, zc, zs, ze, zm)
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FLUSHXDP;
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FLUSHYDP;
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FLUSHDP(z, zc, zs, ze, zm);
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ieee754_clearcx();
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switch (zc) {
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case IEEE754_CLASS_SNAN:
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_nanxcpt(z);
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case IEEE754_CLASS_DNORM:
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DPDNORMx(zm, ze);
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/* QNAN is handled separately below */
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}
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switch (CLPAIR(xc, yc)) {
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
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return ieee754dp_nanxcpt(y);
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
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return ieee754dp_nanxcpt(x);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
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return y;
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
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return x;
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/*
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* Infinity handling
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*/
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_indef();
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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return ieee754dp_inf(xs ^ ys);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
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if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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/* Multiplication is 0 so just return z */
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return z;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
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DPDNORMX;
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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DPDNORMY;
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break;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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DPDNORMX;
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break;
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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/* fall through to real computations */
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}
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/* Finally get to do some computation */
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/*
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* Do the multiplication bit first
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*
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* rm = xm * ym, re = xe + ye basically
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*
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* At this point xm and ym should have been normalized.
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*/
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assert(xm & DP_HIDDEN_BIT);
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assert(ym & DP_HIDDEN_BIT);
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re = xe + ye;
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rs = xs ^ ys;
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/* shunt to top of word */
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xm <<= 64 - (DP_FBITS + 1);
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ym <<= 64 - (DP_FBITS + 1);
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/*
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* Multiply 32 bits xm, ym to give high 32 bits rm with stickness.
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*/
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/* 32 * 32 => 64 */
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#define DPXMULT(x, y) ((u64)(x) * (u64)y)
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lxm = xm;
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hxm = xm >> 32;
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lym = ym;
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hym = ym >> 32;
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lrm = DPXMULT(lxm, lym);
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hrm = DPXMULT(hxm, hym);
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t = DPXMULT(lxm, hym);
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at = lrm + (t << 32);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 32);
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t = DPXMULT(hxm, lym);
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at = lrm + (t << 32);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 32);
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rm = hrm | (lrm != 0);
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/*
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* Sticky shift down to normal rounding precision.
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*/
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if ((s64) rm < 0) {
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rm = (rm >> (64 - (DP_FBITS + 1 + 3))) |
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((rm << (DP_FBITS + 1 + 3)) != 0);
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re++;
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} else {
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rm = (rm >> (64 - (DP_FBITS + 1 + 3 + 1))) |
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((rm << (DP_FBITS + 1 + 3 + 1)) != 0);
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}
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assert(rm & (DP_HIDDEN_BIT << 3));
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/* And now the addition */
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assert(zm & DP_HIDDEN_BIT);
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/*
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* Provide guard,round and stick bit space.
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*/
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zm <<= 3;
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if (ze > re) {
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/*
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* Have to shift y fraction right to align.
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*/
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s = ze - re;
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rm = XDPSRS(rm, s);
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re += s;
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} else if (re > ze) {
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/*
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* Have to shift x fraction right to align.
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*/
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s = re - ze;
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zm = XDPSRS(zm, s);
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ze += s;
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}
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assert(ze == re);
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assert(ze <= DP_EMAX);
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if (zs == rs) {
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/*
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* Generate 28 bit result of adding two 27 bit numbers
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* leaving result in xm, xs and xe.
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*/
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zm = zm + rm;
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if (zm >> (DP_FBITS + 1 + 3)) { /* carry out */
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zm = XDPSRS1(zm);
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ze++;
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}
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} else {
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if (zm >= rm) {
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zm = zm - rm;
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} else {
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zm = rm - zm;
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zs = rs;
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}
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if (zm == 0)
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return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
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/*
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* Normalize to rounding precision.
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*/
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while ((zm >> (DP_FBITS + 3)) == 0) {
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zm <<= 1;
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ze--;
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}
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}
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return ieee754dp_format(zs, ze, zm);
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}
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@ -75,6 +75,9 @@ int ieee754sp_cmp(union ieee754sp x, union ieee754sp y, int cop, int sig);
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union ieee754sp ieee754sp_sqrt(union ieee754sp x);
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union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x,
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union ieee754sp y);
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/*
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* double precision (often aka double)
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*/
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@ -99,6 +102,8 @@ int ieee754dp_cmp(union ieee754dp x, union ieee754dp y, int cop, int sig);
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union ieee754dp ieee754dp_sqrt(union ieee754dp x);
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union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y);
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/* 5 types of floating point number
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255
arch/mips/math-emu/sp_maddf.c
Normal file
255
arch/mips/math-emu/sp_maddf.c
Normal file
@ -0,0 +1,255 @@
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/*
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* IEEE754 floating point arithmetic
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* single precision: MADDF.f (Fused Multiply Add)
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
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*
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* MIPS floating point support
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* Copyright (C) 2015 Imagination Technologies, Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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#include "ieee754sp.h"
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union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x,
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union ieee754sp y)
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{
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int re;
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int rs;
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unsigned rm;
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unsigned short lxm;
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unsigned short hxm;
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unsigned short lym;
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unsigned short hym;
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unsigned lrm;
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unsigned hrm;
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unsigned t;
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unsigned at;
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int s;
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COMPXSP;
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COMPYSP;
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u32 zm; int ze; int zs __maybe_unused; int zc;
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EXPLODEXSP;
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EXPLODEYSP;
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EXPLODESP(z, zc, zs, ze, zm)
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FLUSHXSP;
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FLUSHYSP;
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FLUSHSP(z, zc, zs, ze, zm);
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ieee754_clearcx();
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switch (zc) {
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case IEEE754_CLASS_SNAN:
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754sp_nanxcpt(z);
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case IEEE754_CLASS_DNORM:
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SPDNORMx(zm, ze);
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/* QNAN is handled separately below */
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}
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switch (CLPAIR(xc, yc)) {
|
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
|
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
|
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
|
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
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return ieee754sp_nanxcpt(y);
|
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|
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
|
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
|
||||
case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
|
||||
case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
|
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
|
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
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return ieee754sp_nanxcpt(x);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
|
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
|
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
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return y;
|
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|
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
|
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
|
||||
case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
|
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
|
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
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return x;
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|
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/*
|
||||
* Infinity handling
|
||||
*/
|
||||
case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
|
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
|
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if (zc == IEEE754_CLASS_QNAN)
|
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return z;
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ieee754_setcx(IEEE754_INVALID_OPERATION);
|
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return ieee754sp_indef();
|
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|
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
|
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
|
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
|
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
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if (zc == IEEE754_CLASS_QNAN)
|
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return z;
|
||||
return ieee754sp_inf(xs ^ ys);
|
||||
|
||||
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
|
||||
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
|
||||
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
|
||||
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
|
||||
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
|
||||
if (zc == IEEE754_CLASS_INF)
|
||||
return ieee754sp_inf(zs);
|
||||
/* Multiplication is 0 so just return z */
|
||||
return z;
|
||||
|
||||
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
|
||||
SPDNORMX;
|
||||
|
||||
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
|
||||
if (zc == IEEE754_CLASS_QNAN)
|
||||
return z;
|
||||
else if (zc == IEEE754_CLASS_INF)
|
||||
return ieee754sp_inf(zs);
|
||||
SPDNORMY;
|
||||
break;
|
||||
|
||||
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
|
||||
if (zc == IEEE754_CLASS_QNAN)
|
||||
return z;
|
||||
else if (zc == IEEE754_CLASS_INF)
|
||||
return ieee754sp_inf(zs);
|
||||
SPDNORMX;
|
||||
break;
|
||||
|
||||
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
|
||||
if (zc == IEEE754_CLASS_QNAN)
|
||||
return z;
|
||||
else if (zc == IEEE754_CLASS_INF)
|
||||
return ieee754sp_inf(zs);
|
||||
/* fall through to real computations */
|
||||
}
|
||||
|
||||
/* Finally get to do some computation */
|
||||
|
||||
/*
|
||||
* Do the multiplication bit first
|
||||
*
|
||||
* rm = xm * ym, re = xe + ye basically
|
||||
*
|
||||
* At this point xm and ym should have been normalized.
|
||||
*/
|
||||
|
||||
/* rm = xm * ym, re = xe+ye basically */
|
||||
assert(xm & SP_HIDDEN_BIT);
|
||||
assert(ym & SP_HIDDEN_BIT);
|
||||
|
||||
re = xe + ye;
|
||||
rs = xs ^ ys;
|
||||
|
||||
/* shunt to top of word */
|
||||
xm <<= 32 - (SP_FBITS + 1);
|
||||
ym <<= 32 - (SP_FBITS + 1);
|
||||
|
||||
/*
|
||||
* Multiply 32 bits xm, ym to give high 32 bits rm with stickness.
|
||||
*/
|
||||
lxm = xm & 0xffff;
|
||||
hxm = xm >> 16;
|
||||
lym = ym & 0xffff;
|
||||
hym = ym >> 16;
|
||||
|
||||
lrm = lxm * lym; /* 16 * 16 => 32 */
|
||||
hrm = hxm * hym; /* 16 * 16 => 32 */
|
||||
|
||||
t = lxm * hym; /* 16 * 16 => 32 */
|
||||
at = lrm + (t << 16);
|
||||
hrm += at < lrm;
|
||||
lrm = at;
|
||||
hrm = hrm + (t >> 16);
|
||||
|
||||
t = hxm * lym; /* 16 * 16 => 32 */
|
||||
at = lrm + (t << 16);
|
||||
hrm += at < lrm;
|
||||
lrm = at;
|
||||
hrm = hrm + (t >> 16);
|
||||
|
||||
rm = hrm | (lrm != 0);
|
||||
|
||||
/*
|
||||
* Sticky shift down to normal rounding precision.
|
||||
*/
|
||||
if ((int) rm < 0) {
|
||||
rm = (rm >> (32 - (SP_FBITS + 1 + 3))) |
|
||||
((rm << (SP_FBITS + 1 + 3)) != 0);
|
||||
re++;
|
||||
} else {
|
||||
rm = (rm >> (32 - (SP_FBITS + 1 + 3 + 1))) |
|
||||
((rm << (SP_FBITS + 1 + 3 + 1)) != 0);
|
||||
}
|
||||
assert(rm & (SP_HIDDEN_BIT << 3));
|
||||
|
||||
/* And now the addition */
|
||||
|
||||
assert(zm & SP_HIDDEN_BIT);
|
||||
|
||||
/*
|
||||
* Provide guard,round and stick bit space.
|
||||
*/
|
||||
zm <<= 3;
|
||||
|
||||
if (ze > re) {
|
||||
/*
|
||||
* Have to shift y fraction right to align.
|
||||
*/
|
||||
s = ze - re;
|
||||
SPXSRSYn(s);
|
||||
} else if (re > ze) {
|
||||
/*
|
||||
* Have to shift x fraction right to align.
|
||||
*/
|
||||
s = re - ze;
|
||||
SPXSRSYn(s);
|
||||
}
|
||||
assert(ze == re);
|
||||
assert(ze <= SP_EMAX);
|
||||
|
||||
if (zs == rs) {
|
||||
/*
|
||||
* Generate 28 bit result of adding two 27 bit numbers
|
||||
* leaving result in zm, zs and ze.
|
||||
*/
|
||||
zm = zm + rm;
|
||||
|
||||
if (zm >> (SP_FBITS + 1 + 3)) { /* carry out */
|
||||
SPXSRSX1();
|
||||
}
|
||||
} else {
|
||||
if (zm >= rm) {
|
||||
zm = zm - rm;
|
||||
} else {
|
||||
zm = rm - zm;
|
||||
zs = rs;
|
||||
}
|
||||
if (zm == 0)
|
||||
return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
|
||||
|
||||
/*
|
||||
* Normalize in extended single precision
|
||||
*/
|
||||
while ((zm >> (SP_MBITS + 3)) == 0) {
|
||||
zm <<= 1;
|
||||
ze--;
|
||||
}
|
||||
|
||||
}
|
||||
return ieee754sp_format(zs, ze, zm);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user