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drm/i915: enable DP/eDP for Sandybridge/Cougarpoint
DP on Cougarpoint has new training pattern definitions, and new transcoder DP control register is used to determine the mapping for transcoder and DP digital output. And eDP for Sandybridge has new voltage and pre-emphasis level definitions. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Zhenyu Wang
Eric Anholt
parent
0f229062a1
commit
e3421a1894
@ -1001,6 +1001,7 @@ extern void i8xx_disable_fbc(struct drm_device *dev);
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extern void g4x_disable_fbc(struct drm_device *dev);
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extern void intel_detect_pch (struct drm_device *dev);
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extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
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/**
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* Lock test for when it's just for synchronization of ring access.
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@ -1893,6 +1893,39 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* wait one idle pattern time */
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udelay(100);
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
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int reg;
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reg = I915_READ(trans_dp_ctl);
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reg &= ~TRANS_DP_PORT_SEL_MASK;
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reg = TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_ENH_FRAMING |
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TRANS_DP_VSYNC_ACTIVE_HIGH |
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TRANS_DP_HSYNC_ACTIVE_HIGH;
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switch (intel_trans_dp_port_sel(crtc)) {
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case PCH_DP_B:
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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case PCH_DP_C:
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reg |= TRANS_DP_PORT_SEL_C;
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break;
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case PCH_DP_D:
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reg |= TRANS_DP_PORT_SEL_D;
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break;
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default:
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DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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}
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I915_WRITE(trans_dp_ctl, reg);
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POSTING_READ(trans_dp_ctl);
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}
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/* enable PCH transcoder */
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temp = I915_READ(transconf_reg);
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/*
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@ -2030,6 +2063,14 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(100);
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if (HAS_PCH_CPT(dev)) {
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/* disable TRANS_DP_CTL */
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int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
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int reg;
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reg = I915_READ(trans_dp_ctl);
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reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
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I915_WRITE(trans_dp_ctl, reg);
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POSTING_READ(trans_dp_ctl);
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/* disable DPLL_SEL */
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temp = I915_READ(PCH_DPLL_SEL);
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@ -221,19 +221,27 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
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uint32_t ctl;
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uint32_t status;
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uint32_t aux_clock_divider;
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int try;
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int try, precharge;
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/* The clock divider is based off the hrawclk,
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* and would like to run at 2MHz. So, take the
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* hrawclk value and divide by 2 and use that
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*/
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if (IS_eDP(intel_encoder))
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aux_clock_divider = 225; /* eDP input clock at 450Mhz */
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else if (HAS_PCH_SPLIT(dev))
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if (IS_eDP(intel_encoder)) {
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if (IS_GEN6(dev))
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aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
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else
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aux_clock_divider = 225; /* eDP input clock at 450Mhz */
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} else if (HAS_PCH_SPLIT(dev))
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aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
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else
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aux_clock_divider = intel_hrawclk(dev) / 2;
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if (IS_GEN6(dev))
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precharge = 3;
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else
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precharge = 5;
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/* Must try at least 3 times according to DP spec */
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for (try = 0; try < 5; try++) {
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/* Load the send data into the aux channel data registers */
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@ -246,7 +254,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
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ctl = (DP_AUX_CH_CTL_SEND_BUSY |
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DP_AUX_CH_CTL_TIME_OUT_400us |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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@ -623,17 +631,22 @@ static void
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intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
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struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
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struct drm_crtc *crtc = intel_encoder->enc.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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dp_priv->DP = (DP_LINK_TRAIN_OFF |
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DP_VOLTAGE_0_4 |
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dp_priv->DP = (DP_VOLTAGE_0_4 |
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DP_PRE_EMPHASIS_0 |
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DP_SYNC_VS_HIGH |
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DP_SYNC_HS_HIGH);
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
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dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
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else
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dp_priv->DP |= DP_LINK_TRAIN_OFF;
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switch (dp_priv->lane_count) {
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case 1:
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dp_priv->DP |= DP_PORT_WIDTH_1;
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@ -661,7 +674,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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dp_priv->DP |= DP_ENHANCED_FRAMING;
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}
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if (intel_crtc->pipe == 1)
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/* CPT DP's pipe select is decided in TRANS_DP_CTL */
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if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
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dp_priv->DP |= DP_PIPEB_SELECT;
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if (IS_eDP(intel_encoder)) {
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@ -875,6 +889,25 @@ intel_dp_signal_levels(uint8_t train_set, int lane_count)
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return signal_levels;
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}
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/* Gen6's DP voltage swing and pre-emphasis control */
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static uint32_t
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intel_gen6_edp_signal_levels(uint8_t train_set)
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{
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switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
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case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
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return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
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case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
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return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
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case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
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return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
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case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
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return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
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default:
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DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
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return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
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}
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}
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static uint8_t
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intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
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int lane)
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@ -968,23 +1001,38 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
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bool channel_eq = false;
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bool first = true;
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int tries;
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u32 reg;
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_encoder, 0x100,
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link_configuration, DP_LINK_CONFIGURATION_SIZE);
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DP |= DP_PORT_EN;
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DP &= ~DP_LINK_TRAIN_MASK;
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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else
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DP &= ~DP_LINK_TRAIN_MASK;
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memset(train_set, 0, 4);
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voltage = 0xff;
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tries = 0;
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clock_recovery = false;
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for (;;) {
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/* Use train_set[0] to set the voltage and pre emphasis values */
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uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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uint32_t signal_levels;
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if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
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signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1,
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
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reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_1;
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if (!intel_dp_set_link_train(intel_encoder, reg,
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DP_TRAINING_PATTERN_1, train_set, first))
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break;
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first = false;
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@ -1024,11 +1072,23 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
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channel_eq = false;
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for (;;) {
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/* Use train_set[0] to set the voltage and pre emphasis values */
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uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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uint32_t signal_levels;
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if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
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signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
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reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_2;
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/* channel eq pattern */
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if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2,
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if (!intel_dp_set_link_train(intel_encoder, reg,
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DP_TRAINING_PATTERN_2, train_set,
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false))
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break;
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@ -1051,7 +1111,12 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
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++tries;
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}
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I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
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reg = DP | DP_LINK_TRAIN_OFF_CPT;
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else
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reg = DP | DP_LINK_TRAIN_OFF;
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I915_WRITE(dp_priv->output_reg, reg);
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POSTING_READ(dp_priv->output_reg);
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intel_dp_aux_native_write_1(intel_encoder,
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DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
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@ -1073,9 +1138,15 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
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udelay(100);
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}
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DP &= ~DP_LINK_TRAIN_MASK;
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I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
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POSTING_READ(dp_priv->output_reg);
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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POSTING_READ(dp_priv->output_reg);
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} else {
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DP &= ~DP_LINK_TRAIN_MASK;
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I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
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POSTING_READ(dp_priv->output_reg);
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}
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udelay(17000);
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@ -1268,6 +1339,28 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
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intel_dp_check_link_status(intel_encoder);
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}
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/* Return which DP Port should be selected for Transcoder DP control */
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int
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intel_trans_dp_port_sel (struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_encoder *encoder;
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struct intel_encoder *intel_encoder = NULL;
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list_for_each_entry(encoder, &mode_config->encoder_list, head) {
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if (!encoder || encoder->crtc != crtc)
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continue;
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intel_encoder = enc_to_intel_encoder(encoder);
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if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
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struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
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return dp_priv->output_reg;
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}
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}
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return -1;
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}
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void
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intel_dp_init(struct drm_device *dev, int output_reg)
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{
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