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https://github.com/FEX-Emu/linux.git
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iwlwifi: move register access lock into transport
Move the reg_lock that protects HW register access into the transport implementation. Locking is no longer exposed, but handled internally in grab and release NIC access. This simplifies the users. Signed-off-by: Lilach Edelstein <lilach.edelstein@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
parent
e139dc4aeb
commit
e56b04efc1
@ -459,14 +459,12 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
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base = priv->device_pointers.error_event_table;
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if (iwlagn_hw_valid_rtc_data_addr(base)) {
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spin_lock_irqsave(&priv->trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(priv->trans, true)) {
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if (iwl_trans_grab_nic_access(priv->trans, true, &flags)) {
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iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, base);
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status = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
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iwl_trans_release_nic_access(priv->trans);
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iwl_trans_release_nic_access(priv->trans, &flags);
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ret = 0;
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}
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spin_unlock_irqrestore(&priv->trans->reg_lock, flags);
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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if (ret == 0) {
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@ -353,11 +353,8 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&priv->trans->reg_lock, reg_flags);
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if (!iwl_trans_grab_nic_access(priv->trans, false)) {
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spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
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if (!iwl_trans_grab_nic_access(priv->trans, false, ®_flags))
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return;
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}
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/* Set starting address; reads will auto-increment */
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iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr);
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@ -388,8 +385,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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}
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}
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/* Allow device to power down */
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iwl_trans_release_nic_access(priv->trans);
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spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
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iwl_trans_release_nic_access(priv->trans, ®_flags);
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}
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static void iwl_continuous_event_trace(struct iwl_priv *priv)
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@ -1717,9 +1713,8 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&trans->reg_lock, reg_flags);
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if (!iwl_trans_grab_nic_access(trans, false))
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goto out_unlock;
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if (!iwl_trans_grab_nic_access(trans, false, ®_flags))
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return pos;
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/* Set starting address; reads will auto-increment */
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
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@ -1757,9 +1752,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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}
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/* Allow device to power down */
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iwl_trans_release_nic_access(trans);
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out_unlock:
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spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
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iwl_trans_release_nic_access(trans, ®_flags);
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return pos;
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}
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@ -185,10 +185,8 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
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priv->thermal_throttle.ct_kill_toggle = true;
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}
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iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
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spin_lock_irqsave(&priv->trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(priv->trans, false))
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iwl_trans_release_nic_access(priv->trans);
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spin_unlock_irqrestore(&priv->trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(priv->trans, false, &flags))
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iwl_trans_release_nic_access(priv->trans, &flags);
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/* Reschedule the ct_kill timer to occur in
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* CT_KILL_EXIT_DURATION seconds to ensure we get a
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@ -55,13 +55,10 @@ u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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u32 value = 0x5a5a5a5a;
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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value = iwl_read32(trans, reg);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return value;
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}
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@ -71,12 +68,10 @@ void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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iwl_write32(trans, reg, value);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_write_direct32);
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@ -114,12 +109,10 @@ u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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unsigned long flags;
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u32 val = 0x5a5a5a5a;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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val = __iwl_read_prph(trans, ofs);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return val;
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}
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EXPORT_SYMBOL_GPL(iwl_read_prph);
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@ -128,12 +121,10 @@ void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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__iwl_write_prph(trans, ofs, val);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_write_prph);
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@ -141,13 +132,11 @@ void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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__iwl_write_prph(trans, ofs,
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__iwl_read_prph(trans, ofs) | mask);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_set_bits_prph);
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@ -156,13 +145,11 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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__iwl_write_prph(trans, ofs,
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(__iwl_read_prph(trans, ofs) & mask) | bits);
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_set_bits_mask_prph);
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@ -171,12 +158,10 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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val = __iwl_read_prph(trans, ofs);
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__iwl_write_prph(trans, ofs, (val & ~mask));
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iwl_trans_release_nic_access(trans);
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iwl_trans_release_nic_access(trans, &flags);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_clear_bits_prph);
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@ -466,9 +466,7 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
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/* Hard-coded periphery absolute address */
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if (IWL_ABS_PRPH_START <= addr &&
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addr < IWL_ABS_PRPH_START + PRPH_END) {
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_trans_grab_nic_access(trans, false)) {
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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if (!iwl_trans_grab_nic_access(trans, false, &flags)) {
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return -EIO;
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}
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iwl_write32(trans, HBUS_TARG_PRPH_RADDR,
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@ -476,8 +474,7 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
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for (i = 0; i < size; i += 4)
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*(u32 *)(tst->mem.addr + i) =
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iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
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iwl_trans_release_nic_access(trans);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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iwl_trans_release_nic_access(trans, &flags);
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} else { /* target memory (SRAM) */
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iwl_trans_read_mem(trans, addr, tst->mem.addr,
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tst->mem.size / 4);
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@ -506,19 +503,13 @@ static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr,
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/* Periphery writes can be 1-3 bytes long, or DWORDs */
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if (size < 4) {
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memcpy(&val, buf, size);
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_trans_grab_nic_access(trans, false)) {
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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if (!iwl_trans_grab_nic_access(trans, false, &flags))
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return -EIO;
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}
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iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
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(addr & 0x0000FFFF) |
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((size - 1) << 24));
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iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
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iwl_trans_release_nic_access(trans);
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/* needed after consecutive writes w/o read */
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mmiowb();
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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iwl_trans_release_nic_access(trans, &flags);
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} else {
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if (size % 4)
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return -EINVAL;
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@ -416,8 +416,11 @@ struct iwl_trans;
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* the op_mode. May be called several times before start_fw, can't be
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* called after that.
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* @set_pmi: set the power pmi state
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* @grab_nic_access: wake the NIC to be able to access non-HBUS regs
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* @release_nic_access: let the NIC go to sleep
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* @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
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* Sleeping is not allowed between grab_nic_access and
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* release_nic_access.
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* @release_nic_access: let the NIC go to sleep. The "flags" parameter
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* must be the same one that was sent before to the grab_nic_access.
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* @set_bits_mask - set SRAM register according to value and mask.
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*/
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struct iwl_trans_ops {
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@ -461,8 +464,10 @@ struct iwl_trans_ops {
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void (*configure)(struct iwl_trans *trans,
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const struct iwl_trans_config *trans_cfg);
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void (*set_pmi)(struct iwl_trans *trans, bool state);
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bool (*grab_nic_access)(struct iwl_trans *trans, bool silent);
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void (*release_nic_access)(struct iwl_trans *trans);
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bool (*grab_nic_access)(struct iwl_trans *trans, bool silent,
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unsigned long *flags);
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void (*release_nic_access)(struct iwl_trans *trans,
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unsigned long *flags);
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void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
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u32 value);
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};
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@ -484,7 +489,6 @@ enum iwl_trans_state {
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* @ops - pointer to iwl_trans_ops
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* @op_mode - pointer to the op_mode
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* @cfg - pointer to the configuration
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* @reg_lock - protect hw register access
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* @dev - pointer to struct device * that represents the device
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* @hw_id: a u32 with the ID of the device / subdevice.
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* Set during transport allocation.
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@ -505,7 +509,6 @@ struct iwl_trans {
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struct iwl_op_mode *op_mode;
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const struct iwl_cfg *cfg;
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enum iwl_trans_state state;
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spinlock_t reg_lock;
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struct device *dev;
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u32 hw_rev;
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@ -771,14 +774,14 @@ iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
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trans->ops->set_bits_mask(trans, reg, mask, value);
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}
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#define iwl_trans_grab_nic_access(trans, silent) \
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#define iwl_trans_grab_nic_access(trans, silent, flags) \
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__cond_lock(nic_access, \
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likely((trans)->ops->grab_nic_access(trans, silent)))
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likely((trans)->ops->grab_nic_access(trans, silent, flags)))
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static inline void __releases(nic_access)
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iwl_trans_release_nic_access(struct iwl_trans *trans)
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iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
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{
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trans->ops->release_nic_access(trans);
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trans->ops->release_nic_access(trans, flags);
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__release(nic_access);
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}
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@ -235,6 +235,7 @@ struct iwl_txq {
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* @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
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* @rx_page_order: page order for receive buffer size
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* @wd_timeout: queue watchdog timeout (jiffies)
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* @reg_lock: protect hw register access
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*/
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struct iwl_trans_pcie {
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struct iwl_rxq rxq;
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@ -283,6 +284,9 @@ struct iwl_trans_pcie {
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/* queue watchdog */
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unsigned long wd_timeout;
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/*protect hw register */
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spinlock_t reg_lock;
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};
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/**
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@ -806,11 +806,12 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans)
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}
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#endif /* CONFIG_PM_SLEEP */
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static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
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static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
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unsigned long *flags)
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{
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int ret;
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lockdep_assert_held(&trans->reg_lock);
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struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans);
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spin_lock_irqsave(&pcie_trans->reg_lock, *flags);
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/* this bit wakes up the NIC */
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__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
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@ -846,16 +847,32 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
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WARN_ONCE(1,
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"Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
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val);
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spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags);
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return false;
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}
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}
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/*
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* Fool sparse by faking we release the lock - sparse will
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* track nic_access anyway.
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*/
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__release(&pcie_trans->reg_lock);
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return true;
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}
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static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
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static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
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unsigned long *flags)
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{
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lockdep_assert_held(&trans->reg_lock);
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struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans);
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lockdep_assert_held(&pcie_trans->reg_lock);
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/*
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* Fool sparse by faking we acquiring the lock - sparse will
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* track nic_access anyway.
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*/
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__acquire(&pcie_trans->reg_lock);
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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/*
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@ -865,6 +882,7 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
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* scheduled on different CPUs (after we drop reg_lock).
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*/
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mmiowb();
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spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags);
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}
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static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
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@ -874,16 +892,14 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
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int offs, ret = 0;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (iwl_trans_grab_nic_access(trans, false)) {
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if (iwl_trans_grab_nic_access(trans, false, &flags)) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_trans_release_nic_access(trans);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
} else {
|
||||
ret = -EBUSY;
|
||||
}
|
||||
spin_unlock_irqrestore(&trans->reg_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -894,17 +910,15 @@ static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
|
||||
int offs, ret = 0;
|
||||
u32 *vals = buf;
|
||||
|
||||
spin_lock_irqsave(&trans->reg_lock, flags);
|
||||
if (iwl_trans_grab_nic_access(trans, false)) {
|
||||
if (iwl_trans_grab_nic_access(trans, false, &flags)) {
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
|
||||
for (offs = 0; offs < dwords; offs++)
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WDAT,
|
||||
vals ? vals[offs] : 0);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
} else {
|
||||
ret = -EBUSY;
|
||||
}
|
||||
spin_unlock_irqrestore(&trans->reg_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -982,11 +996,12 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
|
||||
static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
|
||||
u32 mask, u32 value)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&trans->reg_lock, flags);
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
|
||||
spin_unlock_irqrestore(&trans->reg_lock, flags);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
}
|
||||
|
||||
static const char *get_fh_string(int cmd)
|
||||
@ -1467,6 +1482,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
|
||||
trans->cfg = cfg;
|
||||
trans_pcie->trans = trans;
|
||||
spin_lock_init(&trans_pcie->irq_lock);
|
||||
spin_lock_init(&trans_pcie->reg_lock);
|
||||
init_waitqueue_head(&trans_pcie->ucode_write_waitq);
|
||||
|
||||
/* W/A - seems to solve weird behavior. We need to remove this if we
|
||||
@ -1533,7 +1549,6 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
|
||||
|
||||
/* Initialize the wait queue for commands */
|
||||
init_waitqueue_head(&trans_pcie->wait_command_queue);
|
||||
spin_lock_init(&trans->reg_lock);
|
||||
|
||||
snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
|
||||
"iwl_cmd_pool:%s", dev_name(trans->dev));
|
||||
|
Loading…
x
Reference in New Issue
Block a user