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PCI: xilinx: Update Zynq binding with Microblaze node
Update Zynq PCI binding documentation with Microblaze node. [bhelgaas: fix "microbalze_0_intc" typo] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
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@ -17,7 +17,7 @@ Required properties:
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Please refer to the standard PCI bus binding document for a more
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detailed explanation
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Optional properties:
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Optional properties for Zynq/Microblaze:
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- bus-range: PCI bus numbers covered
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Interrupt controller child node
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@ -38,13 +38,13 @@ the four INTx interrupts in ISR and route them to this domain.
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Example:
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++++++++
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Zynq:
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pci_express: axi-pcie@50000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = < 0x50000000 0x10000000 >;
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reg = < 0x50000000 0x1000000 >;
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device_type = "pci";
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interrupts = < 0 52 4 >;
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interrupt-map-mask = <0 0 0 7>;
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@ -60,3 +60,29 @@ Example:
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#interrupt-cells = <1>;
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};
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};
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Microblaze:
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pci_express: axi-pcie@10000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = <0x10000000 0x4000000>;
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device_type = "pci";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = <1 2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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