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drm/vc4: Fix DSI T_INIT timing.

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The DPHY spec requires a much larger T_INIT than I was specifying
before.  In the absence of clear specs from the slave of what their
timing is, just use the value that the firmware was using.

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: http://patchwork.freedesktop.org/patch/msgid/20170627195839.3338-2-eric@anholt.net
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
This commit is contained in:
Eric Anholt 2017-06-27 12:58:32 -07:00
parent 2570fe2586
commit e65d51126f
1 changed files with 11 additions and 1 deletions
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12
drivers/gpu/drm/vc4/vc4_dsi.c
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@ -1035,7 +1035,17 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
DSI_HS_DLT4_TRAIL) |
VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000),
/* T_INIT is how long STOP is driven after power-up to
* indicate to the slave (also coming out of power-up) that
* master init is complete, and should be greater than the
* maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
* D-PHY spec gives a minimum 100us for T_INIT,MASTER and
* T_INIT,SLAVE, while allowing protocols on top of it to give
* greater minimums. The vc4 firmware uses an extremely
* conservative 5ms, and we maintain that here.
*/
DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
5 * 1000 * 1000, 0),
DSI_HS_DLT5_INIT));
DSI_PORT_WRITE(HS_DLT6,