From 14cfa4bd74be31e5502dcb5c98de86db63fddb65 Mon Sep 17 00:00:00 2001 From: Willy Tarreau Date: Sun, 12 Jan 2014 13:09:24 +0100 Subject: [PATCH 01/20] ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260 It was correctly set on mv78460 but not on mv78260, resulting in my OpenBlocks AX3-4 retrieving only 3 of its 4 MAC addresses from the boot loader. Cc: Thomas Petazzoni Cc: Gregory CLEMENT Signed-off-by: Willy Tarreau Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 66609684d41b..9480cf891f8c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -23,6 +23,7 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + eth3 = ð3; }; cpus { @@ -291,7 +292,7 @@ interrupts = <91>; }; - ethernet@34000 { + eth3: ethernet@34000 { compatible = "marvell,armada-370-neta"; reg = <0x34000 0x4000>; interrupts = <14>; From 4de59085091f753d08c8429d756b46756ab94665 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 17 Feb 2014 15:23:25 +0100 Subject: [PATCH 02/20] ARM: mvebu: add Device Tree description of the Armada 375 SoC The Armada 375 SoC is a new SoC from Marvell, based on a dual core Cortex-A9 and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPUs * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * SDIO * Pinctrl * SATA * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 458 ++++++++++++++++++++++++++++++ 1 file changed, 458 insertions(+) create mode 100644 arch/arm/boot/dts/armada-375.dtsi diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi new file mode 100644 index 000000000000..9f5cb5163a7e --- /dev/null +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -0,0 +1,458 @@ +/* + * Device Tree Include file for Marvell Armada 375 family SoC + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 375 family SoC"; + compatible = "marvell,armada375"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = <1 13 0x301>; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <0 1 0x4>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <0 63 0x4>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 2 0x4>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 3 0x4>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <0 12 4>; + reg-io-width = <1>; + status = "disabled"; + }; + + serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <0 13 4>; + reg-io-width = <1>; + status = "disabled"; + }; + + pinctrl { + compatible = "marvell,mv88f6720-pinctrl"; + reg = <0x18000 0x24>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp61", "mpp62"; + marvell,function = "i2c1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13"; + marvell,function = "nand"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29"; + marvell,function = "sd"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp0", "mpp1", "mpp4", + "mpp5", "mpp8", "mpp9"; + marvell,function = "spi0"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 53 0x4>, <0 54 0x4>, + <0 55 0x4>, <0 56 0x4>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 58 0x4>, <0 59 0x4>, + <0 60 0x4>, <0 61 0x4>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 62 0x4>; + }; + + system-controller@18200 { + compatible = "marvell,armada-375-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-375-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = <1 15 0x4>; + }; + + timer@20300 { + compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic 0 8 4>, + <&gic 0 9 4>, + <&gic 0 10 4>, + <&gic 0 11 4>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 0>; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = <0 22 0x4>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <0 23 0x4>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 23>; + status = "okay"; + + xor10 { + interrupts = <0 65 0x4>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <0 66 0x4>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x5000>; + interrupts = <0 26 0x4>; + clocks = <&gateclk 14>, <&gateclk 20>; + clock-names = "0", "1"; + status = "disabled"; + }; + + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 84 0x4>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = <0 25 0x4>; + clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + + coreclk: mvebu-sar@e8204 { + compatible = "marvell,armada-375-core-clock"; + reg = <0xe8204 0x04>; + #clock-cells = <1>; + }; + + coredivclk: corediv-clock@e8250 { + compatible = "marvell,armada-375-corediv-clock"; + reg = <0xe8250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + }; + }; +}; From 44e255a5844dcb84d7e9bfab96c6493ce98dca67 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:26 +0100 Subject: [PATCH 03/20] ARM: mvebu: add Device Tree for the Armada 375 DB board The Armada 375 DB board is the development board from Marvell for the Armada 375 SoC. This commit adds a Device Tree description for this board, which enables the following features: * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash. Note that the SPI bus is disabled by default, because it conflicts with the NAND, and can only work if the board boots out of SPI. Since most boards are shipped to boot out of NAND, we're default to having the SPI bus disabled. * PCIe interfaces Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-375-db.dts | 130 ++++++++++++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/armada-375-db.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9d6a8b485e0..f1eafbdd4efe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-netgear-rn102.dtb \ armada-370-netgear-rn104.dtb \ armada-370-rd.dtb \ + armada-375-db.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts new file mode 100644 index 000000000000..9378d3136b41 --- /dev/null +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -0,0 +1,130 @@ +/* + * Device Tree file for Marvell Armada 375 evaluation board + * (DB-88F6720) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include +#include "armada-375.dtsi" + +/ { + model = "Marvell Armada 375 Development Board"; + compatible = "marvell,a375-db", "marvell,armada375"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + /* + * SPI conflicts with NAND, so we disable it + * here, and select NAND as the enabled device + * by default. + */ + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + }; + + i2c@11100 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + pinctrl { + sdio_st_pins: sdio-st-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "gpio"; + }; + }; + + nand: nand@d0000 { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins &sdio_st_pins>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; +}; From 0d3d96ab0059074a18dbb5fc2f9df859c06019bf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:28 +0100 Subject: [PATCH 04/20] ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a Cortex-A9 cores (single core for 380, dual core for 385) and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPU * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * Pinctrl * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers * Network interfaces Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-380.dtsi | 117 ++++++++++ arch/arm/boot/dts/armada-385.dtsi | 149 +++++++++++++ arch/arm/boot/dts/armada-38x.dtsi | 345 ++++++++++++++++++++++++++++++ 3 files changed, 611 insertions(+) create mode 100644 arch/arm/boot/dts/armada-380.dtsi create mode 100644 arch/arm/boot/dts/armada-385.dtsi create mode 100644 arch/arm/boot/dts/armada-38x.dtsi diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi new file mode 100644 index 000000000000..5a46ec7d207b --- /dev/null +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -0,0 +1,117 @@ +/* + * Device Tree Include file for Marvell Armada 380 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "armada-38x.dtsi" + +/ { + model = "Marvell Armada 380 family SoC"; + compatible = "marvell,armada380", "marvell,armada38x"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + internal-regs { + pinctrl { + compatible = "marvell,mv88f6810-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + + /* x1 port */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 70 0x4>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi new file mode 100644 index 000000000000..b22f5f1bd337 --- /dev/null +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -0,0 +1,149 @@ +/* + * Device Tree Include file for Marvell Armada 385 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 385 family SoC"; + compatible = "marvell,armada385", "marvell,armada38x"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + internal-regs { + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 70 0x4>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 71 0x4>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi new file mode 100644 index 000000000000..5a10248f4bb9 --- /dev/null +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -0,0 +1,345 @@ +/* + * Device Tree Include file for Marvell Armada 38x family of SoCs. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "skeleton.dtsi" + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 38x family SoC"; + compatible = "marvell,armada38x"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + eth0 = ð0; + eth1 = ð1; + eth2 = ð2; + }; + + soc { + compatible = "marvell,armada380-mbus", "marvell,armada370-mbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = <1 13 0x301>; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <0 1 0x4>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <0 63 0x4>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 2 0x4>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 3 0x4>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <0 12 4>; + reg-io-width = <1>; + status = "disabled"; + }; + + serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <0 13 4>; + reg-io-width = <1>; + status = "disabled"; + }; + + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 53 0x4>, <0 54 0x4>, + <0 55 0x4>, <0 56 0x4>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 58 0x4>, <0 59 0x4>, + <0 60 0x4>, <0 61 0x4>; + }; + + system-controller@18200 { + compatible = "marvell,armada-380-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-380-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-380-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = <1 15 0x4>; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic 0 8 4>, + <&gic 0 9 4>, + <&gic 0 10 4>, + <&gic 0 11 4>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + eth1: ethernet@30000 { + compatible = "marvell,armada-370-neta"; + reg = <0x30000 0x4000>; + interrupts-extended = <&mpic 10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + eth2: ethernet@34000 { + compatible = "marvell,armada-370-neta"; + reg = <0x34000 0x4000>; + interrupts-extended = <&mpic 12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = <0 22 0x4>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <0 23 0x4>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = <0 65 0x4>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <0 66 0x4>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + status = "disabled"; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + }; + }; + }; + + clocks { + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; From a47172ead196b9cab9e1eebca93fb4ae88927df4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:29 +0100 Subject: [PATCH 05/20] ARM: mvebu: add Device Tree for the Armada 385 DB board The Armada 385 DB board is the development board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash * PCIe interfaces Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-385-db.dts | 101 ++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 arch/arm/boot/dts/armada-385-db.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f1eafbdd4efe..bd789fcd1972 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-netgear-rn104.dtb \ armada-370-rd.dtb \ armada-375-db.dtb \ + armada-385-db.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts new file mode 100644 index 000000000000..01b6cc76ddc8 --- /dev/null +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -0,0 +1,101 @@ +/* + * Device Tree file for Marvell Armada 385 evaluation board + * (DB-88F6820) + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 385 Development Board"; + compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@11100 { + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; +}; From ae10f8329f9b22d650aa12307b260eba2bc0c571 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Mon, 17 Feb 2014 19:09:58 +0000 Subject: [PATCH 06/20] ARM: dove: dt: revert PMU interrupt controller node The corresponding driver didn't make it into v3.14, so we need to remove the node. Dove systems fail to boot with the node present and no driver. This node will be re-added when the driver makes it to mainline. Reported-by: Jean-Francois Moine Tested-by: Jean-Francois Moine Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 2b76524f4aa7..187fd46b7b5e 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -379,15 +379,6 @@ #clock-cells = <1>; }; - pmu_intc: pmu-interrupt-ctrl@d0050 { - compatible = "marvell,dove-pmu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd0050 0x8>; - interrupts = <33>; - marvell,#interrupts = <7>; - }; - pinctrl: pin-ctrl@d0200 { compatible = "marvell,dove-pinctrl"; reg = <0xd0200 0x10>; @@ -610,8 +601,6 @@ rtc: real-time-clock@d8500 { compatible = "marvell,orion-rtc"; reg = <0xd8500 0x20>; - interrupt-parent = <&pmu_intc>; - interrupts = <5>; }; gpio2: gpio-ctrl@e8400 { From f7f2ea9f49b0c97cfb386b14dda4aed2781cb9f1 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 20 Feb 2014 06:02:34 +1000 Subject: [PATCH 07/20] DT: Vendor prefixes: Add ricoh, qnap, sii and synology The following patches make use of vendor names: * ricoh (Ricoh Co. Ltd.); * qnap (QNAP Systems, Inc.); * sii (Seiko Instruments, Inc.); and * synology (Synology, Inc.) Add them to the vendor prefix list. Signed-off-by: Ben Peddell Signed-off-by: Andrew Lunn Acked-by: Jason Cooper Acked-by: Rob Herring Signed-off-by: Jason Cooper --- Documentation/devicetree/bindings/vendor-prefixes.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 3f900cd51bf0..c73b435f58f5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -65,10 +65,12 @@ picochip Picochip Ltd powervr PowerVR (deprecated, use img) qca Qualcomm Atheros, Inc. qcom Qualcomm, Inc. +qnap QNAP Systems, Inc. ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation +ricoh Ricoh Co. Ltd. rockchip Fuzhou Rockchip Electronics Co., Ltd samsung Samsung Semiconductor sbs Smart Battery System @@ -76,11 +78,13 @@ schindler Schindler sil Silicon Image silabs Silicon Laboratories simtek +sii Seiko Instruments, Inc. sirf SiRF Technology, Inc. snps Synopsys, Inc. st STMicroelectronics ste ST-Ericsson stericsson ST-Ericsson +synology Synology, Inc. ti Texas Instruments tlm Trusted Logic Mobility toshiba Toshiba Corporation From 36670de13d711f58467e99acbde4dfc0db98543c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 20 Feb 2014 06:02:36 +1000 Subject: [PATCH 08/20] DT: i2c: Trivial: Add sii,s35390a Add the Seiko Instruments Inc S35390a to the list of trivial i2c devices. Signed-off-by: Ben Peddell Signed-off-by: Andrew Lunn Acked-by: Jason Cooper Signed-off-by: Jason Cooper --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 1a1ac2e560e9..e11ed0fe770c 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -58,6 +58,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch ramtron,24c64 i2c serial eeprom (24cxx) ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) +sii,s35390a 2-wire CMOS real-time clock st-micro,24c256 i2c serial eeprom (24cxx) stm,m41t00 Serial Access TIMEKEEPER stm,m41t62 Serial real-time clock (RTC) with alarm From 2d0a7addbd109bd4a586d2ae2914a0047a4719de Mon Sep 17 00:00:00 2001 From: Ben Peddell Date: Thu, 20 Feb 2014 06:02:37 +1000 Subject: [PATCH 09/20] ARM: Kirkwood: Add support for many Synology NAS devices Add device tree fragments and files to support many of the kirkwood based Synology NAS devices. This is a modification of Andrew Lunn's translation of the board setup file maintained by Ben Peddell The Ricoh RS5C372 RTC was used in all 2009 units and some 2010 units. All other Synology Kirkwood-based DiskStations and RackStations use the Seiko S35390A RTC. Most of the 1-bay and 2-bay units use the GPIOs that are multiplexed with the built-in SATA interface activity/presence pins on mpp 20-23, while the 4-bay units use ge01 and a PCIe SATA controller, and put the software controlled HDD leds on mpp 36-43. Most of the 6281 units with HDD power controls use mpp 29 and 31, while most of the 6282 units with HDD power controls use mpp 30, 34, 44 and 45 and provide a model ID on mpp 28, 29, 46 and 47. Pre-2012 units and most 4-bay units didn't have a separate power control for HDD1. These power controls are presumably to limit startup current from the 12V brick power supply. Instead of using separate dtsi files in a synology directory, this patch uses a single dtsi file containing all of the modules for these boards, with all of the modules not common to all boards disabled. The board dts files then enable the appropriate modules for their boards. Signed-off-by: Andrew Lunn Signed-off-by: Ben Peddell Tested-by: Ben Peddell (ds211j) Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 15 + arch/arm/boot/dts/kirkwood-ds109.dts | 41 ++ arch/arm/boot/dts/kirkwood-ds110jv10.dts | 41 ++ arch/arm/boot/dts/kirkwood-ds111.dts | 44 ++ arch/arm/boot/dts/kirkwood-ds112.dts | 48 ++ arch/arm/boot/dts/kirkwood-ds209.dts | 44 ++ arch/arm/boot/dts/kirkwood-ds210.dts | 46 ++ arch/arm/boot/dts/kirkwood-ds212.dts | 47 ++ arch/arm/boot/dts/kirkwood-ds212j.dts | 41 ++ arch/arm/boot/dts/kirkwood-ds409.dts | 48 ++ arch/arm/boot/dts/kirkwood-ds409slim.dts | 40 ++ arch/arm/boot/dts/kirkwood-ds411.dts | 52 ++ arch/arm/boot/dts/kirkwood-ds411j.dts | 48 ++ arch/arm/boot/dts/kirkwood-ds411slim.dts | 48 ++ arch/arm/boot/dts/kirkwood-rs212.dts | 48 ++ arch/arm/boot/dts/kirkwood-rs409.dts | 44 ++ arch/arm/boot/dts/kirkwood-rs411.dts | 44 ++ arch/arm/boot/dts/kirkwood-synology.dtsi | 871 +++++++++++++++++++++++ 18 files changed, 1610 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-ds109.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds110jv10.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds111.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds112.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds209.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds210.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds212.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds212j.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds409.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds409slim.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds411.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds411j.dts create mode 100644 arch/arm/boot/dts/kirkwood-ds411slim.dts create mode 100644 arch/arm/boot/dts/kirkwood-rs212.dts create mode 100644 arch/arm/boot/dts/kirkwood-rs409.dts create mode 100644 arch/arm/boot/dts/kirkwood-rs411.dts create mode 100644 arch/arm/boot/dts/kirkwood-synology.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0eda36cbf7e0..7b54b05b9395 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -90,6 +90,18 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-ds110jv10.dtb \ + kirkwood-ds111.dtb \ + kirkwood-ds209.dtb \ + kirkwood-ds210.dtb \ + kirkwood-ds212.dtb \ + kirkwood-ds212j.dtb \ + kirkwood-ds409.dtb \ + kirkwood-ds409slim.dtb \ + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ kirkwood-goflexnet.dtb \ kirkwood-guruplug-server-plus.dtb \ kirkwood-ib62x0.dtb \ @@ -115,6 +127,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-rd88f6192.dtb \ kirkwood-rd88f6281-a0.dtb \ kirkwood-rd88f6281-a1.dtb \ + kirkwood-rs212.dtb \ + kirkwood-rs409.dtb \ + kirkwood-rs411.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts new file mode 100644 index 000000000000..772092c94ca3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds109.dts @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS109, DS110, DS110jv20"; + compatible = "synology,ds109", "synology,ds110jv20", + "synology,ds110", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts new file mode 100644 index 000000000000..aabafbe0da4c --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS110j v10 and v30"; + compatible = "synology,ds110jv10", "synology,ds110jv30", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts new file mode 100644 index 000000000000..16ec7fbab573 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds111.dts @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS111"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts new file mode 100644 index 000000000000..cff1b2388765 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds112.dts @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS111"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-21-2 { + status = "okay"; + }; + + regulators-hdd-30 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts new file mode 100644 index 000000000000..330411993d38 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds209.dts @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS209"; + compatible = "synology,ds209", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts new file mode 100644 index 000000000000..6052eaa37d4f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds210.dts @@ -0,0 +1,46 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS210 v10, v20, v30, DS211j"; + compatible = "synology,ds210jv10", "synology,ds210jv20", + "synology,ds210jv30", "synology,ds211j", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts new file mode 100644 index 000000000000..7f76cd30e84e --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds212.dts @@ -0,0 +1,47 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; + compatible = "synology,ds212", "synology,ds212pv10", + "synology,ds212pv10", "synology,ds212pv20", + "synology,ds213airv10", "synology,ds213v10", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts new file mode 100644 index 000000000000..1f83a00f1f74 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212j v10, v20"; + compatible = "synology,ds212jv10", "synology,ds212jv20", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts new file mode 100644 index 000000000000..0a573add44a2 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds409.dts @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS409, DS410j"; + compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts new file mode 100644 index 000000000000..1848a6245fd3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts @@ -0,0 +1,40 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology 409slim"; + compatible = "synology,ds409slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-20 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts new file mode 100644 index 000000000000..a1737b4311c6 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411.dts @@ -0,0 +1,52 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411, DS413jv10"; + compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + regulators-hdd-34 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts new file mode 100644 index 000000000000..0cde914eceae --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411j"; + compatible = "synology,ds411j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts new file mode 100644 index 000000000000..aef0cadc2c78 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411slim"; + compatible = "synology,ds411slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts new file mode 100644 index 000000000000..93ec3d00c6ab --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs212.dts @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS212"; + compatible = "synology,rs212", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-38 { + status = "okay"; + }; + + regulators-hdd-30-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts new file mode 100644 index 000000000000..311df4e5aa28 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs409.dts @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS409"; + compatible = "synology,rs409", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts new file mode 100644 index 000000000000..f90da850bb31 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs411.dts @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS411 RS812"; + compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi new file mode 100644 index 000000000000..4227c974729d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -0,0 +1,871 @@ +/* + * Nodes for Marvell 628x Synology devices + * + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/ { + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie2: pcie@2,0 { + status = "disabled"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pmx_alarmled_12: pmx-alarmled-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_15: pmx-fanctrl-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_16: pmx-fanctrl-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_17: pmx-fanctrl-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_18: pmx-fanalarm-18 { + marvell,pins = "mpp18"; + marvell,function = "gpo"; + }; + + pmx_hddled_20: pmx-hddled-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_hddled_21: pmx-hddled-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_hddled_22: pmx-hddled-22 { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_hddled_23: pmx-hddled-23 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_hddled_24: pmx-hddled-24 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_hddled_25: pmx-hddled-25 { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + pmx_hddled_26: pmx-hddled-26 { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + pmx_hddled_27: pmx-hddled-27 { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + pmx_hddled_28: pmx-hddled-28 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_32: pmx-fanctrl-32 { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_33: pmx-fanctrl-33 { + marvell,pins = "mpp33"; + marvell,function = "gpo"; + }; + + pmx_fanctrl_34: pmx-fanctrl-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_35: pmx-fanalarm-35 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + pmx_hddled_36: pmx-hddled-36 { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_hddled_37: pmx-hddled-37 { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_hddled_38: pmx-hddled-38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_hddled_39: pmx-hddled-39 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_hddled_40: pmx-hddled-40 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_hddled_41: pmx-hddled-41 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_hddled_42: pmx-hddled-42 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_hddled_43: pmx-hddled-43 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + pmx_hddled_44: pmx-hddled-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hddled_45: pmx-hddled-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_44: pmx-fanalarm-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_45: pmx-fanalarm-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + }; + + rtc@10300 { + status = "disabled"; + }; + + spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@00000000 { + reg = <0x00000000 0x00080000>; + label = "RedBoot"; + }; + + partition@00080000 { + reg = <0x00080000 0x00200000>; + label = "zImage"; + }; + + partition@00280000 { + reg = <0x00280000 0x00140000>; + label = "rd.gz"; + }; + + partition@003c0000 { + reg = <0x003c0000 0x00010000>; + label = "vendor"; + }; + + partition@003d0000 { + reg = <0x003d0000 0x00020000>; + label = "RedBoot config"; + }; + + partition@003f0000 { + reg = <0x003f0000 0x00010000>; + label = "FIS directory"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + + rs5c372: rs5c372@32 { + status = "disabled"; + compatible = "ricoh,rs5c372"; + reg = <0x32>; + }; + + s35390a: s35390a@30 { + status = "disabled"; + compatible = "ssi,s35390a"; + reg = <0x30>; + }; + }; + + serial@12000 { + status = "okay"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + }; + + serial@12100 { + status = "okay"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-fan-150-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-150-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-100-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-1 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-3 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH + &gpio1 12 GPIO_ACTIVE_HIGH + &gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-leds-alarm-12 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_alarmled_12>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:alarm"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-20 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 + &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 + &pmx_hddled_26 &pmx_hddled_27>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-1 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-2 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-36 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 + &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 + &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 + &pmx_hddled_45>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + hdd5-green { + label = "synology:green:hdd5"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + hdd5-amber { + label = "synology:amber:hdd5"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-38 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; + + regulators-hdd-29 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-1 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-2 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-4 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 + &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-31 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-34 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 + &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <8>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <9>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "disabled"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; From a2be1561a3f6ea5e7ffb1ce42c0db9cb1bc7ab28 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 20 Feb 2014 12:11:29 +0100 Subject: [PATCH 10/20] ARM: mvebu: use C preprocessor include for Armada 375/38x DTs Some of the Armada 375/38x DTs that were recently submitted were still using the old-style /include/ instead of the new-style, C-preprocessor based #include. Since we are going to start including more headers, switching to the C-preprocessor based includes is important. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 2 +- arch/arm/boot/dts/armada-380.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 9f5cb5163a7e..c89fee488319 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -11,7 +11,7 @@ * warranty of any kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 5a46ec7d207b..82b33473a146 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -12,7 +12,7 @@ * warranty of any kind, whether express or implied. */ -/include/ "armada-38x.dtsi" +#include "armada-38x.dtsi" / { model = "Marvell Armada 380 family SoC"; From f327d43da130fe6a4a0b3ecf6ad27eff7fd92877 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 20 Feb 2014 12:11:30 +0100 Subject: [PATCH 11/20] ARM: mvebu: use GIC_{SPI,PPI} in Armada 375/38x DTs Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts, use the definitions of to clarify the Device Tree code. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 53 ++++++++++++++++--------------- arch/arm/boot/dts/armada-380.dtsi | 6 ++-- arch/arm/boot/dts/armada-385.dtsi | 8 ++--- arch/arm/boot/dts/armada-38x.dtsi | 41 ++++++++++++------------ 4 files changed, 55 insertions(+), 53 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c89fee488319..23d497f3f3bc 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -12,6 +12,7 @@ */ #include "skeleton.dtsi" +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -129,7 +130,7 @@ timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; - interrupts = <1 13 0x301>; + interrupts = ; clocks = <&coreclk 2>; }; @@ -148,7 +149,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; - interrupts = <0 1 0x4>; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -159,7 +160,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - interrupts = <0 63 0x4>; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -169,7 +170,7 @@ reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 2 0x4>; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -180,7 +181,7 @@ reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 3 0x4>; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -190,7 +191,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; - interrupts = <0 12 4>; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -199,7 +200,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; - interrupts = <0 13 4>; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -248,8 +249,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 53 0x4>, <0 54 0x4>, - <0 55 0x4>, <0 56 0x4>; + interrupts = , , + , ; }; gpio1: gpio@18140 { @@ -260,8 +261,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 58 0x4>, <0 59 0x4>, - <0 60 0x4>, <0 61 0x4>; + interrupts = , , + , ; }; gpio2: gpio@18180 { @@ -272,7 +273,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 62 0x4>; + interrupts = ; }; system-controller@18200 { @@ -299,16 +300,16 @@ #size-cells = <1>; interrupt-controller; msi-controller; - interrupts = <1 15 0x4>; + interrupts = ; }; timer@20300 { compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic 0 8 4>, - <&gic 0 9 4>, - <&gic 0 10 4>, - <&gic 0 11 4>, + interrupts-extended = <&gic GIC_SPI 8 4>, + <&gic GIC_SPI 9 4>, + <&gic GIC_SPI 10 4>, + <&gic GIC_SPI 11 4>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 0>; @@ -322,12 +323,12 @@ status = "okay"; xor00 { - interrupts = <0 22 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor01 { - interrupts = <0 23 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -342,12 +343,12 @@ status = "okay"; xor10 { - interrupts = <0 65 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor11 { - interrupts = <0 66 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -357,7 +358,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; reg = <0xa0000 0x5000>; - interrupts = <0 26 0x4>; + interrupts = ; clocks = <&gateclk 14>, <&gateclk 20>; clock-names = "0", "1"; status = "disabled"; @@ -368,7 +369,7 @@ reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <1>; - interrupts = <0 84 0x4>; + interrupts = ; clocks = <&gateclk 11>; status = "disabled"; }; @@ -376,7 +377,7 @@ mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; - interrupts = <0 25 0x4>; + interrupts = ; clocks = <&gateclk 17>; bus-width = <4>; cap-sdio-irq; @@ -429,7 +430,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -446,7 +447,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 82b33473a146..678ba3d0c485 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -70,7 +70,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; @@ -88,7 +88,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -106,7 +106,7 @@ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 70 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index b22f5f1bd337..055bc2f1c051 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -81,7 +81,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; @@ -99,7 +99,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -117,7 +117,7 @@ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 70 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; @@ -138,7 +138,7 @@ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 71 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 0x4>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 5a10248f4bb9..502d21ae7b61 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -13,6 +13,7 @@ */ #include "skeleton.dtsi" +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -109,7 +110,7 @@ timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; - interrupts = <1 13 0x301>; + interrupts = ; clocks = <&coreclk 2>; }; @@ -128,7 +129,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; - interrupts = <0 1 0x4>; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -139,7 +140,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - interrupts = <0 63 0x4>; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -149,7 +150,7 @@ reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 2 0x4>; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -160,7 +161,7 @@ reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 3 0x4>; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -170,7 +171,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; - interrupts = <0 12 4>; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -179,7 +180,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; - interrupts = <0 13 4>; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -197,8 +198,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 53 0x4>, <0 54 0x4>, - <0 55 0x4>, <0 56 0x4>; + interrupts = , , + , ; }; gpio1: gpio@18140 { @@ -209,8 +210,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 58 0x4>, <0 59 0x4>, - <0 60 0x4>, <0 61 0x4>; + interrupts = , , + , ; }; system-controller@18200 { @@ -244,17 +245,17 @@ #size-cells = <1>; interrupt-controller; msi-controller; - interrupts = <1 15 0x4>; + interrupts = ; }; timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic 0 8 4>, - <&gic 0 9 4>, - <&gic 0 10 4>, - <&gic 0 11 4>, + interrupts-extended = <&gic GIC_SPI 8 4>, + <&gic GIC_SPI 9 4>, + <&gic GIC_SPI 10 4>, + <&gic GIC_SPI 11 4>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 2>, <&refclk>; @@ -285,12 +286,12 @@ status = "okay"; xor00 { - interrupts = <0 22 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor01 { - interrupts = <0 23 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -305,12 +306,12 @@ status = "okay"; xor10 { - interrupts = <0 65 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor11 { - interrupts = <0 66 0x4>; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; From d11548e3113961b3d3c0b362f0dbe72d72a7959b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 20 Feb 2014 12:11:31 +0100 Subject: [PATCH 12/20] ARM: mvebu: use macros for interrupt flags on Armada 375/38x Instead of hardcoding the values of the interrupt flags, use the macros provided by and for the Armada 375 and Armada 38x Device Tree files. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 57 +++++++++++++++++-------------- arch/arm/boot/dts/armada-380.dtsi | 6 ++-- arch/arm/boot/dts/armada-385.dtsi | 8 ++--- arch/arm/boot/dts/armada-38x.dtsi | 45 +++++++++++++----------- 4 files changed, 63 insertions(+), 53 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 23d497f3f3bc..3877693fb2d8 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -13,6 +13,7 @@ #include "skeleton.dtsi" #include +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -130,7 +131,7 @@ timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; - interrupts = ; + interrupts = ; clocks = <&coreclk 2>; }; @@ -149,7 +150,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; - interrupts = ; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -160,7 +161,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - interrupts = ; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -170,7 +171,7 @@ reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -181,7 +182,7 @@ reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -191,7 +192,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; - interrupts = ; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -200,7 +201,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; - interrupts = ; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -249,8 +250,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = , , - , ; + interrupts = , + , + , + ; }; gpio1: gpio@18140 { @@ -261,8 +264,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = , , - , ; + interrupts = , + , + , + ; }; gpio2: gpio@18180 { @@ -273,7 +278,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = ; + interrupts = ; }; system-controller@18200 { @@ -300,16 +305,16 @@ #size-cells = <1>; interrupt-controller; msi-controller; - interrupts = ; + interrupts = ; }; timer@20300 { compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 4>, - <&gic GIC_SPI 9 4>, - <&gic GIC_SPI 10 4>, - <&gic GIC_SPI 11 4>, + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 0>; @@ -323,12 +328,12 @@ status = "okay"; xor00 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor01 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -343,12 +348,12 @@ status = "okay"; xor10 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor11 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -358,7 +363,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; reg = <0xa0000 0x5000>; - interrupts = ; + interrupts = ; clocks = <&gateclk 14>, <&gateclk 20>; clock-names = "0", "1"; status = "disabled"; @@ -369,7 +374,7 @@ reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <1>; - interrupts = ; + interrupts = ; clocks = <&gateclk 11>; status = "disabled"; }; @@ -377,7 +382,7 @@ mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; - interrupts = ; + interrupts = ; clocks = <&gateclk 17>; bus-width = <4>; cap-sdio-irq; @@ -430,7 +435,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -447,7 +452,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 678ba3d0c485..068031f0f263 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -70,7 +70,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; @@ -88,7 +88,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -106,7 +106,7 @@ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index 055bc2f1c051..e2919f02e1d4 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -81,7 +81,7 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; @@ -99,7 +99,7 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -117,7 +117,7 @@ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; @@ -138,7 +138,7 @@ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 0x4>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 502d21ae7b61..812ce280b349 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -14,6 +14,7 @@ #include "skeleton.dtsi" #include +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -110,7 +111,7 @@ timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; - interrupts = ; + interrupts = ; clocks = <&coreclk 2>; }; @@ -129,7 +130,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; - interrupts = ; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -140,7 +141,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - interrupts = ; + interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; @@ -150,7 +151,7 @@ reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -161,7 +162,7 @@ reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -171,7 +172,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; - interrupts = ; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -180,7 +181,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; - interrupts = ; + interrupts = ; reg-io-width = <1>; status = "disabled"; }; @@ -198,8 +199,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = , , - , ; + interrupts = , + , + , + ; }; gpio1: gpio@18140 { @@ -210,8 +213,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = , , - , ; + interrupts = , + , + , + ; }; system-controller@18200 { @@ -245,17 +250,17 @@ #size-cells = <1>; interrupt-controller; msi-controller; - interrupts = ; + interrupts = ; }; timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 4>, - <&gic GIC_SPI 9 4>, - <&gic GIC_SPI 10 4>, - <&gic GIC_SPI 11 4>, + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 2>, <&refclk>; @@ -286,12 +291,12 @@ status = "okay"; xor00 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor01 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -306,12 +311,12 @@ status = "okay"; xor10 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; }; xor11 { - interrupts = ; + interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; From e65d9c61cb6ab86b5e8fe76d0fab0a62879fd2c6 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 22 Feb 2014 20:14:53 +0100 Subject: [PATCH 13/20] ARM: kirkwood: Instantiate L2 cache from DT. Now that the Feroceon L2 cache has a DT binding, make use of it. Signed-off-by: Andrew Lunn Acked-by: Arnd Bergmann Tested-by: Jason Gunthorpe Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 85542c2f34b1..1c088ae70c5d 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -161,6 +161,11 @@ #clock-cells = <1>; }; + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; + intc: main-interrupt-ctrl@20200 { compatible = "marvell,orion-intc"; interrupt-controller; From 7702693758311cca28ae2d4851f7b94c846af4ec Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 22 Feb 2014 20:14:59 +0100 Subject: [PATCH 14/20] ARM: mvebu: Instantiate system controller in kirkwood.dtsi Make use of the mvebu system controller, by placing a node into the dtsi file. Signed-off-by: Andrew Lunn Acked-by: Arnd Bergmann Tested-by: Jason Gunthorpe Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 1c088ae70c5d..7b921b30cfcb 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -145,6 +145,11 @@ reg = <0x20000 0x80>, <0x1500 0x20>; }; + system-controller@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x120>; + }; + bridge_intc: bridge-interrupt-ctrl@20110 { compatible = "marvell,orion-bridge-intc"; interrupt-controller; From 5db263743d5d43f9d35ad61dbbececda72bee7b8 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 24 Feb 2014 09:42:55 +0100 Subject: [PATCH 15/20] ARM: dove: add additional pinctrl registers Dove pinctrl uses additional registers to control MPPs. This patch first increases existing pinctrl reg property by one register, and then adds two new ranges for MPP4 and PMU MPP registers. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 644b1f40cb30..ca9ba9ac8c4f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -389,7 +389,9 @@ pinctrl: pin-ctrl@d0200 { compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x10>; + reg = <0xd0200 0x14>, + <0xd0440 0x04>, + <0xd802c 0x08>; clocks = <&gate_clk 22>; pmx_gpio_0: pmx-gpio-0 { From 7a98c18f71a23b70775327d7f993cf36db162b43 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 24 Feb 2014 09:42:56 +0100 Subject: [PATCH 16/20] ARM: dove: add global-config register node We share global config registers by syscon node, add it to dove.dtsi. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index ca9ba9ac8c4f..43cbdc2366b3 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -613,6 +613,12 @@ reg = <0xd8500 0x20>; }; + gconf: global-config@e802c { + compatible = "marvell,dove-global-config", + "syscon"; + reg = <0xe802c 0x14>; + }; + gpio2: gpio-ctrl@e8400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; From b89af936c911ed613d1868699d4eb4b7978c54f1 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Tue, 25 Feb 2014 17:00:10 +0000 Subject: [PATCH 17/20] ARM: mvebu: select dtbs from MACH_ARMADA_* With kirkwood migrating into mach-mvebu, mvebu_v5_defconfig needs to select ARCH_MVEBU. Unfortunately, this means that when building a v5 kernel, we unnecessarily build dtbs for the armada v7 boards. To fix this, we instead select based on MACH_ARMADA_* on a per SoC basis. Reported-by: Kevin Hilman Acked-by: Kevin Hilman Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 46c54a2dac71..1e6dbde1724e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -142,13 +142,17 @@ dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-apq8074-dragonboard.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ +dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb \ - armada-375-db.dtb \ - armada-385-db.dtb \ + armada-370-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb +dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb +dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ From b3f742cc76274644c3346e9e1af3f22f40a36dd3 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 25 Feb 2014 18:33:59 +0100 Subject: [PATCH 18/20] ARM: kirkwood: Add audio node to kirkwood.dtsi The binding has existed for a while, so add the missing node so it can be used by devices. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 7b921b30cfcb..5a86fa820e12 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -310,5 +310,14 @@ #phy-cells = <0>; status = "ok"; }; + + audio0: audio-controller@a0000 { + compatible = "marvell,kirkwood-audio"; + reg = <0xa0000 0x2210>; + interrupts = <24>; + clocks = <&gate_clk 9>; + clock-names = "internal"; + status = "disabled"; + }; }; }; From cb932e12d931f7973ac3ac66004977aec8fc87c0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 25 Feb 2014 18:34:00 +0100 Subject: [PATCH 19/20] ARM: kirkwood: Add i2c alias so setting bus number When using platform_driver instantiation, the i2c bus was given bus number 0. The kirkwood-t5325 audio driver has this bus number hard coded for the address of the codec. However by default device tree i2c busses are dynamically allocated a bus number, starting from 1. Thus the kirkwood-t5325 cannot find its audio codec. By adding an alias in the DT file we can control the bus number and set it to 0. The codec can then be found. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 5a86fa820e12..90384587c278 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -24,6 +24,7 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; + i2c0 = &i2c0; }; mbus { @@ -111,7 +112,7 @@ clocks = <&gate_clk 7>; }; - i2c@11000 { + i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; From e2b15689dcb052b8c4c6580c79aef50052c55581 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 25 Feb 2014 18:34:02 +0100 Subject: [PATCH 20/20] ARM: kirkwood: Add dts file describing HP T5325 thin client Describe the T5325 using device tree properties, where possible. The first version of this file was produced by Thomas Petazzoni. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-t5325.dts | 208 +++++++++++++++++++++++++++ 2 files changed, 209 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-t5325.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1e6dbde1724e..a292b3cc94a5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-rs411.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ + kirkwood-t5325.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts new file mode 100644 index 000000000000..7d1c7677a18f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -0,0 +1,208 @@ +/* + * Device Tree file for HP t5325 Thin Client" + * + * Copyright (C) 2014 + * + * Thomas Petazzoni + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "HP t5325 Thin Client"; + compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_i2s &pmx_sysrst>; + pinctrl-names = "default"; + + pmx_button_power: pmx-button_power { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + /* + * Redefined from kirkwood-6281.dtsi, because + * we don't use SPI CS on MPP0, but on MPP7. + */ + pmx_spi: pmx-spi { + marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; + marvell,function = "spi"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_i2s: pmx-i2s { + marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", + "mpp43"; + marvell,function = "audio"; + }; + }; + + spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <86000000>; + reg = <0>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + + partition@1 { + reg = <0x80000 0x40000>; + label = "SSD firmware"; + }; + + partition@2 { + reg = <0xc0000 0x10000>; + label = "u-boot env"; + }; + + partition@3 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + + partition@4 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + + alc5621: alc5621@1a { + compatible = "realtek,alc5621"; + reg = <0x1a>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + audio: audio-controller@a0000 { + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_sata_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB-SATA Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_power>; + pinctrl-names = "default"; + + button@1 { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +};