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e1000e: Fix/cleanup PHY reset code for ICHx/PCHx
i) Fixes a bug where e1000_sw_lcd_config_ich8lan() was calling e1000_lan_init_done_ich8lan() to poll the STATUS.LAN_INIT_DONE bit to make sure the MAC had completed the PHY configuration. However, e1000_lan_init_done_ich8lan() had already been called in one of the two places where PHY reset occurs for ICHx/PCHx parts, which caused the second call to busy-wait for 150 msec because the LAN_INIT_DONE bit had already been checked and cleared. ii) Cleanup the two separate PHY reset code paths, i.e. the full-chip reset in e1000_reset_hw_ich8lan() and the PHY-only reset in e1000_phy_hw_reset_ich8lan(). There was duplicate code in both paths to be performed post-reset that are now combined into one new function - e1000_post_phy_reset_ich8lan(). This cleanup also included moving the clearing of the PHY Reset Asserted bit in the STATUS register (now done for all ICH/PCH parts) and the check for the indication from h/w that basic configuration has completed back to where it previously was in e1000_get_cfg_done_ich8lan(). iii) Corrected a few comments Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bruce Allan
David S. Miller
parent
a305595b12
commit
e98cac447c
@ -850,9 +850,6 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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if (!(data & sw_cfg_mask))
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goto out;
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/* Wait for basic configuration completes before proceeding */
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e1000_lan_init_done_ich8lan(hw);
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/*
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* Make sure HW does not configure LCD from PHY
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* extended configuration before SW configuration
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@ -1260,30 +1257,26 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
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}
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/**
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* e1000_phy_hw_reset_ich8lan - Performs a PHY reset
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* e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
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* @hw: pointer to the HW structure
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*
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* Resets the PHY
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* This is a function pointer entry point called by drivers
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* or other shared routines.
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**/
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static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
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static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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u16 reg;
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ret_val = e1000e_phy_hw_reset_generic(hw);
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if (ret_val)
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return ret_val;
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/* Allow time for h/w to get to a quiescent state after reset */
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mdelay(10);
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if (e1000_check_reset_block(hw))
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goto out;
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/* Perform any necessary post-reset workarounds */
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if (hw->mac.type == e1000_pchlan) {
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switch (hw->mac.type) {
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case e1000_pchlan:
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ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
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if (ret_val)
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return ret_val;
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goto out;
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break;
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default:
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break;
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}
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/* Dummy read to clear the phy wakeup bit after lcd reset */
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@ -1296,11 +1289,32 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
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goto out;
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/* Configure the LCD with the OEM bits in NVM */
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if (hw->mac.type == e1000_pchlan)
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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out:
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return 0;
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return ret_val;
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}
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/**
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* e1000_phy_hw_reset_ich8lan - Performs a PHY reset
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* @hw: pointer to the HW structure
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*
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* Resets the PHY
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* This is a function pointer entry point called by drivers
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* or other shared routines.
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**/
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static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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ret_val = e1000e_phy_hw_reset_generic(hw);
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if (ret_val)
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goto out;
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ret_val = e1000_post_phy_reset_ich8lan(hw);
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out:
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return ret_val;
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}
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/**
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@ -2511,9 +2525,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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* on the last TLP read/write transaction when MAC is reset.
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*/
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ret_val = e1000e_disable_pcie_master(hw);
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if (ret_val) {
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if (ret_val)
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e_dbg("PCI-E Master disable polling has failed.\n");
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}
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e_dbg("Masking off all interrupts\n");
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ew32(IMC, 0xffffffff);
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@ -2552,14 +2565,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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ctrl = er32(CTRL);
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if (!e1000_check_reset_block(hw)) {
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/* Clear PHY Reset Asserted bit */
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if (hw->mac.type >= e1000_pchlan) {
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u32 status = er32(STATUS);
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ew32(STATUS, status & ~E1000_STATUS_PHYRA);
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}
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/*
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* PHY HW reset requires MAC CORE reset at the same
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* Full-chip reset requires MAC and PHY reset at the same
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* time to make sure the interface between MAC and the
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* external PHY is reset.
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*/
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@ -2573,39 +2580,16 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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if (!ret_val)
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e1000_release_swflag_ich8lan(hw);
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/* Perform any necessary post-reset workarounds */
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if (hw->mac.type == e1000_pchlan)
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ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
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if (ctrl & E1000_CTRL_PHY_RST)
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if (ctrl & E1000_CTRL_PHY_RST) {
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ret_val = hw->phy.ops.get_cfg_done(hw);
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if (ret_val)
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goto out;
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if (hw->mac.type >= e1000_ich10lan) {
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e1000_lan_init_done_ich8lan(hw);
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} else {
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ret_val = e1000e_get_auto_rd_done(hw);
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if (ret_val) {
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/*
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* When auto config read does not complete, do not
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* return with an error. This can happen in situations
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* where there is no eeprom and prevents getting link.
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*/
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e_dbg("Auto Read Done did not complete\n");
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}
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}
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/* Dummy read to clear the phy wakeup bit after lcd reset */
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if (hw->mac.type == e1000_pchlan)
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e1e_rphy(hw, BM_WUC, ®);
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ret_val = e1000_sw_lcd_config_ich8lan(hw);
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if (ret_val)
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goto out;
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if (hw->mac.type == e1000_pchlan) {
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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ret_val = e1000_post_phy_reset_ich8lan(hw);
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if (ret_val)
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goto out;
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}
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/*
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* For PCH, this write will make sure that any noise
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* will be detected as a CRC error and be dropped rather than show up
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@ -3291,33 +3275,50 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
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}
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/**
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* e1000_get_cfg_done_ich8lan - Read config done bit
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* e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
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* @hw: pointer to the HW structure
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*
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* Read the management control register for the config done bit for
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* completion status. NOTE: silicon which is EEPROM-less will fail trying
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* to read the config done bit, so an error is *ONLY* logged and returns
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* 0. If we were to return with error, EEPROM-less silicon
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* would not be able to be reset or change link.
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* Read appropriate register for the config done bit for completion status
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* and configure the PHY through s/w for EEPROM-less parts.
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*
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* NOTE: some silicon which is EEPROM-less will fail trying to read the
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* config done bit, so only an error is logged and continues. If we were
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* to return with error, EEPROM-less silicon would not be able to be reset
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* or change link.
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**/
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static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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u32 bank = 0;
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if (hw->mac.type >= e1000_pchlan) {
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u32 status = er32(STATUS);
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if (status & E1000_STATUS_PHYRA)
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ew32(STATUS, status & ~E1000_STATUS_PHYRA);
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else
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e_dbg("PHY Reset Asserted not set - needs delay\n");
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}
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u32 status;
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e1000e_get_cfg_done(hw);
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/* Wait for indication from h/w that it has completed basic config */
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if (hw->mac.type >= e1000_ich10lan) {
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e1000_lan_init_done_ich8lan(hw);
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} else {
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ret_val = e1000e_get_auto_rd_done(hw);
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if (ret_val) {
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/*
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* When auto config read does not complete, do not
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* return with an error. This can happen in situations
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* where there is no eeprom and prevents getting link.
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*/
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e_dbg("Auto Read Done did not complete\n");
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ret_val = 0;
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}
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}
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/* Clear PHY Reset Asserted bit */
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status = er32(STATUS);
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if (status & E1000_STATUS_PHYRA)
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ew32(STATUS, status & ~E1000_STATUS_PHYRA);
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else
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e_dbg("PHY Reset Asserted not set - needs delay\n");
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/* If EEPROM is not marked present, init the IGP 3 PHY manually */
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if ((hw->mac.type != e1000_ich10lan) &&
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(hw->mac.type != e1000_pchlan)) {
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if (hw->mac.type <= e1000_ich9lan) {
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if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
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(hw->phy.type == e1000_phy_igp_3)) {
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e1000e_phy_init_script_igp3(hw);
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@ -3326,11 +3327,11 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
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if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
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/* Maybe we should do a basic PHY config */
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e_dbg("EEPROM not present\n");
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return -E1000_ERR_CONFIG;
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ret_val = -E1000_ERR_CONFIG;
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}
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}
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return 0;
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return ret_val;
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}
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/**
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