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dmaengine: ti: k3-psil: add map for j7200
Add new PSI-L map file for the new TI j7200 SoC. The DMA hardware in j7200 is the same as in j721e with different set of peripherals resulting different PSI-L thread map compered to j721e. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20200803125713.17829-3-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Peter Ujfalusi
Vinod Koul
parent
ce310bd704
commit
e9ca48d9bf
@ -4,5 +4,8 @@ obj-$(CONFIG_TI_EDMA) += edma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o
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obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o
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obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o k3-psil-am654.o k3-psil-j721e.o
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obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o \
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k3-psil-am654.o \
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k3-psil-j721e.o \
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k3-psil-j7200.o
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obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o
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175
drivers/dma/ti/k3-psil-j7200.c
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175
drivers/dma/ti/k3-psil-j7200.c
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@ -0,0 +1,175 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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#define PSIL_SA2UL(x, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.notdpkt = tx, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep j7200_src_ep_map[] = {
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/* PDMA_MCASP - McASP0-2 */
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PSIL_PDMA_MCASP(0x4400),
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PSIL_PDMA_MCASP(0x4401),
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PSIL_PDMA_MCASP(0x4402),
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/* PDMA_SPI_G0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0x4600),
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PSIL_PDMA_XY_PKT(0x4601),
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PSIL_PDMA_XY_PKT(0x4602),
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PSIL_PDMA_XY_PKT(0x4603),
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PSIL_PDMA_XY_PKT(0x4604),
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PSIL_PDMA_XY_PKT(0x4605),
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PSIL_PDMA_XY_PKT(0x4606),
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PSIL_PDMA_XY_PKT(0x4607),
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PSIL_PDMA_XY_PKT(0x4608),
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PSIL_PDMA_XY_PKT(0x4609),
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PSIL_PDMA_XY_PKT(0x460a),
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PSIL_PDMA_XY_PKT(0x460b),
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PSIL_PDMA_XY_PKT(0x460c),
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PSIL_PDMA_XY_PKT(0x460d),
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PSIL_PDMA_XY_PKT(0x460e),
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PSIL_PDMA_XY_PKT(0x460f),
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/* PDMA_SPI_G1 - SPI4-7 */
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PSIL_PDMA_XY_PKT(0x4610),
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PSIL_PDMA_XY_PKT(0x4611),
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PSIL_PDMA_XY_PKT(0x4612),
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PSIL_PDMA_XY_PKT(0x4613),
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PSIL_PDMA_XY_PKT(0x4614),
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PSIL_PDMA_XY_PKT(0x4615),
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PSIL_PDMA_XY_PKT(0x4616),
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PSIL_PDMA_XY_PKT(0x4617),
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PSIL_PDMA_XY_PKT(0x4618),
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PSIL_PDMA_XY_PKT(0x4619),
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PSIL_PDMA_XY_PKT(0x461a),
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PSIL_PDMA_XY_PKT(0x461b),
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PSIL_PDMA_XY_PKT(0x461c),
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PSIL_PDMA_XY_PKT(0x461d),
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PSIL_PDMA_XY_PKT(0x461e),
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PSIL_PDMA_XY_PKT(0x461f),
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/* PDMA_USART_G0 - UART0-1 */
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PSIL_PDMA_XY_PKT(0x4700),
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PSIL_PDMA_XY_PKT(0x4701),
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/* PDMA_USART_G1 - UART2-3 */
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PSIL_PDMA_XY_PKT(0x4702),
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PSIL_PDMA_XY_PKT(0x4703),
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/* PDMA_USART_G2 - UART4-9 */
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PSIL_PDMA_XY_PKT(0x4704),
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PSIL_PDMA_XY_PKT(0x4705),
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PSIL_PDMA_XY_PKT(0x4706),
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PSIL_PDMA_XY_PKT(0x4707),
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PSIL_PDMA_XY_PKT(0x4708),
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PSIL_PDMA_XY_PKT(0x4709),
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/* CPSW5 */
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PSIL_ETHERNET(0x4a00),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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/* MCU_PDMA_MISC_G0 - SPI0 */
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PSIL_PDMA_XY_PKT(0x7100),
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PSIL_PDMA_XY_PKT(0x7101),
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PSIL_PDMA_XY_PKT(0x7102),
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PSIL_PDMA_XY_PKT(0x7103),
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/* MCU_PDMA_MISC_G1 - SPI1-2 */
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PSIL_PDMA_XY_PKT(0x7200),
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PSIL_PDMA_XY_PKT(0x7201),
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PSIL_PDMA_XY_PKT(0x7202),
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PSIL_PDMA_XY_PKT(0x7203),
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PSIL_PDMA_XY_PKT(0x7204),
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PSIL_PDMA_XY_PKT(0x7205),
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PSIL_PDMA_XY_PKT(0x7206),
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PSIL_PDMA_XY_PKT(0x7207),
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/* MCU_PDMA_MISC_G2 - UART0 */
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PSIL_PDMA_XY_PKT(0x7300),
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/* MCU_PDMA_ADC - ADC0-1 */
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PSIL_PDMA_XY_TR(0x7400),
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PSIL_PDMA_XY_TR(0x7401),
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep j7200_dst_ep_map[] = {
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/* CPSW5 */
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PSIL_ETHERNET(0xca00),
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PSIL_ETHERNET(0xca01),
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PSIL_ETHERNET(0xca02),
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PSIL_ETHERNET(0xca03),
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PSIL_ETHERNET(0xca04),
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PSIL_ETHERNET(0xca05),
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PSIL_ETHERNET(0xca06),
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PSIL_ETHERNET(0xca07),
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/* CPSW0 */
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PSIL_ETHERNET(0xf000),
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PSIL_ETHERNET(0xf001),
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PSIL_ETHERNET(0xf002),
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PSIL_ETHERNET(0xf003),
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PSIL_ETHERNET(0xf004),
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),
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};
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struct psil_ep_map j7200_ep_map = {
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.name = "j7200",
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.src = j7200_src_ep_map,
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.src_count = ARRAY_SIZE(j7200_src_ep_map),
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.dst = j7200_dst_ep_map,
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.dst_count = ARRAY_SIZE(j7200_dst_ep_map),
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};
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@ -39,5 +39,6 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
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/* SoC PSI-L endpoint maps */
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extern struct psil_ep_map am654_ep_map;
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extern struct psil_ep_map j721e_ep_map;
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extern struct psil_ep_map j7200_ep_map;
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#endif /* K3_PSIL_PRIV_H_ */
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@ -19,6 +19,7 @@ static const struct psil_ep_map *soc_ep_map;
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static const struct soc_device_attribute k3_soc_devices[] = {
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{ .family = "AM65X", .data = &am654_ep_map },
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{ .family = "J721E", .data = &j721e_ep_map },
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{ .family = "J7200", .data = &j7200_ep_map },
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{ /* sentinel */ }
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};
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