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ath5k: Fix bitmasks and typos for PCU Diagnostic register
As reported by Ryan Niemi, some bitmasks in the register definition for the PCU Diagnostic register (DIAG_SW) were missing a zero at the end. While at it fix some typos and add more comments. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -244,7 +244,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
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/* Force channel idle high */
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AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
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AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
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AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
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/* Wait a while and disable mechanism */
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udelay(200);
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@ -261,7 +261,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
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} while (--i && pending);
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AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
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AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
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AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
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}
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/* Clear register */
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@ -1257,7 +1257,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
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* Disable beacons and RX/TX queues, wait
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*/
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AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
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AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
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AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
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beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
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ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
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@ -1336,7 +1336,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
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* Re-enable RX/TX and beacons
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*/
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AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
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AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
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AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
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ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
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return 0;
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@ -1387,10 +1387,9 @@
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/*
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* PCU control register
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* PCU Diagnostic register
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*
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* Only DIS_RX is used in the code, the rest i guess are
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* for tweaking/diagnostics.
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* Used for tweaking/diagnostics.
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*/
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#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */
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#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */
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@ -1399,22 +1398,22 @@
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#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */
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#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */
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#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */
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#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */
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#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */
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#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */
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#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */
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#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable HW encryption */
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#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable HW decryption */
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#define AR5K_DIAG_SW_DIS_TX_5210 0x00000020 /* Disable transmit [5210] */
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#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable receive */
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#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
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#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
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AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
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#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */
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#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */
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#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
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#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
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AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
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#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */
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#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */
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#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
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#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
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AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
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#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */
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#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Add 56 bytes of channel info before the frame data in the RX buffer */
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#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
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#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
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AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
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@ -1426,17 +1425,17 @@
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#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */
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#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */
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#define AR5K_DIAG_SW_SCRAM_SEED_S 10
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#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */
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#define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000 /* Disable seqnum increment (?)[5210] */
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#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
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#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
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#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
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AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
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#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */
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#define AR5K_DIAG_SW_OBSPT_S 18
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#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */
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#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */
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#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */
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#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */
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#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000 /* Ignore carrier sense */
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#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000 /* Ignore virtual carrier sense */
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#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000 /* Force channel idle high */
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#define AR5K_DIAG_SW_PHEAR_ME 0x00800000 /* ??? */
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/*
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* TSF (clock) register (lower 32 bits)
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